AE5.0E
FUJITSU SEMICONDUCTOR
DATA SHEET
1
MEMORY Mobile FCRAMTM
CMOS
16M Bit (1M word x 16 bit)
Mobile Phone Application Specific Memory
MB82D01161
-85/-85L/-90/90L
CMOS 1,048,576-WORD x 16 BIT
Fast Cycle Random Access Memory
with Low Power SRAM Interface
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DESCRIPTION
The Fujitsu MB82D01161 is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static
Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format.
This MB82D01161 is suited for low power applications such as Cellular Handset and PDA.
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FEATURES
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PRODUCT LINE
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PACKAGE
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
MB82D01161
85
85L
90
90L
Access Time ( t
AA
Max. & t
CE
Max. )
85ns
90ns
Active Current ( I
DDA1
Max. )
20mA
Stabdby Current ( I
DDS1
Max. )
200
µ
A
100
µ
A
200
µ
A
100
µ
A
Power Down Current ( I
DDP
Max. )
10
µ
A
· Asynchronous SRAM Interface
· 1M word
!
16bit Organization
· Fast Random Cycle Time:
t
RC
= 90ns
· Fast Random Access Time
t
AA
= t
CE
= 85ns (-85), 90ns (-90)
· Low Power Consumption:
I
DDS1
= 200
µ
A, 100
µ
A (L version)
· Wide Operating Conditions:
V
DD
=
+2.3V to +2.7V
+2.7V to +3.1V
+3.1V to +3.5V
T
A
=
-30
o
C to +85
o
C
· Byte Write Control
· Power Down Control by CE2
(BGA-48P-M16) (BGA-48P-M18)
48-pin Plastic FBGA Package
9.00±0.10(.354±.004)
6.00±0.10
(.236±.004)
0.36±0.10
(.014±.004)
.041
.004
+.006
0.10
1.05
INDEX AREA
(Mounting height)
(Stand off)
0 10( 004)
0.20(.008) S
S
(5.60(.220))
(4.00(.157))
0.80(.031)
TYP
0.80(.031)
TYP
6
5
4
3
2
1
H G F
E D C B A
48-Ø0.45±0.10
(48-Ø.018±.004)
M
0.08(.003)
2
MB82D01161
-85/-85L/-90/-90L
(AE5.0E)
Confidential
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PIN ASSIGNMENT
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PIN DESCRIPTION
Pin Name
Description
A
0
to A
19
Address Input
CE1
Chip Enable (Low Active)
CE2
Chip Enable (High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Write Control (Low Active)
UB
Upper Byte Write Control (Low Active)
DQ
1
-
8
Lower Byte Data Input/Output
DQ
9
-
16
Upper Byte Data Input/Output
V
DD
Power Supply
V
SS
Ground
NC
No Connection
(TOP VIEW)
1
2
3
4
5
6
A
A4
A17
UB
CE2
A8
A12
B
A3
A7
LB
WE
A9
A13
C
A2
A6
A18
NC
A10
A14
D
A1
A5
NC
A19
A11
A15
E
A0
DQ1
DQ3
DQ6
DQ8
A16
F
CE1
DQ9 DQ11 DQ13 DQ15
NC
G
OE
DQ10 DQ12
V
DD
DQ14 DQ16
H
V
SS
DQ2
DQ4
DQ5
DQ7
V
SS
(BGA-48P-M16)
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CE2
B
DQ9
UB
A3
A4
CE1
DQ1
C
DQ10 DQ11
A5
A6
DQ2
DQ3
D
V
SS
DQ12
A17
A7
DQ4
V
DD
E
V
DD
DQ13
NC
A16
DQ5
V
SS
F
DQ15 DQ14
A14
A15
DQ6
DQ7
G
DQ16
A19
A12
A13
WE
DQ8
H
A18
A8
A9
A10
A11
NC
(BGA-48P-M18)
Flash Compatible FBGA
(suffix PBT)
SRAM Compatible FBGA
(suffix PBN)
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MB82D01161
-85/-85L/-90/-90L
(AE5.0E)
Confidential
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BLOCK DIAGRAM
A0
to
A19
ADDRESS
LATCH &
BUFFER
ROW
DECODER
MEMORY
CELL
ARRAY
16,777,216 bit
COLUMN /
DECODER
INPUT DATA
LATCH &
CONTROLER
OUTPUT
DATA
CONTROLER
DQ1
to
DQ8
DQ9
to
DQ16
ADDRESS
LATCH &
BUFFER
SENSE /
SWITCH
V
DD
V
SS
LB
OE
CE2
UB
TIMING
CONTROLLER
INPUT /
OUTPUT
BUFFER
CE1
WE
POWER
CONTROL
4
MB82D01161
-85/-85L/-90/-90L
(AE5.0E)
Confidential
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FUNCTION TRUTH TABLE
*1
*1: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
*2: Output Disable condition should not be kept longer than 1
µ
s.
*3: Byte control at Read operation is not supported.
Mode
CE1
CE2
WE
OE
LB
UB
DQ1-8
DQ9-16
I
DD
Data
Retention
Power Down
L
L
X
X
X
X
High-Z
High-Z
I
DDP
No
Standby (Deselect)
H
X
X
X
X
High-Z
High-Z
I
DDS
H
X
X
X
X
Yes
Output Disable
*2
L
H
H
X
X
High-Z
High-Z
I
DDA
Read
*3
L
X
X
Output
Valid
Output
Valid
Write
L
H
L
L
Input
Valid
Input
Valid
Write (Upper Byte)
L
H
Input
Valid
Invalid
Write (Lower Byte)
H
L
Invalid
Input
Valid
5
MB82D01161
-85/-85L/-90/-90L
(AE5.0E)
Confidential
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ABSOLUTE MAXIMUM RATINGS
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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RECOMMENDED OPERATING CONDITIONS
Notes: *1: All voltages are referenced to V
SS
.
*2: Minimum DC voltage on input or I/O pins are -0.3V. During voltage transitions, inputs may negative
overshoot V
SS
to -1.0V for periods of up to 5ns. Maximum DC voltage on input and I/O pins are
V
DD
+0.3V. During voltage transitions, outputs may positive overshoot to V
DD
+1.0V for periods of up
to 5 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their FUJITSU representatives beforehand.
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PACKAGE PIN CAPACITANCE
Note: Test conditions T
A
= 25°C, f = 1.0 MHz
Parameter
Symbol
Value
Unit
Voltage of V
DD
Supply Relative to V
SS
V
DD
-0.5 to +3.6
V
Voltage at Any Pin Relative to V
SS
V
IN
, V
OUT
-0.5 to +3.6
V
Short Circuit Output Current
I
OUT
+
50
mA
Storage Temperature
T
STG
-55 to +125
o
C
Parameter
Notes
Symbol
Min.
Max.
Unit
Supply Voltage
V
DD (31)
3.1
3.5
V
V
DD (27)
2.7
3.1
V
*1
V
DD (23)
2.3
2.7
V
V
SS
0
0
V
High Level Input Voltage
*1,*2
V
IH (31)
2.6
V
DD
+0.3
and
3.6V
V
V
IH (27)
2.3
V
DD
+0.3
V
V
IH (23)
2.0
V
DD
+0.3
V
Low Level Input Voltage
*1,*2
V
IL
-0.3
0.4
V
Ambient Temperature
T
A
-30
85
°
C
Symbol
Description
Test Setup
Typ.
Max.
Unit
C
IN1
Address Input Capacitance
V
IN
= 0V
--
5
pF
C
OUT
Output Capacitance
V
OUT
= 0V
--
8
pF
C
IN2
Control Pin Capacitance
V
IN
= 0V
--
5
pF
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