AE1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
2
×
512 K
×
16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F161622C-60/-70/-80/-80L
CMOS 2-Bank
×
524,288-Word
×
16 Bit
Synchronous Dynamic Random Access Memory
s
DESCRIPTION
The Fujitsu MB81F161622C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
16,777,216 memory cells accessible in an 16-bit format. The MB81F161622C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F161622C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F161622C is ideally suited for laser printers, high resolution graphic adapters, accelerators and other
applications where an extremely large memory and bandwidth are required and where a simple interface is
needed.
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PRODUCT LINE & FEATURES
Parameter
MB81F161622C
Reference Spec
(100MHz @CL=3)
-60
-70
-80/-80L
CL - t
RCD
- t
RP
3 - 3 - 3 clk min.
3 - 3 - 3 clk min.
3 - 3 - 3 clk min.
3 - 3 - 3 clk min.
Clock Frequency (CL = 3)
167 MHz max.
143 MHz max.
125 MHz max.
100 MHz max.
Burst Mode Cycle Time (CL = 3)
6.0 ns min.
7.0 ns min.
8.0 ns min.
10 ns min.
Access Time From Clock (CL = 3)
5.5 ns max.
6 ns max.
6 ns max.
6 ns max.
Operating Current
150 mA max.
130 mA max.
110 mA max.
90 mA max.
Power Down Mode Current (I
CC2P
)
1 mA max.
1 mA max.
1 mA max.
1 mA max.
Self Refresh Mode Current (I
CC6
)
1 mA max.
1 mA max.
1 mA / 400 µA max.
1 mA max.
· Single +3.3 V Supply: +0.3 V /
-
0.15 V tolerance (-60)
±
0.3 V tolerance (-70/-80/-80L)
· LVTTL compatible I/O interface
· 4 K refresh cycles every 64 ms
· Dual banks operation
· Burst read/write operation and burst
read/single write operation capability
· Byte control by DQMU/DQML
· Programmable burst type, burst length,
and CAS latency
· Auto-and Self-refresh (every 15.6
µ
s)
· CKE power down mode
· Output Enable and Input Data Mask
· 167 MHz/143MHz/125 MHz clock frequency
2
MB81F161622C-60/-70/-80/-80L
Preliminary (AE1E)
s
PACKAGE
Package and Ordering Information
50-pin plastic (400 mil) TSOP-II with normal bend leads, order as MB81F161622C-
××
FN (Std. power)
/-
××
LFN (Low power)
50-pin plastic TSOP (II)
(FPT-50P-M05)
(Normal Bend)
Marking side
3
MB81F161622C-60/-70/-80/-80L
Preliminary (AE1E)
s
PIN ASSIGNMENTS AND DESCRIPTIONS
44
43
42
41
40
39
38
37
36
35
50
49
48
47
46
45
34
33
32
31
30
29
V
CC
DQ
0
DQ
1
V
SSQ
DQ
2
DQ
3
V
CCQ
DQ
4
DQ
5
V
SSQ
DQ
6
DQ
7
V
CCQ
DQML
WE
CAS
RAS
CS
A
11
A
10
/AP
A
0
A
1
A
2
A
3
V
CC
V
SS
DQ
15
DQ
14
V
SSQ
DQ
13
DQ
12
V
CCQ
DQ
11
DQ
10
V
SSQ
DQ
9
DQ
8
V
CCQ
DU
DQMU
CLK
CKE
DU
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
17
18
19
20
21
22
<Normal Bend: FPT-50P-M05>
(TOP VIEW)
50-Pin TSOP (II)
(Marking side)
* : These pins are connected internally in the chip.
Pin Number
Symbol
Description
1, 7, 13, 25, 38, 44
V
CC
, V
CCQ
Supply Voltage
2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42,
43, 45, 46, 48, 49
DQ
0
to DQ
15
Data I/O
· Lower Byte: DQ
0
to DQ
7
· Upper Byte: DQ
8
to DQ
15
4, 10, 26, 41, 47, 50
V
SS
, V
SSQ
*
Ground
33, 37
DU
Don't use (leave open)
15
WE
Write Enable
16
CAS
Column Address Strobe
17
RAS
Row Address Strobe
18
CS
Chip Select
19
A
11
(BA)
Bank Select
20
AP
Auto Precharge Enable
20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32
A
0
to A
10
Address
Input
· Row:
A
0
to A
10
· Column:
A
0
to A
7
34
CKE
Clock Enable
35
CLK
Clock Input
14, 36
DQML, DQMU
Input Mask/Output Enable
28
27
26
23
24
25
4
MB81F161622C-60/-70/-80/-80L
Preliminary (AE1E)
s
BLOCK DIAGRAM
BANK-1
V
CC
V
SS
/V
SSQ
CLK
CKE
A
0
to A
11
,
AP
DQ
0
to
DQ
15
COMMAND
DECODER
ADDRESS
BUFFER/
REGISTER
I/O DATA
BUFFER/
REGISTER
MODE
REGISTER
COLUMN
ADDRESS
COUNTER
RAS
DRAM
CORE
(2,048
×
256
×
16)
COL.
ADDR.
RAS
CAS
WE
CS
BANK-0
I/O
ROW
ADDR.
To each block
CONTROL
SIGNAL
LATCH
Fig. 1 - MB81F161622C BLOCK DIAGRAM
DQML
V
CCQ
CAS
WE
DQMU
CLOCK
BUFFER
5
MB81F161622C-60/-70/-80/-80L
Preliminary (AE1E)
s
FUNCTIONAL TRUTHAL TABLE
(Note 1)
COMMAND TRUTH TABLE Notes 2,3,4
Notes: *1.
V = Valid, L = Logic Low, H = Logic High, X = either L or H
*2.
All commands assume no CSUS command on previous rising edge of clock.
*3.
All commands are assumed to be valid state transitions.
*4.
All inputs are latched on the rising edge of clock.
*5.
NOP and DESL commands have the same effect on the part.
*6.
READ, READA, WRIT, and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7.
ACTV command should only be asserted after corresponding bank has been precharged (PRE or PALL
command).
*8.
Required after power up.
*9.
MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
Function
Notes Symbol
CKE
CS
RAS CAS
WE
A
11
(BA)
A
10
(AP)
A
9
, A
8
A
7
to
A
0
n-1
n
Device Deselect
*5
DESL
H
X
H
X
X
X
X
X
X
X
No Operation
*5
NOP
H
X
L
H
H
H
X
X
X
X
Burst Stop
BST
H
X
L
H
H
L
X
X
X
X
Read
*6
READ
H
X
L
H
L
H
V
L
X
V
Read with Auto-precharge
*6 READA
H
X
L
H
L
H
V
H
X
V
Write
*6
WRIT
H
X
L
H
L
L
V
L
X
V
Write with Auto-precharge
*6 WRITA
H
X
L
H
L
L
V
H
X
V
Bank Active (RAS) *7
ACTV
H
X
L
L
H
H
V
V
V
V
Precharge Single Bank
PRE
H
X
L
L
H
L
V
L
X
X
Precharge All Banks
PALL
H
X
L
L
H
L
X
H
X
X
Mode Register Set
*8,9
MRS
H
X
L
L
L
L
L
L
V
V
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