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Part Number FA3687V

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FA3687V
1
s
Block diagram
FA3687V
s
Dimensions, mm
TSSOP-16
s
Description
FA3687V is a PWM type DC-to-DC converter control IC with
2ch outputs that can directly drive power MOSFETs. CMOS
devices with high breakdown voltage are used in this IC and
low power consumption is achieved. This IC is suitable for very
small DC-to-DC converters because of their small and thin
package (1.1mm max.), and high frequency operation (up to
1.5MHz). You can select Pch or Nch of MOSFETs driven, and
design any topology of DC-to-DC converter circuit like a buck, a
boost, inverting, a fly-back, or a forward.
s
Features
· Wide range of supply voltage: V
CC
=2.5 to 20V
· MOSFET direct driving
· Selectable output stage for Pch/Nch MOSFET on each
channel
· Low operating current by CMOS process: 2.5mA (typ.)
· 2ch PWM control IC
· High frequency operation: 300kHz to 1.5MHz
· Simple setting of operation frequency by timing resistor
· Soft start function at each channel
· Adjustable maximum duty cycle at each channel
· Built-in undervoltage lockout
· High accuracy reference voltage: V
REF
: 1.00V±1%
V
REG
: 2.20V±1%
· Adjustable built-in timer latch for short-circuit protection
· Thin and small package: TSSOP-16
CMOS IC
For Switching Power Supply Control
Pin No. Pin symbol Description
1
CP
Timer latched short circuit protection
2
SEL2
Selection of type of driven MOSFET (OUT2)
3
FB2
Ch.2 output of error amplifier
4
IN2­
Ch.2 inverting input to error amplifier
5
IN2+
Ch.2 non-inverting input to error amplifier
6
VCC
Power supply
7
CS2
Soft start for Ch.2
8
OUT2
Ch.2 output
9
OUT1
Ch.1 output
10
CS1
Soft start for Ch.1
11
GND
Ground
12
RT
Oscillator timing resistor
13
VREG
Regulated voltage output
14
IN1­
Ch.1 inverting input to error amplifier
15
FB1
Ch.1 output of error amplifier
16
SEL1
Selection of type of driven MOSFET (OUT1)
1
8
9
16
0
~
8
°
0.65
6.4
±
0.2
0
.
1
0
5

t
o
0
.
1
4
5
4.4
5
0.22
±
0.02
0.5
±
0.08
1.1max
0.10
±
0.05
FA3687V
2
Maximum power dissipation curve
s
Recommended operating condition
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Supply voltage
V
CC
2.5
18
V
CS1, CS2, CP pin voltage
V
CTR_IN
0.0
2.5
V
SEL1, SEL2 pin voltage
V
SEL_IN
0.0
2.5
V
IN1­, IN2­, IN2+ pin voltage
V
EA_IN
0.0
2.5
V
Oscillation frequency
f
OSC
300
500
1500
kHz
VREG pin capacitance
C
REG
Vcc<10V
0.1
1.0
4.7
µF
10V Vcc<18V
0.47
1.0
4.7
µF
VREG pin current
I
REG
1.0
mA
VCC pin capacitance
C
VCC
1.0
µF
CS1 pin capacitance
C
CS1
Between CS1 and GND
0.01
µF
CS2 pin capacitance
C
CS2
Between CS2 and VREG
0.01
µF
CP pin capacitance
C
CP
Between CP and VREG *
0.01
µF
* If the timer latched mode is not needed, connect the CP pin to GND.
0
50
100
150
200
250
300
350
-30
0
30
60
90
120
150
Ambient temperature [°C]
Maximun power dissipation [mW]
s
Absolute maximum ratings
I
tem
Symbol
Rating
Unit
Power supply voltage
V
CC
20
V
SEL1, SEL2 pin voltage
V
SEL
­0.3 to 5.0
V
FB1, IN1­, FB2, IN2­, IN2+ pin voltage
V
EA_IN
­0.3 to 5.0
V
CS1, CS2, CP, RT, VREG pin voltage
V
CTR_IN
­0.3 to 5.0
V
OUT1/2
OUT pin source current
I
OUT­
­400 (peak)
mA
OUT pin sink current
I
OUT+
150 (peak)
mA
OUT1/2
OUT pin source current
I
OUT­
­50 (continuous) mA
OUT pin sink current
I
OUT+
50 (continuous)
mA
Power dissipation *
P
d
300 (Ta 25°C)
mW
Operating junction temperature
T
J
+125
°C
Operating ambient temperature
T
OPR
­30 to +85
°C
Storage temperature
T
STG
­40 to +125
°C
* Derating factor Ta 25°C: 3mW/°C
s
Electrical characteristics (V
CC
=3.3V, C
REG
=1.0µF, R
T
=12k
, Ta=+25°C)
Regulated voltage for internal control blocks (V
REG
pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Regulated voltage
V
REG
2.178
2.200
2.222
V
Line regulation
V
REG_LINE
V
CC
=2.5 to 18V
±5
±15
mV
Load regulation
V
REG_LOAD
I
REG
=0 to 1mA
­5
­1
mV
Variation with temperature
V
REG_TC
Ta= ­30 to +85°C
±0.5
%
Oscillator section (R
T
pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Oscillation frequency
f
OSC
435
500
565
kHz
Line regulation
f
OSC_LINE
V
CC
=2.5 to 18V
±1
±5
%
Variation with temperature
f
OSC_TC1
Ta= ­30 to +85°C
±3
%
FA3687V
3
Soft start section (CS1, CS2 pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Threshold voltage (CS1)
V
CS1D0N
Duty cycle=0%, V
FB1
=1.4V
0.82
V
(Driving Nch-MOSFET)
V
CS1D20N
Duty cycle=20%, V
FB1
=1.4V
0.89
0.925
0.96
V
V
CS1D80N
Duty cycle=80%, V
FB1
=1.4V
1.25
1.285
1.32
V
V
CS1D100N
Duty cycle=100%, V
FB1
=1.4V
1.38
V
Threshold voltage (CS1)
V
CS1D0P
Duty cycle=0%, V
FB1
=1.4V
0.82
V
(Driving Pch-MOSFET)
V
CS1D20P
Duty cycle=20%, V
FB1
=1.4V
0.90
0.935
0.97
V
V
CS1D80P
Duty cycle=80%, V
FB1
=1.4V
1.26
1.295
1.33
V
V
CS1D100P
Duty cycle=100%, V
FB1
=1.4V
1.38
V
Threshold voltage (CS2)
V
CS2D0N
Duty cycle=0%, V
FB2
=0.7V
1.33
V
(Driving Nch-MOSFET)
V
CS2D20N
Duty cycle=20%, V
FB2
=0.7V
1.21
1.245
1.28
V
V
CS2D80N
Duty cycle=80%, V
FB2
=0.7V
0.85
0.885
0.92
V
V
CS2D100N
Duty cycle=100%, V
FB2
=0.7V
0.80
V
Threshold voltage (CS2)
V
CS2D0P
Duty cycle=0%, V
FB2
=0.7V
1.33
V
(Driving Pch-MOSFET)
V
CS2D20P
Duty cycle=20%, V
FB2
=0.7V
1.20
1.23
1.27
V
V
CS2D80P
Duty cycle=80%, V
FB2
=0.7V
0.84
0.875
0.91
V
V
CS2D100P
Duty cycle=100%, V
FB2
=0.7V
0.80
V
Error amplifier section (IN1­, FB1, IN2­, IN2+, FB2 pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Reference voltage (ch.1)
V
REF1
*
0.99
1.00
1.01
V
V
REF1
Line regulation (ch.1)
V
REF_LINE
V
CC
=2.5 to 18V
±2
±5
mV
V
REF1
Variation with temperature (ch.1)
V
REF_TC1
Ta= ­30 to +85°C
±0.5
%
Input offset voltage (ch.2)
V
OFFSET
V
IN2+
=1.0V, IN2+, IN2­
±10
mV
V
OFFSET
Line regulation (ch.2)
V
OFF_LINE
V
CC
=2.5 to 18V
0
mV
Input bias current
I
IN­
VINx­ =0.0 to 2.5V
0.0
mA
Common mode input voltage
V
COM
IN2+, IN2­
0.7
1.5
V
Open loop gain
A
VO
70
dB
Unity gain bandwidth
f
T
1.5
MHz
Output current (sink)
I
SIFB
V
FB1
=0.5V, V
IN1­
=V
REG
2.3
3.5
4.7
mA
V
FB2
=0.5V, V
IN2­
=V
REG
, V
IN2+
=1V
Output current (source)
I
SOFB
V
FB1
=V
REG­
0.5V, V
IN1­
=0V
­360
­270
­180
µA
V
FB2
=V
REG­
0.5V, V
IN2­
=0V, V
IN2+
=1V
* The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of the error amplifier is included.
Pulse width modulation (PWM) section (FB1, FB2 pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Threshold voltage (FB1)
V
FB1D0N
Duty cycle=0%, V
CS1
=V
REG
0.82
V
(Driving Nch-MOSFET)
V
FB1D20N
Duty cycle=20%, V
CS1
=V
REG
0.925
V
V
FB1D80N
Duty cycle=80%, V
CS1
=V
REG
1.285
V
V
FB1D100N
Duty cycle=100%, V
CS1
=V
REG
1.38
V
Threshold voltage (FB1)
V
FB1D0P
Duty cycle=0%, V
CS1
=V
REG
0.82
V
(Driving Pch-MOSFET)
V
FB1D20P
Duty cycle=20%, V
CS1
=V
REG
0.935
V
V
FB1D80P
Duty cycle=80%, V
CS1
=V
REG
1.295
V
V
FB1D100P
Duty cycle=100%, V
CS1
=V
REG
1.38
V
Threshold voltage (FB2)
V
FB2D0N
Duty cycle=0%, V
CS2
=0V
1.33
V
(Driving Nch-MOSFET)
V
FB2D20N
Duty cycle=20%, V
CS2
=0V
1.245
V
V
FB2D80N
Duty cycle=80%, V
CS2
=0V
0.885
V
V
FB2D100N
Duty cycle=100%, V
CS2
=0V
0.80
V
Threshold voltage (FB2)
V
FB2D0P
Duty cycle=0%, V
CS2
=0V
1.33
V
(Driving Pch-MOSFET)
V
FB2D20P
Duty cycle=20%, V
CS2
=0V
1.235
V
V
FB2D80P
Duty cycle=80%, V
CS2
=0V
0.875
V
V
FB2D100P
Duty cycle=100%, V
CS2
=0V
0.80
V
FA3687V
4
Overall section
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Operating mode supply current
I
CCA
Ch.1, Ch.2 operating mode
2.5
3.5
mA
I
CCA1
Ch.1, Ch.2 off mode
2.0
mA
I
CCA2
Ch.1, Ch.2 operating mode, Vcc=18V
3.0
mA
I
CCA3
Latch mode
2.0
mA
Undervoltage lockout circuit section (VCC pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
ON threshold voltage of VCC
V
UVLO
2.0
2.2
2.35
V
Hysteresis voltage
V
UVLO
0.1
V
*
1
The current source of the CP pin operates when the voltage of FB1 exceeds the threshold voltage as shown in the table.
*
2
The current source of the CP pin operates when the voltage of FB2 falls below the threshold voltage as shown in the table.
*
3
The timer latch of FB1 is disabled when the CS1 voltage is below the threshold voltage as shown in the table.
*
4
The timer latch of FB2 is disabled when the CS2 voltage is above the threshold voltage as shown in the table.
Timer latch protection section (CS pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Threshold voltage of FB1
V
THFB1TL
*
1
1.5
2.0
V
Threshold voltage of FB2
V
THFB2TL
*
2
0.2
0.6
V
Threshold voltage of CS1
V
THFB3TL
*
3
0.2
0.6
V
Threshold voltage of CS2
V
VTHCS1TL
*
4
1.5
2.0
V
Charge current of CP
I
CP
V
CP
=0.5V, V
FB1
=2.1V
­2.4
­2.0
­1.5
µA
Threshold voltage of CP
V
THCPTL
1.6
2.1
V
Output section (OUT1, OUT2, SEL1, SEL2 pin)
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
High side on resistance of OUT1/2
R
ONHI
I
OUT2
= ­50mA
10
20
I
OUT1
= ­50mA, V
CC
=5V
9
I
OUT1
= ­50mA, V
CC
=15V
8
Low side on resistance of OUT1/2
R
ONLO
I
OUT1
=50mA
5
10
I
OUT2
=50mA, V
CC
=5V
5
I
OUT2
=50mA, V
CC
=15V
5
Rise time of OUT1/2
t
RISE
C
L
=1000pF
25
ns
Fall time of OUT1/2
t
FALL
C
L
=1000pF
40
ns
SEL pin voltage for driving Nch-MOSFET
V
SELN
0.0
0.2
V
SEL pin voltage for driving Pch-MOSFET
V
SELP
V
REG-0.2
V
REG
V
FA3687V
5
s
Characteristic curves
Oscillation frequency vs. timing resistor
Oscillation frequency vs. supply voltage V
CC
V
CC
=3.3V, Ta=25°C
Ta=25°C, R
T
=12k
(f
OSC
=500kHz)
Oscillation frequency vs. ambient temperature
Regulated voltage vs. supply voltage V
CC
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
Ta=25°C, R
T
=12k
(f
OSC
=500kHz)
Regulated voltage vs. ambient temperature
Regulated voltage vs. load current
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
0
200
400
600
800
1000
1200
1400
1600
1800
1
10
100
Timing resistor R
T
[k
]
Oscillation frequency [kHz]
490
492
494
496
498
500
502
504
506
508
510
0
5
10
15
20
Vcc [V]
Oscillation frequency [kHz]
430
450
470
490
510
530
550
570
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Oscillation frequency [kHz]
2.17
2.18
2.19
2.20
2.21
2.22
2.23
0
5
10
15
20
Vcc [V]
Regulated voltage V
REG
[V]
Load current
I
REG
=0A
2.17
2.18
2.19
2.20
2.21
2.22
2.23
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Regulated voltage V
REG
[V]
2.17
2.18
2.19
2.20
2.21
2.22
2.23
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Load current I
REG
[mA]
Regulated voltage V
REG
[V]
Ta=­30°C
Ta=25°C
Ta=85°C
FA3687V
6
Reference voltage vs. supply voltage VCC
Reference voltage vs. ambient temperature
Ta=25°C, R
T
=12k
(f
OSC
=500kHz)
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
Error amp. output current (sink) vs. ambient temperature
Error amp. output current (source) vs. ambient temperarure
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
Charge current of CP vs. ambient temperature
Threshold voltage of CP vs. ambient temperature
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0
5
10
15
20
25
Vcc [V]
Reference voltage V
REF
[V]
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Reference voltage V
REF
[V]
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Output current (sink) I
SIFB
[mA]
-350
-300
-250
-200
-150
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Output current (source) I
SOFB
[uA]
-3.0
-2.5
-2.0
-1.5
-1.0
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Charge current of CP [uA]
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Threshold voltage of CP [V]
FA3687V
7
Output duty cycle vs. Cs voltage (ch. 1)
Output duty cycle vs. oscillation frequency (ch. 1)
Driving Nch MOSFET
Driving Nch MOSFET
V
CC
=3.3V, Ta=25°C
V
CC
=3.3V, Ta=25°C
Output duty cycle vs. Cs voltage (ch. 1)
Output duty cycle vs. oscillation frequency (ch. 1)
Driving Nch MOSFET
Driving Nch MOSFET
V
CC
=3.3V, Ta=25°C
V
CC
=3.3V, Ta=25°C
0
10
20
30
40
50
60
70
80
90
100
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
V
CS1
[V]
Output duty cycle (ch.1) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Output duty cycle (ch.1) [%]
VCS1=0.85V
VCS1=1.35V
VCS1=0.90V
VCS1=0.95V
VCS1=1.00V
VCS1=1.05V
VCS1=1.10V
VCS1=1.15V
VCS1=1.20V
VCS1=1.25V
VCS1=1.30V
0
10
20
30
40
50
60
70
80
90
100
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
V
CS1
[V]
Output duty cycle (ch.1) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Output duty cycle (ch.1) [%]
VCS1=1.35V
VCS1=1.30V
VCS1=1.25V
VCS1=1.20V
VCS1=1.15V
VCS1=1.10V
VCS1=1.05V
VCS1=1.00V
VCS1=0.95V
VCS1=0.90V
VCS1=0.85V
FA3687V
8
Output duty cycle vs. Cs voltage (ch. 2)
Output duty cycle vs. oscillation frequency (ch. 2)
Driving Nch MOSFET
Driving Nch MOSFET
V
CC
=3.3V, Ta=25°C
V
CC
=3.3V, Ta=25°C
Output duty cycle vs. Cs voltage (ch. 2)
Output duty cycle vs. oscillation frequency (ch. 2)
Driving Nch MOSFET
Driving Nch MOSFET
V
CC
=3.3V, Ta=25°C
V
CC
=3.3V, Ta=25°C
0
10
20
30
40
50
60
70
80
90
100
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
V
CS2
[V]
Output duty cycle (ch.2) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Output duty cycle (ch.2) [%]
VCS2=0.85V
VCS2=0.90V
VCS2=0.95V
VCS2=1.00V
VCS2=1.05V
VCS2=1.10V
VCS2=1.15V
VCS2=1.20V
VCS2=1.25V
VCS2=1.30V
VCS2=0.80V
0
10
20
30
40
50
60
70
80
90
100
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
V
CS2
[V]
Output duty cycle (ch.2) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Output duty cycle (ch.2) [%]
VCS2=0.85V
VCS2=0.90V
VCS2=0.95V
VCS2=1.00V
VCS2=1.05V
VCS2=1.10V
VCS2=1.15V
VCS2=1.20V
VCS2=1.25V
VCS2=1.30V
VCS2=0.80V
FA3687V
9
OUT1 terminal source current vs. H level output voltage
OUT2 terminal source current vs. H level output voltage
Ta=25°C
Ta=25°C
OUT1 terminal sink current vs. H level output voltage
OUT2 terminal sink current vs. H level output voltage
V
CC
=3.3V
V
CC
=3.3V
OUT1 terminal sink current vs. H level output voltage
OUT2 terminal sink current vs. H level output voltage
V
CC
=12V
V
CC
=12V
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Vcc ­VOUT1 [V]
IOUT1 [mA]
Vcc=2.5V
Vcc= 3V
Vcc= 5V
Vcc=12V
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
0.0
1.0
2.0
3.0
4.0
5.0
Vcc ­VOUT2 [V]
IOUT2 [mA]
Vcc=2.5V
Vcc= 3V
Vcc= 5V
Vcc=12V
-300
-250
-200
-150
-100
-50
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Vcc ­VOUT1 [V]
IOUT1 [mA]
Ta= ­30°C
Ta=25°C
Ta=85°C
-300
-250
-200
-150
-100
-50
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Vcc ­VOUT2 [V]
IOUT2 [mA]
Ta= ­30°C
Ta=85°C
Ta=25°C
-500
-400
-300
-200
-100
0
0.0
1.0
2.0
3.0
4.0
5.0
Vcc ­VOUT1 [V]
IOUT1 [mA]
Ta=85°C
Ta= ­30°C
Ta=25°C
-500
-400
-300
-200
-100
0
0.0
1.0
2.0
3.0
4.0
5.0
Vcc ­VOUT2 [V]
IOUT2 [mA]
Ta= ­30°C
Ta=25°C
Ta=85°C
FA3687V
10
OUT1 terminal sink current vs. L level voltage
OUT2 terminal sink current vs. L level voltage
OUT1 terminal rise time vs. supply voltage V
CC
OUT2 terminal rise time vs. supply voltage V
CC
C
L
=1000pF
C
L
=1000pF
OUT1 terminal fall time vs. supply voltage V
CC
OUT2 terminal fall time vs. supply voltage V
CC
C
L
=1000pF
C
L
=1000pF
0
50
100
150
200
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOUT1 [V]
IOUT1 [mA]
Ta= ­30°C
Ta=25°C
Ta=85°C
0
50
100
150
200
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOUT2 [V]
IOUT2 [mA]
Ta= ­30°C
Ta=85°C
Ta=25°C
0
10
20
30
40
50
60
0
5
10
15
20
Vcc [V]
OUT1 terminal rise time t
RISE
[ns]
Ta= ­30°C
Ta=25°C
Ta=85°C
0
10
20
30
40
50
60
0
5
10
15
20
Vcc [V]
OUT2 terminal rise time t
RISE
[ns]
Ta= ­30°C
Ta=25°C
Ta=85°C
0
50
100
150
200
0
5
10
15
20
Vcc [V]
OUT1 terminal fall time t
FALL
[ns]
Ta= ­30°C
Ta=25°C
Ta=85°C
0
50
100
150
200
0
5
10
15
20
Vcc [V]
OUT2 terminal fall time t
FALL
[ns]
Ta=25°C
Ta= ­30°C
Ta=85°C
FA3687V
11
Operating mode supply current vs. oscillation frequency
UVLO ON threshold vs. ambient temperature
Ta=25°C
CS1 internal discharge switch current vs. voltage
CS2 internal discharge switch current vs. voltage
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
V
CC
=3.3V, R
T
=12k
(f
OSC
=500kHz)
Error amplifier gain and phase vs. frequency
2.0
3.0
4.0
5.0
6.0
300
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Operating mode supply current I
CCA
[mA]
Vcc=2.5V
Vcc=18V
Vcc=12V
Vcc=5V
Vcc=3.3V
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
-50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
UVLO ON threshold V
UVLO
[V]
0
50
100
150
200
250
300
350
400
0.00
0.50
1.00
1.50
2.00
2.50
VCS1 [V]
ICS1off [
µ
A]
Ta= ­30°C
Ta=25°C
Ta=85°C
-200
-150
-100
-50
0
0.00
0.50
1.00
1.50
2.00
V
REG
­VCS2 [V]
ICS2 off [
µ
A]
Ta= ­30°C
Ta=25°C
Ta=85°C
FA3687V
12
s
Description of each circuit
1. Reference voltage circuit (V
REF
)
This circuit generates the reference voltage of 1.00V±1%
compensated in temperature from V
CC
voltage, and is
connected to the non-inverting input of the error amplifier. The
voltage cannot be observed directly because there is no
external pin for this purpose.
2. Regulated voltage circuit (V
REG
)
This circuit generates 2.20V±1% based on the reference
voltage V
REF
, and is used as the power supply of the internal IC
circuits. The voltage is generated when the supply voltage, V
CC
is input. The V
REG
voltage is also used as a regulated power
supply for soft start, maximum duty cycle limitation, and others.
The output current for external circuit should be within 1mA. A
capacitor connected between VREG pin and GND pin is
necessary to stabilize the V
REG
voltage (To determine
capacitance, refer to recommended operating conditions). The
V
REG
voltage is regulated in V
CC
voltage of 2.4V or above.
3. Oscillator
The oscillator generates a triangular waveform by charging and
discharging the built-in capacitor. A desired oscillation
frequency can be set by the value of the resistor connected to
the RT pin (Fig. 1). The built-in capacitor voltage oscillates
between approximately 0.82V and 1.38V at fosc=500kHz (that
of ch1 and ch2 are slightly different) with almost the same
charging and discharging gradients (Fig. 2).
You can set the desired oscillation frequency by changing the
gradients using the resistor connected to the RT pin (Large RT:
Low frequency, Small RT: High frequency). The oscillator
waveform cannot be observed from the outside because a pin
for this purpose is not provided. The RT pin voltage is
approximately 1V DC in normal operation. The oscillator output
is connected to the PWM comparator.
4. Error amplifier circuit
The error amplifier 1 has the inverting input of IN1(­) pin
(Pin14). The non-inverting input is internally connected to the
reference voltage V
REF
(1.00V±1%; 25°C). The error amplifier 2
has the inverting input IN2(­) pin (Pin4) and non-inverting input
IN2(+) pin (Pin5) externally. Since each input of error amplifier
2 is connected to the pins, CH2 is suitable for any circuit
topology. The FB pins (Pin3, Pin15) are the output of the error
amplifier. An external RC network is connected between FB pin
and IN­pin for gain and phase compensation setting. (Fig. 3)
For connecting of each topology, see "Design advice".
Fig. 1
Fig. 2
Fig. 3
12
OSC
R
T
R
T
R
T
value:Small
R
T
value:Large
0.82V
1.38V
+
14
15
5
4
3
13
IN1-
VREG
IN2+
IN2-
FB2
FB1
Comp
Comp
Vout1
Vout2
R
NF
1
R
NF2
V
REF
(1.0V)
R1
R2
R3
R4
R5
R6
Er. Amp.1
Er. Amp.2
FA3687V
13
5. PWM comparator
The PWM output generates from the oscillator output, the error
amplifier output (FB1, FB2) and CS voltage (CS1, CS2) (Fig. 4).
The oscillator output is compared with the preferred lower
voltage between FB1 and CS1 for ch1. While the preferred
voltage is lower than oscillator output, the PWM output is low.
While the preferred voltage is higher than oscillator output, the
PWM output is high. Since the phase of Ch2 is the opposite
phase of Ch1, higher voltage between FB2 and CS2 is
preferred and while the preferred voltage is lower than the
oscillator output, the PWM output 2 is high. (Cannot be
observed externally) The output polarity of OUT1, OUT2
changes according to the condition of SEL pin. (See Fig. 6)
6. Soft start function
This IC has a soft start function to protect DC-to-DC converter
circuits from damage when starting operation. CS1 pin (Pin10),
and CS2 pin (Pin7) are used for soft start function of ch1 and
ch2 respectively (Fig. 5). When the supply voltage is applied to
the VCC pin and UVLO is cancelled, capacitor C
CS1
and C
CS2
is charged by VREG through the resistor R7 or R9. Therefore,
CS1 voltage gradually increases and CS2 voltage gradually
decreases. Since CS1 and CS2 pin are connected to the PWM
comparator internally, the pulses gradually widen and then the
soft start function operates (Fig. 6).
The maximum duty cycle can be set by using the CS pins.
(See "Design advice" about the detail)
Fig. 4
Fig. 5
Fig. 6
N/P ch.
drive
N/P ch.
drive
UVLO
Oscillator
output
CS1
CS2
FB2
FB1
OUT1
OUT2
PWM
Comp.1
PWM
Comp.2
PWM output1
9
8
SEL1
16
SEL2
2
PWM output2
13
10
CS1
VREG
C
CS1
R7
13
7
VREG
CS2
R9
C
CS2
Oscillator output
CS1 pin voltage
Er. Amp.1 output
PWM
output 1
OUT1
Pch.drive
(SEL1:VREG)
OUT1
Nch.drive
(SEL1:GND)
Oscillator output
CS2 pin voltage
Er. Amp.2 output
PWM
output2
OUT2
Pch.drive
(SEL2:VREG)
OUT2
Nch.drive
(SEL2:GND)
FA3687V
14
7. Timer latch short-circuit protection circuit
This IC has the timer latch short-circuit protection circuit. This
circuit cuts off the output of all channels when the output
voltage of DC-to-DC converter drops due to short circuit or
overload. To set delay time for timer latch operation, a capacitor
C
CP
should be connected to the CP pin (Fig. 7). When one of
the output voltage of the DC-to-DC converter drops due to short
circuit or overload, the FB1 pin voltage increases up to around
the V
REG
voltage for ch1, or the FB2 pin voltage drops down to
around 0V for ch2. When FB1 pin voltage exceeds 2.0V (max.)
or FB2 pin voltage falls below 0.2V (min.), constant-current
source (2µA typ.) starts charging the capacitor C
CP
connected
to the CP pin. If the voltage of the CP pin exceeds 2.1 V (max.),
the circuit regards the case as abnormal. Then the IC is set to
off latch mode and the output of all channels is shut off (Fig. 8),
and the current consumption becomes 2mA (typ.). The period
(tp) between the occurrence of short-circuit in the converter
output and setting to off latched mode can be calculated by the
following equation:
You can reset off latched mode of the short-circuit protection by
either of the following ways about 1) CP pin, or 2) VCC pin, or
3) CS1or CS2 pin:
1) CP voltage = 0V
2) V
CC
voltage U
VLO
voltage (2.2V typ.) or below
3) Set the CS pin of the cause of off latched mode as follows
CS1 pin voltage = 0V, CS2 pin voltage = V
REG
If the timer-latched mode is not necessary, connect the CP pin
to GND.
8. Output circuit
The IC contains a push-pull output stage and can directly drive
MOSFETs. The maximum peak current of the output stage is
sink current of +150mA, and source current of ­400mA. The IC
can also drive NPN and PNP transistors. The maximum current
in such cases is ±50mA. You must design the output current
considering the rating of power dissipation. (See "Design
advice')
You can switch the types of external discrete MOSFETs by
wiring of the SEL pins (Pin 2, Pin 16). For driving Nch MOS,
connect the SEL pins to GND. For driving Pch MOS, connect
the SEL pins to VREG. You can design buck converter or
inverting converter by driving Pch MOS, and boost converter by
driving Nch MOS.
Connect them either to GND or to VREG surely.
9. Undervoltage lockout circuit
The IC contains a undervoltage lockout circuit to protect the
circuit from the damage caused by malfunctions when the
supply voltage drops. When the supply voltage rises from 0V,
the IC starts to operate at V
CC
of 2.2V (typ.) and outputs
generate pulses. If a drop of the supply voltage occurs, it stops
output at V
CC
of 2.1V (typ.). When it occurs, the CS1 pin is
turned to low level and the CS2 pin to high level, and then these
pins are reset.
Fig. 7
Fig. 8
V
THCPTL
: CP pin latched mode threshold voltage [V]
I
CP
:
CP charge source current [µA]
C
CP
:
Capacitance of CP pin capacitor
1
CP
C
CP
Icp
Vcp
CP pin voltage [V]
1.0
2.0
Time t
Start-up
Momentary short
circuit
Short circuit
Short circuit
protection
tp
2.1V (max)
VREG pin voltag
tp [s] = C
CP
V
THCPTL
I
CP
FA3687V
15
s
Design advice
1. Setting the oscillation frequency
As described in item 1 of "Description of each circuit," a desired
oscillation frequency can be determined by the value of the
resistor connected to the RT pin. When designing an oscillation
frequency, you can set any frequency between 300kHz and
1.5MHz. You can obtain the oscillation frequency from the
characteristic curve "Oscillation frequency (fosc) vs. timing
resistor resistance (R
T
)" or the value can be approximately
calculated by the following expression.
This expression, however, can be used for rough calculation,
the obitained value is not guaranteed. The operation frequency
varies due to the conditions such as tolerance of the
characteristics of the ICs, influence of noises, or external
discrete components. When determining the values, examine
the effectiveness of the values in an actual circuit. The timing
resistor R
T
should be wired to the GND pin as shortly as
possible because the RT pin is a high impedance pin and is
easy affected by noises.
2. Operation near the maximum or the minimum output
duty cycle
As described in "Output duty cycle vs. voltage", the output duty
cycle of this IC changes sharply near the minimum and the
maximum output duty cycle. Note that these phenomena are
conspicuous for high frequency operation (when the pulse width
is narrow).
3. Determining soft start period
The period from the start of charging the capacitor C
CS
to
widening n% of output duty cycle can be roughly calculated by
the following expression: (see Fig. 5 for symbols)
V
CS1n
and V
CS2n
are the voltage of the CS1 and CS2 pins in
n% of output duty cycle, and vary in accordance with operating
frequency. The value can be obtained from the characteristic
curve "Output duty cycle vs. CS voltage"
To reset the soft start function, the supply voltage V
CC
is
lowered below the UVLO voltage (2.1V typ.) and then the
internal switch discharges the CS capacitor. The characteristics
of the internal switch for discharge are shown in following the
characteristics curves of "Characteristics of CS1 internal
discharge switch current vs. voltage" and "Characteristics of
CS2 internal discharge switch current vs. voltage". Therefore,
when determining the period of soft start at restarting the power
supply, consider the characteristics carefully.
C
CS1
, C
CS2
: Capacitance connected to CS1or CS2 pin [µF]
R7, R9:
Resistance connected to CS1 or CS2 pin [k
]
f
OSC
= 4050 R
T
­0.86
f
OSC
: Oscillation frequency [kHz]
R
T
:
Timing resistor [k
]
( )
R
T
=
4050
f
OSC
1.16
For CS1 pin
(
)
t [ms] = R7
C
CS1
1n
1 ­
V
CS1n
V
REG
For CS2 pin
(
)
t [ms] = R9
C
CS2
1n
V
CS2n
V
REG
FA3687V
16
4. Setting maximum duty cycle
As described in the Fig. 9, you can limit maximum duty cycle by
connecting a resistor divider "R7, R8 or R9, R10" between CS1,
CS2 and VREG pin. Set the maximum duty cycle considering
that relation between the maximum output duty cycle and the
CS pin voltage changes with operation frequency as described
in the characteristic curves of "Output duty cycle vs. oscillation
frequency" and "Output duty cycle vs. CS voltage". When the
maximum duty cycle is limited, CS pin voltage at start-up is
described in Fig. 10, and the approximate value of soft start
period can be obtained by the following expressions:
The divided CS1 voltage is obtained by:
The divided CS2 voltage is obtained by:
V
CS1n
and V
CS2n
are the voltages of CS1 and CS2 under a
certain output duty cycle and varies with operation frequencies.
The values of V
CS1n
and V
CS2n
can be obtained from the
characteristic curves of "Output duty cycle vs. CS voltage".
The charging of C
CS1
and C
CS2
after UVLO is unlocked.
Therefore, the period from power-on of Vcc to widening n% of
output duty cycle is the sum of t0 and t.
5. Determining the output voltage of DC-DC converters
The ways to determine the output voltage of the DC-DC
converter of each channel is shown in Fig. 10 and the following
equations.
For ch1:
The positive output voltage of DC-to-DC converter (a buck, a
boost) is determined by:
For ch2:
The positive output voltage of DC-to-DC converter is
determined by:
Here,
When R5=R6,
C
CS1
, C
CS2
:
Capacitance connected to the CS1 or CS2 pin [µF]
R7, R8, R9, R10: Resistance connected to CS1 or CS2 pin [k
]
V
CS1
=
R8
V
REG
R7 + R8
V
CS2
=
R9
V
REG
R9 + R10
For CS2
(
)
t [ms] = R
0
C
CS2
1n
V
CS2n
­ V
CS2
V
REG
­ V
CS2
V
out1
=
R1 + R2
V
REF
R2
V
out2
= V1
R3 + R4
R3
V1 = V
REG
R6
R5 + R6
For CS1
(
)
t [ms] = R
0
C
CS1
1n
V
CS1n
V
CS1
(
)
Vout2 = V
REG
R3 + R4
2R3
13
10
VREG
CS1
C
CS1
R7
R8
13
7
CS2
VREG
R9
R10
C
CS2
Fig. 9
Threshold voltage
Vcc
t
t0
t
t0
V
REG
V
CS1N
R8
R7+R8
Threshold voltage
t0: Time from power-on of V
CC
to reaching unlock voltage of UVLO.
V
REG
V
REG
pin voltage
V
CS2n
V
CC
R9
R9+R10
Fig. 10
Ch1
Ch2
R
0
=
R7 R8
R7+R8
R
0
=
R9 R10
R9+R10
FA3687V
17
Fig. 11
The negative output voltage of DC-to-DC converter (inverting) is
determined by:
The ratio of resistances is determined by:
(Use the absolute value of the Vout2 voltage.)
When R5 = R6,
Connect the SEL1 and SEL2 pin to GND or VREG surely.
6. Restriction of external discrete components and
recommended operating conditions
To achieve a stable operation of the IC, the value of external
discrete components connected to VCC, VREG, CS, CP pins
should be within the recommended operating conditions. And
the voltage and the current applied to each pin should be also
within the recommended operating conditions. If the pin voltage
of OUT1, OUT2, or VREG becomes higher than the VCC pin
voltage, the current flows from the pins to the VCC pin because
parasitic three diodes exist between the VCC pin and these
pins. Be careful not to allow this current to flow.
7. Loss calculation
Since it is hard to measure IC loss directly, the calculation to
obtain the approximate loss of the IC connected directly to a
MOSFET is described below.
When the supply voltage is V
CC
, the current consumption of the
IC is I
CCA
, the total input gate charge of the driven MOSFET is
Qg and the switching frequency is fsw, the total loss Pd of the
IC can be calculated by:
Pd V
CC
(I
CCA
+ Qg fsw).
The value in this expression is influenced by the effects of the
dependency of supply voltage, the characteristics of
temperature, or the tolerance of parameter. Therefore, evaluate
the appropriateness of IC loss sufficiently considering the range
of values of above parameters under all conditions.
Example
I
CCA
=2.5mA for V
CC
=3.3V in the case of a typical IC from the
characteristic curves. Qg=6nC, fsw=500kHz, the IC loss "Pd" is
as follows.
Pd 3.3 (2.5mA + 6nC 500kHz) 18.2mW
If two MOSFETs are driven under the same condition for 2
channels, Pd is as follows:
Pd 3.3 {2.5mA+2 (6nC 500kHz)} = 28.1mW
IN1-
FB1
Vout1
R2
R1
SEL1
VREG
OUT1
Vout1
9
16
15
14
+
VREF
(1.0V)
IN1-
FB1
Vout1
R2
R1
SEL1
GND
OUT1
Vout1
9
16
15
14
+
VREF
(1.0V)
Buck
Boost
5
4
3
13
VREG
IN2+
IN2-
FB2
Vout2
R3
R4
R5
R6
2
SEL2
VREG
OUT2
8
Vout2
V1
5
4
3
13
VREG
IN2+
IN2-
FB2
Vout2
R3
R4
R5
R6
2
SEL2
VREG
OUT2
8
Vout2
V1
5
4
3
13
VREG
IN2+
IN2-
FB2
Vout2
R3
R4
R5
R6
2
SEL2
GND
OUT2
8
Vout2
V1
Buck
Boost
Inverting
(
)
Vout2 = V
REG
R3 ­ R4
2R3
R3
=
V
REG
­ V1
R4
Vout2 + V1
Vout2 =
R3 + R4
V1 ­
R4
V
REG
R3
R3
FA3687V
18
s
Application circuit
40k
10k
22k
11k
100
0.01
µ
F
10
µ
F
10
µ
F
10
µ
F
7to18V
GND
5V/500mA
3.3V/500mA
GND
0.01
µ
F
0.068
µ
F
0.47
µ
F
0.1uF
1M
1
µ
F
0.1
µ
F
10k
6.2k
100k
100k
10k
FB1
IN1-
IN2-
GND
IN2+
FB2
RT
CS1
CS2
SEL1
CP
VREG
OUT1
VCC
OUT2
SEL2
FA3687V
15
14
11
10
12
13
9
16
4
5
3
2
1
7
6
8
10k
10k
0.01
µ
F
Parts tolerances characteristics are not defined in the circuit design
sample shown above. When designing an actual circuit for a product,
you must determine parts tolerances and characteristics for safe and
economical operation.