56F8366 Technical Data, Rev. 2.0
2
Freescale Semiconductor
Preliminary
Document Revision History
Version History
Description of Change
Rev 0
Pre-release, Alpha customers only
Rev 1.0
Initial Public Release
Rev. 2.0
Added output voltage maximum value and note to clarify in
Table 10-1
; also removed overall
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
P
D
in
Table 10-3
. Corrected note about average value for Flash Data Retention in
Table 10-4
.
Added new RoHS-compliant orderable part numbers in
Table 13-1
.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8366 Technical Data, Rev. 2.0
Freescale Semiconductor
3
Preliminary
56F8366/56F8166 Block Diagram - 144 LQFP
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
PLL
Clock
Generator
EXTAL
Interrupt
Controller
COP/
Watchdog
SCI1 or
GPIOD
4
External
Address Bus
Switch
Ex
t
e
rna
l
Bu
s
In
ter
f
ace
Un
it
2
CLKMODE
IRQA IRQB
External Data
Bus Switch
Program Memory
256K x 16 Flash
2K x 16 RAM
Boot ROM
16K x 16 Flash
D
ata Memory
16K x 16 Flash
16K x 16 RAM
PDB
PDB
XAB1
XAB2
XDB2
CDBR
SCI0 or
GPIOE
SPI0 or
GPIOE
IPBus Bridge (IPBB)
Integration
Module
System
P
O
R
O
S
C
Decoding
Peripherals
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
System Bus
R/W Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
Clock
resets
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
V
CAP
V
DD
V
SS
V
DDA
V
SSA
5
4
7
5
2
V
PP
2
OCR_DIS
RESET
EXTBOOT
EMI_MODE
RSTO
4
3
6
PWM Outputs
Fault Inputs
PWMA
Current Sense Inputs
or GPIOC
3
4
6
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
or GPIOD
3
Quad
Timer D or
GPIOE
Quad
Timer C or
GPIOE
AD0
AD1
ADCA
2
5
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
FlexCAN
2
4
AD0
AD1
4
4
4
Temp_Sense
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
4
CLKO
Bus Control
6
2
8
7
9
XTAL
PS / CS0 (GPIOD8)
RD
WR
D7-15 or GPIOF0-8
D0-6 or GPIOF9-15
GPIOB0 or A16
A8-15 or GPIOA0-7
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
VREF
ADCB
16-Bit
56800E Core
DS / CS1 (GPIOD9)
Control
GPIO or
EMI CS or
FlexCAN2
GPIOD1 (CS3 or CAN2_RX)
GPIOD0 (CS2 or CAN2_TX)
56F8366/56F8166 General Description
Note: Features in italics are NOT available in the 56F8166 device.
· Up to 60 MIPS at 60MHz core frequency
· DSP and MCU functionality in a unified,
C-efficient architecture
· Access up to 1MB of off-chip program and data memory
· Chip Select Logic for glueless interface to ROM and
SRAM
· 512KB of Program Flash
· 4KB of Program RAM
· 32KB of Data Flash
· 32KB of Data RAM
· 32KB of Boot Flash
· Up to two 6-channel PWM modules
· Four 4-channel, 12-bit ADCs
· Temperature Sensor
· Up to two Quadrature Decoders
· Optional On-Chip Regulator
· Up to two FlexCAN modules
· Two Serial Communication Interfaces (SCIs)
· Up to two Serial Peripheral Interfaces (SPIs)
· Up to four General Purpose Quad Timers
· Computer Operating Properly (COP) / Watchdog
· JTAG/Enhanced On-Chip Emulation (OnCETM) for
unobtrusive, real-time debugging
· Up to 62 GPIO lines
· 144-pin LQFP Package
56F8366 Technical Data, Rev. 2.0
4
Freescale Semiconductor
Preliminary
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8366/56F8166 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . . 38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 44
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 48
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 49
4.7. Peripheral Memory Mapped Registers . . . . 50
4.8. Factory Programmed Memory . . . . . . . . . . 83
Part 5: Interrupt Controller (ITCN) . . . . . . . . 83
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3. Functional Description . . . . . . . . . . . . . . . . 83
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 85
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 85
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 86
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Part 6: System Integration Module (SIM) . 114
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 115
6.4. Operating Mode Register . . . . . . . . . . . . . 116
6.5. Register Descriptions . . . . . . . . . . . . . . . . 117
6.6. Clock Generation Overview . . . . . . . . . . . 132
6.7. Power-Down Modes Overview . . . . . . . . . 132
6.8. Stop and Wait Mode Disable Function . . . 133
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Part 7: Security Features . . . . . . . . . . . . . . 134
7.1. Operation with Security Enabled . . . . . . . 134
7.2. Flash Access Blocking Mechanisms . . . . 135
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 137
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . .137
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . .138
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . .138
Part 9: Joint Test Action Group (JTAG) . 143
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . .143
Part 10: Specifications . . . . . . . . . . . . . . . 144
10.1. General Characteristics . . . . . . . . . . . . . .144
10.2. DC Electrical Characteristics . . . . . . . . . .148
10.3. AC Electrical Characteristics . . . . . . . . . .152
10.4. Flash Memory Characteristics . . . . . . . . .152
10.5. External Clock Operation Timing . . . . . . .153
10.6. Phase Locked Loop Timing . . . . . . . . . . .153
10.7. Crystal Oscillator Timing . . . . . . . . . . . . .154
10.8. External Memory Interface Timing . . . . . .154
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . .157
10.10. Serial Peripheral Interface (SPI) Timing .159
10.11. Quad Timer Timing . . . . . . . . . . . . . . . .162
10.12. Quadrature Decoder Timing . . . . . . . . . .163
10.13. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . .164
10.14. Controller Area Network (CAN) Timing .164
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . .165
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . .166
10.17. Equivalent Circuit for ADC Inputs . . . . . .169
10.18. Power Consumption . . . . . . . . . . . . . . . .169
Part 11: Packaging . . . . . . . . . . . . . . . . . . 171
11.1. 56F8366 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .171
11.2. 56F8166 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .174
Part 12: Design Considerations . . . . . . . . 178
12.1. Thermal Design Considerations . . . . . . . .178
12.2. Electrical Design Considerations . . . . . . .179
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .180
Part 13: Ordering Information . . . . . . . . . 181
Table of Contents
56F8366/56F8166 Features
56F8366 Technical Data, Rev. 2.0
Freescale Semiconductor
5
Preliminary
Part 1 Overview
1.1 56F8366/56F8166 Features
1.1.1
Core
·
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
·
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
·
Single-cycle 16
× 16-bit parallel Multiplier-Accumulator (MAC)
·
Four 36-bit accumulators, including extension bits
·
Arithmetic and logic multi-bit shifter
·
Parallel instruction set with unique DSP addressing modes
·
Hardware DO and REP loops
·
Three internal address buses
·
Four internal data buses
·
Instruction set supports both DSP and controller functions
·
Controller-style addressing modes and instructions for compact code
·
Efficient C compiler and local variable support
·
Software subroutine and interrupt stack with depth limited only by memory
·
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8366 and 56F8166 devices.
Table 1-1 Device Differences
Feature
56F8366
56F8166
Guaranteed Speed
60MHz/60 MIPS
40MHz/40 MIPS
Program RAM
4KB
Not Available
Data Flash
8KB
Not Available
PWM
2 x 6
1 x 6
CAN
2
Not Available
Quad Timer
4
2
Quadrature Decoder
2 x 4
1 x 4
Temperature Sensor
1
Not Available
Dedicated GPIO
--
5
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