September 1983
Revised February 1999
MM74HC165 Paral
l
el
-i
n/
Seri
al-
out 8-
B
i
t Shi
f
t
Regi
ster
© 1999 Fairchild Semiconductor Corporation
DS005316.prf
www.fairchildsemi.com
MM74HC165
Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT
SHIFT REGISTER utilizes advanced silicon-gate CMOS
technology. It has the low power consumption and high
noise immunity of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from Q
A
to Q
H
when clocked. Parallel inputs to each stage are enabled by
a low level at the SHIFT/LOAD input. Also included is a
gated CLOCK input and a complementary output from the
eighth bit.
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel
loading is inhibited as long as the SHIFT/LOAD input is
HIGH. When taken LOW, data at the parallel inputs is
loaded directly into the register independent of the state of
the clock.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 20 ns (clock to Q)
s
Wide operating supply voltage range: 26V
s
Low input current: 1
µ
A maximum
s
Low quiescent supply current: 80
µ
A maximum (74HC
Series)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Function Table
H
=
HIGH Level (steady state), L
=
LOW Level (steady state)
X
=
Irrelevant (any input, including transitions)
=
Transition from LOW-to-HIGH level
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the indi-
cated steady-state input conditions were established.
Q
AN
, Q
GN
=
The level of Q
A
or Q
G
before the most recent
transition of the
clock; indicates a one-bit shift.
Order Number
Package Number
Package Description
MM74HC165M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC165SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC165MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC165
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Inputs
Internal
Output
Shift/ Clock Clock Serial Parallel Outputs
Q
H
Load Inhibit
A. . .H Q
A
Q
B
L
X
X
X
a. . .h
a
b
h
H
L
L
X
X
Q
A0
Q
B0
Q
H0
H
L
H
X
H
Q
AN
Q
GN
H
L
L
X
L
Q
AN
Q
GN
H
H
X
X
X
Q
A0
Q
B0
Q
H0
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2
MM
74HC165
Logic Diagrams
3
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MM74HC165
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
°
C from 65
°
C to 85
°
C.
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
±
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
±
20 mA
DC Output Current, per pin (I
OUT
)
±
25 mA
DC V
CC
or GND Current, per pin (I
CC
)
±
50 mA
Storage Temperature Range (T
STG
)
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
(V
IN
, V
OUT
)
0
V
CC
V
Operating Temperature Range (T
A
)
-
40
+
85
°
C
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
T
A
=
-
40 to 85
°
C T
A
=
-
55 to 125
°
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
V
IL
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
20
µ
A
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
20
µ
A
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input
V
IN
=
V
CC
or GND
6.0V
±
0.1
±
1.0
±
1.0
µ
A
Current
V
CC
=
2
-
6V
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
8.0
80
160
µ
A
Supply Current
I
OUT
=
0
µ
A
V
CC
=
2
-
6V
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4
MM
74HC165
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
f
MAX
Maximum Operating Frequency
50
30
MHz
t
PHL
, t
PLH
Maximum Propagation Delay H to Q
H
or Q
H
15
25
ns
t
PHL
, t
PLH
Maximum Propagation Delay
13
25
ns
Serial Shift/Parallel Load to Q
H
t
PHL
, t
PLH
Maximum Propagation Delay
15
25
ns
Clock to Output
t
S
Minimum Setup Time Serial Input
10
20
ns
to Clock, Parallel or Data to Shift/Load
t
S
Minimum Setup Time Shift/Load to Clock
11
20
ns
t
S
Minimum Setup Time Clock Inhibit to Clock
10
20
ns
t
H
Minimum Hold Time Serial
0
ns
Input to Clock or
Parallel Data to Shift/Load
t
W
Minimum Pulse Width Clock
16
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
T
A
=
-
40 to 85
°
C T
A
=
-
55 to 125
°
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
2.0V
10
5
4
4
MHz
Frequency
4.5V
45
27
21
18
MHz
6.0V
50
32
25
21
MHz
t
PHL
, t
PLH
Maximum Propagation
2.0V
70
150
189
225
ns
Delay H to Q
H
or Q
H
4.5V
21
30
38
45
ns
6.0V
18
26
33
39
ns
t
PHL
, t
PLH
Maximum Propagation
2.0V
70
175
220
260
ns
Delay Serial Shift/
4.5V
21
35
44
52
ns
Parallel Load to Q
H
6.0V
18
30
37
44
ns
t
PHL
, t
PLH
Maximum Propagation
2.0V
70
150
189
225
ns
Delay Clock to Output
4.5V
21
30
38
45
ns
6.0V
18
26
33
39
ns
t
S
Minimum Setup Time
2.0V
35
100
125
150
ns
Serial Input to Clock,
4.5V
11
20
25
30
ns
or Parallel Data to Shift/Load
6.0V
9
17
21
25
ns
t
S
Minimum Setup Time
2.0V
38
100
125
150
ns
Shift/Load to Clock
4.5V
12
20
25
30
ns
6.0V
9
17
21
25
ns
t
S
Minimum Setup Time
2.0V
35
100
125
150
ns
Clock Inhibit to Clock
4.5V
11
20
25
30
ns
6.0V
9
17
21
25
ns
t
H
Minimum Hold Time Serial
2.0V
0
0
0
ns
Input to Clock or
4.5V
0
0
0
ns
Parallel Data to Shift/Load
6.0V
0
0
0
ns
t
W
Minimum Pulse Width,
2.0V
30
80
100
120
ns
Clock
4.5V
9
16
20
24
ns
6.0V
8
14
18
20
ns
t
THL
, t
TLH
Maximum Output
2.0V
30
75
95
110
ns
Rise and Fall Time
4.5V
9
15
19
22
ns
6.0V
8
13
16
19
ns
t
r
, t
f
Maximum Input Rise and
2.0V
1000
1000
1000
ns
Fall Time
4.5V
500
500
500
ns
6.0V
400
400
400
ns
5
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MM74HC165
AC Electrical Characteristics
(Continued)
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
T
A
=
-
40 to 85
°
C T
A
=
-
55 to 125
°
C
Units
Typ
Guaranteed Limits
C
PD
Power Dissipation
(per package)
100
pF
Capacitance (Note 5)
C
IN
Maximum Input Capacitance
5
10
10
10
pF
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6
MM
74HC165
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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MM74HC165
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC165
Par
a
l
l
el
-i
n/Ser
i
al
-o
ut 8-Bi
t Shif
t Regis
t
er
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300" Wide
Package N16E
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