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Part Number MM74C42

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October 1987
Revised January 1999
MM74C42 BCD
-
t
o-
Deci
m
a
l

Dec
oder
© 1999 Fairchild Semiconductor Corporation
DS005882.prf
www.fairchildsemi.com
MM74C42
BCD-to-Decimal Decoder
General Description
The MM74C42 one-of-ten decoder is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. This decoder
produces a logical "0" at the output corresponding to a four
bit binary input from zero to nine, and a logical "1" at the
other outputs. For binary inputs from ten to fifteen all out-
puts are logical "1".
Features
s
Supply voltage range:
3V to 15V
s
Tenth power TTL compatible:
drive 2 LPTTL loads
s
High noise immunity:
0.45 V
CC
(typ.)
s
Low power:
50 nW (typ.)
s
Medium speed operation:
10 MHz (typ.) with 10V V
CC
Applications
· Automotive
· Data terminals
· Instrumentation
· Medical electronics
· Alarm systems
· Industrial electronics
· Remote metering
· Computers
Ordering Code:
Connection Diagram
Pin Assignments for DIP
Top View
Order Number
Package Number
Package Description
MM74C42N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
MM
74C42
Schematic Diagram
Truth Table
Inputs
Outputs
D
C
B
A
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
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MM74C42
Absolute Maximum Ratings
(Note 1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
AC Electrical Characteristics
(Note 2)
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise specified
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note--
AN-90.
Voltage at Any Pin (Note 1)
-
0.3V to V
CC
+
0.3V
Operating Temperature Range
-
40
°
C to
+
85
°
C
Storage Temperature Range
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Operating V
CC
Range
3.0V to 15V
Absolute Maximum V
CC
18V
Lead Temperature
(Soldering, 10 seconds)
260
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical "1" Input Voltage
V
CC
=
5.0V
3.5
V
V
CC
=
10V
8.0
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
5.0V
1.5
V
V
CC
=
10V
2.0
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
5.0V, I
O
=
-
10
µ
A
4.5
V
V
CC
=
10V, I
O
=
-
10
µ
A
9.0
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
5.0V, I
O
=
10
µ
A
0.5
V
V
CC
=
10V, I
O
=
10
µ
A
1.0
V
I
IN(1)
Logical "1" Input Current
V
CC
=
15V, V
IN
=
15V
1.0
µ
A
I
IN(0)
Logical "0" Input Current
V
CC
=
15V, V
IN
=
0V
-
1.0
µ
A
I
CC
Supply Current
V
CC
=
15V
0.05
300
µ
A
CMOS/LPTTL INTERFACE
V
IN(1)
Logical "1" Input Voltage
V
CC
=
4.75V
V
CC
-
1.5
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
4.75V
0.8
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
4.75V, I
O
=
-
360
µ
A 2.4
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
4.75V, I
O
=
360
µ
A
0.4
V
OUTPUT DRIVE (see Family Characteristics Data Sheet) T
A
=
25
°
C (short circuit current)
I
SOURCE
Output Source Current
V
CC
=
5.0V, V
IN(0)
=
0V, V
OUT
=
0V
-
1.75
mA
I
SOURCE
Output Source Current
V
CC
=
10V, V
IN(0)
=
0V, V
OUT
=
0V
-
8.0
mA
I
SINK
Output Sink Current
V
CC
=
5.0V, V
IN(1)
=
5.0V, V
OUT
=
V
CC
1.75
mA
I
SINK
Output Sink Current
V
CC
=
10V, V
IN(1)
=
10V, V
OUT
=
V
CC
8.0
mA
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay Time to
V
CC
=
5.0V
200
300
ns
Logical "0" or "1"
V
CC
=
10V
90
140
ns
C
IN
Input Capacitance
(Note 3)
5
pF
C
PD
Power Dissipation Capacitance
(Note 4)
50
pF
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM
74
C
4
2 BCD-t
o
-Dec
imal
Decoder
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E