Š2000 Fairchild Semiconductor International

www.fairchildsemi.com

Rev. 5.0

Features

ˇ Low Start Up Current
ˇ Maximum Duty Clamp
ˇ UVLO With Hysteresis
ˇ Operating Frequency Up To 500KHz

Description

The KA3842B/KA3843B/KA3844B/KA3845B are fixed
frequency current-mode PWM controller. They are spe-
cially designed for Off - Line and DC-to-DC converter
applications with minimum external components. These
integrated circuits feature a trimmed oscillator for precise
duty cycle control, a temperature compensated reference,
high gain error amplifier. current sensing comparator, and a
high current totempole output Ideally suited for driving a
power MOSFET. Protection circuity Includes built in
under-voltage lockout and current limiting. The KA3842B
and KA3844B have UVLO thresholds of 16V (on) and
10V (off) The KA3843B and KA3845B are 8.5V (on) and
7.9V (off) The KA3842B and KA3843B can operate within
100% duty cycle. The KA3844B and KA3845B can operate
with 50% duty cycle.

8-DIP

14-SOP

KA3842B/KA3843B/KA3844B/KA3845B

SMPS Controller

KA3842B/KA3843B/KA3844B/KA3845B

Electrical Characteristics

=15V, R

=10K

, C

=3.3nF, T

= 0

C to +70

C, unless otherwise specified)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

REFERENCE SECTION
Reference Output Voltage

REF

= 25

C, I

REF

= 1mA

4.90

5.00

5.10

Line Regulation

REF

12V

25V

Load Regulation

REF

1mA

REF

20mA

Short Circuit Output Current

= 25

-100

-180

OSCILLATOR SECTION
Oscillation Frequency

= 25

KHz

Frequency Change with Voltage

12V

25V

0.05

Oscillator Amplitude

OSC

1.6

P-P

ERROR AMPLIFIER SECTION
Input Bias Current

BIAS

-0.1

-2

Input Voltage

I(E>A)

= 2.5V

2.42

2.50

2.58

Open Loop Voltage Gain

Power Supply Rejection Ratio

PSRR

12V

25V

Output Sink Current

SINK

= 2.7V, V

= 1.1V

Output Source Current

SOURCE

= 2.3V, V

= 5V

-0.6

-1.0

High Output Voltage

= 2.3V, R

= 15K

to GND

Low Output Voltage

= 2.7V, R

= 15K

to Pin 8

0.8

1.1

CURRENT SENSE SECTION
Gain

(Note 1 & 2)

2.85

3.15

V/V

Maximum Input Signal

I(MAX)

= 5V(Note 1)

0.9

1.1

Power Supply Rejection Ratio

PSRR

12V

25V (Note 1)

Input Bias Current

BIAS

-3

-10

OUTPUT SECTION

Low Output Voltage

SINK

= 20mA

0.08

0.4

SINK

= 200mA

1.4

2.2

High Output Voltage

SOURCE

= 20mA

13.5

SOURCE

= 200mA

13.0

Rise Time

= 25

C, C

= 1nF (Note 3)

150

Fall Time

= 25

C, C

= 1nF (Note 3)

150

UNDER-VOLTAGE LOCKOUT SECTION

Start Threshold

TH(ST)

KA3842B/KA3844B

14.5

16.0

17.5

KA3843B/KA3845B

7.8

8.4

9.0

Min. Operating Voltage
(After Turn On)

OPR(MIN)

KA3842B/KA3844B

8.5

10.0

11.5

KA3843B/KA3845B

7.0

7.6

8.2

KA3842B/KA3843B/KA3844B/KA3845B

Electrical Characteristics (Continued)

=15V, R

=10K

, C

=3.3nF, T

= 0

C to +70

C unless otherwise specified)

Adjust V

above the start threshould before setting at 15V

Note:
1. Parameter measured at trip point of latch
2. Gain defined as:

3.These parameters, although guaranteed, are not 100 tested in production.

Figure 1. Open Loop Test Circuit

High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors
should be connected close to pin 5 in a single point ground. The transistor and 5K

potentiometer are used to sample the

oscillator waveform and apply an adjustable ramp to pin 3.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

PWM SECTION

Max. Duty Cycle

(max)

KA3842B/KA3843B

100

KA3844B/KA3845B

Min. Duty Cycle

(MIN)

TOTAL STANDBY CURRENT
Start-Up Current

0.45

Operating Supply Current

CC(OPR)

=ON

Zener Voltage

= 25mA

----------

0.8V

KA3842B/KA3843B/KA3844B/KA3845B

Figure 2. Under Voltage Lockout

During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground
with a bleeder resistor to prevent activating the power switch with output leakage current.

Figure 3. Error Amp Configuration

Figure 4. Current Sense Circuit

Peak current (I

) is determined by the formula:

A small RC filter may be required to suppress switch transients.

MAX

(

)

1.0V

------------

KA3842B/KA3843B/KA3844B/KA3845B

Figure 5. Oscillator Waveforms and Maximum Duty Cycle

Oscillator timing capacitor, C

, is charged by V

REF

through R

, and discharged by an internal current source. During the dis-

charge time, the internal clock signal blanks the output to the low state. Selection of R

and C

therefore determines both

oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:

= 0.55 R

Frequency, then, is: f=(t

+ t

)

-1

Figure 8. Shutdown Techniques

Figure 6. Oscillator Dead Time & Frequency

Figure 7. Timing Resistance vs Frequency

0.0063R

2.7

0.0063R

----------------------------------------

ForRT 5K

1.8

---------------

(Deadtime vs C

RT > 5k

)

KA3842B/KA3843B/KA3844B/KA3845B

Shutdown of the KA3842B can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage
two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram).
The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at
pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SOR which
will be reset by cycling Voc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch
spikes.

TEMPERATURE (

Figure 10. TEMPERATURE DRIFT (Vref)

TEMPERATURE (

Figure 11. TEMPERATURE DRIFT (Ist)

TEMPERATURE (

Figure 12. TEMPERATURE DRIFT (Icc)

KA3842B/KA3843B/KA3844B/KA3845B

Mechanical Dimensions

Package

6.40

0.20

3.30

0.30

0.130

0.012

3.40

0.20

0.134

0.008

0.252

0.008

9.20

0.20

0.79

2.54

0.100

0.031

()

0.46

0.10

0.018

0.004

0.060

0.004

1.524

0.10

0.362

0.008

9.60

0.378

MAX

5.08

0.200

0.33

0.013

7.62

0~15

0.300

MAX

MIN

0.25

+0.10

0.05

0.010

+0.004

0.002

8-DIP

KA3842B/KA3843B/KA3844B/KA3845B

Mechanical Dimensions

(Continued)

Package

8.56

0.20

0.337

0.008

1.27

0.050

5.72

0.225

1.55

0.10

0.061

0.004

0.05

0.002

6.00

0.30

0.236

0.012

3.95

0.20

0.156

0.008

0.60

0.20

0.024

0.008

8.70

0.343

MAX

0~8

#14

0.47

0.019

()

1.80

0.071

MAX0.10

MAX0.004

MAX

MIN

0.10

-0.05

0.20

0.004

-0.002

0.008

0.10

-0.05

0.406

0.004

-0.002

0.016

14-SOP

KA3842B/KA3843B/KA3844B/KA3845B

7/13/00 0.0m 001

Stock#DSxxxxxxxx

2000 Fairchild Semiconductor International

LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

INTERNATIONAL. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with
instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

Part Number KA3845B