DS006372

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August 1986

Revised March 2000

DM74LS73A Dual Negat

ive-

Edge-

r
i
ggered Master

-Sl
ave J-K Fli

-Fl
ops wit

Cl
ear and C

mpl

ntar

Out

puts

DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Connection Diagram

Function Table

HIGH Logic Level

LOW Logic Level

Either LOW or HIGH Logic Level

Negative going edge of pulse.

The output logic level before the indicated input conditions were

established.
Toggle

Each output changes to the complement of its previous level on

each falling edge of the clock pulse.

Order Number

Package Number

Package Description

DM74LS73AM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS73AN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Outputs

CLR

CLK

Toggle

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74L

Absolute Maximum Ratings

(Note 1)

Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.

Recommended Operating Conditions

Note 2: C

15 pF, R

2 k

, T

C and V

5V.

Note 3: C

50 pF, R

2 k

, T

C and V

5V.

Note 4: The symbol (

) indicates the falling edge of the clock pulse is used for reference.

Supply Voltage

Input Voltage

Operating Free Air Temperature Range

C to

Storage Temperature Range

C to

150

Symbol

Parameter

Min

Nom

Max

Units

Supply Voltage

4.75

5.25

HIGH Level Input Voltage

LOW Level Input Voltage

0.8

HIGH Level Output Current

0.4

LOW Level Output Current

CLK

Clock Frequency (Note 2)

MHz

CLK

Clock Frequency (Note 3)

MHz

Pulse Width

Clock HIGH

(Note 2)

Preset LOW

Clear LOW

Pulse Width

Clock HIGH

(Note 3)

Preset LOW

Clear LOW

Setup Time (Note 2)(Note 4)

Setup Time (Note 3)(Note 4)

Hold Time (Note 2)(Note 4)

Hold Time (Note 3)(Note 4)

Free Air Operating Temperature

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DM74LS73A

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typicals are at V

5V, T

Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where V

2.125V with the mini-

mum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 7: With all outputs OPEN, I

is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.

Switching Characteristics

at V

5V and T

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(Note 5)

Input Clamp Voltage

Min, I

18 mA

1.5

HIGH Level

Min, I

Max

2.7

3.4

Output Voltage

Max, V

Min

LOW

Level V

Min, I

Max

0.35

0.5

Output Voltage

Max, V

Min

4 mA, V

Min

0.25

0.4

Input Current @ Max

Max

J, K

0.1

Input Voltage

Clear

0.3

Clock

0.4

HIGH Level

Max

J, K

Input Current

2.7V

Clear

Clock

LOW

Level V

Max

J, K

0.4

Input Current

0.4V

Clear

0.8

Clock

0.8

Short Circuit Output Current

Max (Note 6)

100

Supply Current

Max (Note 7)

From (Input)

2 k

Symbol

Parameter

To (Output)

15 pF

50 pF

Units

Min

Max

Min

Max

MAX

Maximum Clock Frequency

MHz

PHL

Propagation Delay Time

Clear

HIGH-to-LOW Level Output

to Q

PLH

Propagation Delay Time

Clear

LOW-to-HIGH Level Output

to Q

PLH

Propagation Delay Time

Clock to

LOW-to-HIGH Level Output

Q or Q

PHL

Propagation Delay Time

Clock to

HIGH-to-LOW Level Output

Q or Q

www.fairchildsemi.com

DM74LS73A Dual Negat

ive-

Edge-

r
i
ggered Master

-Sl
ave J-K Fli

-Fl
ops wit

Cl
ear and C

mpl

ntar

Out

puts

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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Part Number DM74LS73A