© 2000 Fairchild Semiconductor Corporation
DS006207
www.fairchildsemi.com
April 1984
Revised April 2000
DM74ALS169B Synchro
nous
Fou
r-Bi
t Up/Down Counter
s
DM74ALS169B
Synchronous Four-Bit Up/Down Counters
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for cascading in high speed counting
applications. The DM74ALS169B is a four-bit binary up/
down counter. The carry output is decoded to prevent
spikes during normal mode of counting operation. Synchro-
nous operation is provided so that outputs change coinci-
dent with each other when so instructed by count enable
inputs and internal gating. This mode of operation elimi-
nates the output counting spikes which are normally asso-
ciated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive going) edge of clock input waveform.
These counters are fully programmable; that is, the outputs
may each be preset either HIGH or LOW. The load input
circuitry allows loading with carry-enable output of cas-
caded counters. As loading is synchronous, setting up a
low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next
clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (P and T) must be LOW to count.
The direction of the count is determined by the level of the
up/down input. When the input is HIGH, the counter counts
UP; when LOW, it counts DOWN. Input T is fed forward to
enable the carry outputs. The carry output thus enabled will
produce a low level output pulse with a duration approxi-
mately equal to the high portion of the Q
A
output when
counting UP, and approximately equal to the low portion of
the Q
A
when counting DOWN. This low level overflow carry
pulse can be used to enable successively cascaded
stages. Transitions at the enable P or T inputs are allowed
regardless of the level of the clock input.
The control functions for these counters are fully synchro-
nous. Changes at control inputs (enable P, enable T, load,
up/down) which modify the operating mode have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s
Improved AC performance over Schottky and low power
Schottky counterparts
s
Synchronously programmable
s
Internal look ahead for fast counting
s
Carry output for n-bit cascading
s
Synchronous counting
s
ESD inputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
DM74ALS169BM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS169BN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com
4
DM
74ALS16
9B
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: The symbol (
) indicates that the rising edge of the clock is used as reference.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
°
C to
+
70
°
C
Storage Temperature Range
-
65
°
C to
+
150
°
C
Typical
JA
N Package
78.1
°
C/W
M Package
106.8
°
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
8
mA
f
CLK
Clock Frequency
0
40
MHz
t
SU
Setup Time (Note 2)
Data;
15
6
ns
A, B, C, D
En P, En T
15
8
ns
Load
15
8
ns
U/D
15
10
ns
t
H
Hold Time (Note 2)
Data;
0
-
3
ns
A, B, C, D
En P, En T
0
-
3
ns
Load
0
-
4
ns
U/D
0
-
4
ns
t
W
Width of Clock Pulse
13
ns
5
www.fairchildsemi.com
DM74ALS169B
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
°
C
Switching Characteristics
over recommended operating free air temperature range
Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is
maximum, the ripple carry output will be out of phase.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
I
OH
=
-
0.4 mA
V
CC
-
2
V
Output Voltage
V
CC
=
4.5V to 5.5V
V
OL
LOW Level
V
CC
=
4.5V
I
OL
=
8 mA
0.35
0.5
V
Output Voltage
I
I
Input Current @ Max
V
CC
=
5.5V, V
IH
=
7V
0.1
mA
Input Voltage
I
IH
HIGH Level Input Current
V
CC
=
5.5V, V
IH
=
2.7V
20
µ
A
I
IL
LOW Level Input Current
V
CC
=
5.5V, V
IL
=
0.4V
-
0.2
mA
I
O
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
5.5V
15
25
mA
Symbol
Parameter
Conditions
From
To
Min
Max
Units
f
MAX
Maximum Clock Frequency
40
MHz
t
PLH
Propagation Delay Time
V
CC
=
4.5V to 5.5V
Clock
Ripple Carry
3
20
ns
LOW-to-HIGH Level Output
R
L
=
500
t
PHL
Propagation Delay Time
C
L
=
50 pF
Clock
Ripple Carry
6
20
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clock
Any Q
2
15
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock
Any Q
5
20
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
En T
Ripple Carry
2
13
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
En T
Ripple Carry
3
16
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
U/D (Note 3)
Ripple Carry
5
19
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
U/D (Note 3) Ripple Carry
5
19
ns
HIGH-to-LOW Level Output
PDF 
ZIP
