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Part Number CD4512BC

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October 1987
Revised January 1999
CD451
2BC
8-
C
h
annel Buff
ered Data

Sel
ector
© 1999 Fairchild Semiconductor Corporation
DS005993.prf
www.fairchildsemi.com
CD4512BC
8-Channel Buffered Data Selector
General Description
The CD4512BC buffered 8-channel data selector is a com-
plementary MOS (CMOS) circuit constructed with N- and
P-channel enhancement mode transistors. This data selec-
tor is primarily used as a digital signal multiplexer selecting
1 of 8 inputs and routing the signal to a 3-STATE output. A
high level at the Inhibit input forces a low level at the out-
put. A high level at the Output Enable (OE) input forces the
output into the 3-STATE condition. Low levels at both the
Inhibit and (OE) inputs allow normal operation.
Features
s
Wide supply voltage range:
3.0V to 15V
s
High noise immunity:
0.45 V
DD
(typ.)
s
3-STATE output
s
Low quiescent power dissipation:
0.25
µ
W/package (typ.) @ V
CC
=
5.0V
s
Plug-in replacement for Motorola MC14512
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix "X" to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
Truth Table
2
=
Don't care
Hi-Z
=
3-STATE condition
Xn
=
Data at input n
Order Number
Package Number
Package Description
CD4512BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body
CD4512BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Address Inputs
Control Inputs
Output
C
B
A
Inhibit
OE
Z
0
0
0
0
0
X0
0
0
1
0
0
X1
0
1
0
0
0
X2
0
1
1
0
0
X3
1
0
0
0
0
X4
1
0
1
0
0
X5
1
1
0
0
0
X6
1
1
1
0
0
X7
2
1
1
1
0
0
2
2
2
2
1
Hi-Z
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2
C
D
45
12BC
Logic Diagram
3
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CD451
2BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The Recommended
Operating Conditions and Electrical Characteristics table provide condi-
tions for actual device operation.
Note 2: V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 2)
Note 3: I
OH
and I
OL
are tested one output at a time.
Supply Voltage (V
DD
)
-
0.5 to
+
18 V
DC
Input Voltage (V
IN
)
-
0.5 to V
DD
+
0.5 V
DC
Storage Temperature Range (T
S
)
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
Dual-In-Line 700
mW
Small Outline
500 mW
Lead Temperature, (T
L
)
(Soldering, 10 seconds)
260
°
C
DC Supply Voltage (V
DD
)
3.0 to 15 V
DC
Input Voltage (V
IN
)
0 to V
DD
V
DC
Operating Temperature Range (T
A
)
-
40
°
C to
+
85
°
C
Symbol
Parameter
Conditions
-
40
°
C
+
25
°
C
+
85
°
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
=
5V, V
IN
=
V
DD
or V
SS
20
0.005
20
150
µ
A
Current
V
DD
=
10V, V
IN
=
V
DD
or V
SS
40
0.010
40
300
µ
A
V
DD
=
15V, V
IN
=
V
DD
or V
SS
80
0.015
80
600
µ
A
V
OL
LOW Level
V
DD
=
5V
0.05
0
0.05
0.05
V
Output Voltage
V
DD
=
10V
|I
OL
|
<
1
µ
A
0.05
0
0.05
0.05
V
V
DD
=
15V
0.05
0
0.05
0.05
V
V
OH
HIGH Level
V
DD
=
5V
4.95
4.95
5.0
4.95
V
Output Voltage
V
DD
=
10V
|I
OH
|
<
1
µ
A
9.95
9.95
10.0
9.95
V
V
DD
=
15V
14.95
14.95
15.0
14.95
V
V
IL
LOW Level
V
DD
=
5V, V
O
=
0.5V
1.5
2.25
1.5
1.5
V
Input Voltage
V
DD
=
10V, V
O
=
1.0V
3.0
4.50
3.0
3.0
V
V
DD
=
15V, V
O
=
1.5V
4.0
6.75
4.0
4.0
V
V
IH
HIGH Level
V
DD
=
5V, V
O
=
4.5V
3.5
3.5
2.75
3.5
V
Input Voltage
V
DD
=
10V, V
O
=
9.0V
7.0
7.0
5.50
7.0
V
V
DD
=
15V, V
O
=
13.5V
11.0
11.0
8.25
11.0
V
I
OL
LOW Level Output
V
DD
=
5V, V
O
=
0.4V
0.52
0.44
0.78
0.36
mA
Current
V
DD
=
10V, V
O
=
0.5V
1.3
1.1
2.0
0.9
mA
(Note 3)
V
DD
=
15V, V
O
=
1.5V
3.6
3.4
7.8
2.4
mA
I
OH
HIGH Level Output
V
DD
=
5V, V
O
=
4.6V
-
0.2
-
0.16
-
0.12
mA
Current
V
DD
=
10V, V
O
=
9.5
-
0.5
-
0.4
-
0.3
mA
(Note 3)
V
DD
=
15V, V
O
=
13.5V
-
1.4
-
1.2
-
1.0
mA
I
IN
Input Current
V
DD
=
15V, V
IN
=
0V
-
0.3
-
10
-
5
-
0.3
-
1.0
µ
A
V
DD
=
15V, V
IN
=
15V
0.3
10
-
5
0.3
1.0
µ
A
I
OZ
3-STATE
V
DD
=
15V, V
O
=
0V
±
1.0
±
10
-
5
±
1.0
±
7.5
µ
A
Output Current
V
DD
=
15V, V
O
=
15V
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4
C
D
45
12BC
AC Electrical Characteristics
(Note 4)
T
A
=
25
°
C, t
r
=
t
f
=
20 ns, C
L
=
50 pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: Capacitance guaranteed by periodic testing.
Note 6: C
PD
determines the no load AC power of any CMOS device. For complete explanation, see Family Characteristics Application Note, AN-90.
Symbol
Parameter
Conditions
CD4512BM
CD4512BC
Units
Min
Typ
Max
Min
Typ
Max
t
PHL
Propagation Delay
V
DD
=
5V
225
500
225
750
ns
HIGH-to-LOW Level
V
DD
=
10V
75
175
75
200
ns
V
DD
=
15V
57
130
57
150
ns
t
PLH
Propagation Delay
V
DD
=
5V
225
500
225
750
ns
LOW-to-HIGH Level
V
DD
=
10V
75
175
75
200
ns
V
DD
=
15V
57
130
57
150
ns
t
THL
, t
TLH
Transition Time
V
DD
=
5V
70
200
70
200
ns
V
DD
=
10V
35
100
35
100
ns
V
DD
=
15V
25
80
25
80
ns
t
PHZ
, t
PLZ
Propagation Delay into
V
DD
=
5V
50
125
50
125
ns
3-STATE from Logic Level
V
DD
=
10V
25
75
25
75
ns
V
DD
=
15V
19
60
19
60
ns
t
PZH
, t
PZL
Propagation Delay to Logic
V
DD
=
5V
50
125
50
125
ns
Level from 3-STATE
V
DD
=
10V
25
75
25
75
ns
V
DD
=
15V
19
60
19
60
ns
C
IN
Input Capacitance
(Note 5)
7.5
15
7.5
15
pF
C
OUT
3-STATE Output
(Note 5)
7.5
15
7.5
15
pF
Capacitance
C
PD
Power Dissipation Capacity
(Note 6)
150
150
pF
5
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CD451
2BC
Typical Application
Serial Data Routing Interface
AC Test Circuit and Switching Time Waveforms
Input Connections for t
r
, t
f
, t
PLH
, t
PHL
Test
Inhibit
A
X0
1
PG
GND
V
DD
2
GND
PG
V
DD
3
GND
GND
PG