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Part Number CD40193BC

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October 1987
Revised January 1999
CD401
92BC

· C
D
40
193BC
Sync
hr
onous
4-
Bit
U
p
/
D
o
w
n Decade C
o
unter

· Sync
hr
onous 4-
B
i
t

Up/
D
o
w
n
Bi
nar
y
Coun
ter
© 1999 Fairchild Semiconductor Corporation
DS005988.prf
www.fairchildsemi.com
CD40192BC · CD40193BC
Synchronous 4-Bit Up/Down Decade Counter ·
Synchronous 4-Bit Up/Down Binary Counter
General Description
The CD40192BC and CD40193BC up/down counters are
monolithic complementary MOS (CMOS) integrated cir-
cuits. The CD40192BC is a BCD counter, while the
CD40193BC is a binary counter.
Counting up and counting down is performed by two count
inputs, one being held HIGH while the other is clocked. The
outputs change on the positive-going transition of this
clock.
These counters feature preset inputs that are enabled
when load is a logical "0" and a clear which forces all out-
puts to "0" when it is at logical "1". The counters also have
carry and borrow outputs so that they can be cascaded
using no external circuitry.
All inputs are protected against damage due to static dis-
charge by clamps to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
3V to 15V
s
High noise immunity:
0.45 V
DD
(typ.)
s
Low power TTL compatibility:
Fan out of 2 driving 74L
or 1 driving 74LS
s
Carry and borrow outputs for easy expansion to N-bit by
cascading
s
Asynchronous clear
s
Equivalent to:
MM74C192 and MM74C193
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Cascading Packages
Order Number
Package Number
Package Description
CD40192BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD40193BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD40193BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body
www.fairchildsemi.com
2
CD4019
2BC

· C
D
401
93BC
Block Diagrams
CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BC Synchronous 4-Bit Up/Down Binary Counter
3
www.fairchildsemi.com
CD401
92BC

· C
D
40
193BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The "Recommended
Operating Conditions" and Electrical Characteristics tables provide condi-
tions for actual device operation.
Note 2: V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: I
OH
and I
OL
are tested one output at a time.
DC Supply Voltage (V
DD
)
-
0.5 to
+
18 V
DC
Input Voltage (V
IN
)
-
0.5 to V
DD
+
0.5 V
DC
Storage Temperature Range (T
S
)
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
Dual-In-Line 700
mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
DC Supply Voltage (V
DD
)
3 to 15 V
DC
Input Voltage (V
IN
)
0 to V
DD
V
DC
Operating Temperature Range (T
A
)
CD40192BC, CD40193BC
-
40
°
C to
+
85
°
C
Symbol
Parameter
Conditions
-
40
°
C
+
25
°
C
+
85
°
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
=
5V, V
IN
=
V
DD
or V
SS
20
20
150
µ
A
Current
V
DD
=
10V, V
IN
=
V
DD
or V
SS
40
40
300
µ
A
V
DD
=
15V, V
IN
=
V
DD
or V
SS
80
80
600
µ
A
V
OL
LOW Level
V
DD
=
5V
0.05
0.05
0.05
V
Output Voltage
V
DD
=
10V
0.05
0.05
0.05
V
V
DD
=
15V
0.05
0.05
0.05
V
V
OH
HIGH Level
V
DD
=
5V
4.95
4.95
4.95
V
Output Voltage
V
DD
=
10V
9.95
9.95
9.95
V
V
DD
=
15V
14.95
14.95
14.95
V
V
IL
LOW Level
V
DD
=
5V, V
O
=
0.5V or 4.5V
1.5
1.5
1.5
V
Input Voltage
V
DD
=
10V, V
O
=
1V or 9V
3.0
3.0
3.0
V
V
DD
=
15V, V
O
=
1.5V or 13.5V
4.0
4.0
4.0
V
V
IH
HIGH Level
V
DD
=
5V, V
O
=
0.5V or 4.5V
3.5
3.5
3.5
V
Input Voltage
V
DD
=
10V, V
O
=
1V or 9V
7.0
7.0
7.0
V
V
DD
=
15V, V
O
=
1.5V or 13.5V
11.0
11.0
11.0
V
I
OL
LOW Level Output
V
DD
=
5V, V
O
=
0.4V
0.52
0.44
0.88
0.36
mA
Current (Note 4)
V
DD
=
10V, V
O
=
0.5V
1.3
1.1
2.25
0.9
mA
V
DD
=
15V, V
O
=
1.5V
3.6
3.0
8.8
2.4
mA
I
OH
HIGH Level Output
V
DD
=
5V, V
O
=
4.6V
-
0.52
-
0.44
-
0.88
-
0.36 mA
Current (Note 4)
V
DD
=
10V, V
O
=
9.5V
-
1.3
-
1.1
-
2.25
-
0.9
mA
V
DD
=
15V, V
O
=
13.5V
-
3.6
-
3.0
-
8.8
-
2.4
mA
I
IN
Input Current
V
DD
=
15V, V
IN
=
0V
-
0.3
-
10
-
5
-
0.3
-
1.0
µ
A
V
DD
=
15V, V
IN
=
15V
0.3
10
-
5
0.3
1.0
µ
A
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4
CD4019
2BC

· C
D
401
93BC
AC Electrical Characteristics
(Note 3)
T
A
=
25
°
C, C
L
=
50 pF, R
L
=
200 k
, input t
r
=
t
f
=
20 ns, unless otherwise specified.
Note 5: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,
AN-90.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
250
400
ns
from Count Up or
V
DD
=
10V
100
160
ns
Count Down to Q
V
DD
=
15V
80
130
ns
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
120
200
ns
from Count Up to Carry
V
DD
=
10V
50
80
ns
V
DD
=
15V
40
65
ns
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
120
200
ns
from Count Down
V
DD
=
10V
50
80
ns
to Borrow
V
DD
=
15V
40
65
ns
t
SU
Time Prior to Load
V
DD
=
5V
100
160
ns
That Data Must
V
DD
=
10V
30
50
ns
Be Present
V
DD
=
15V
25
40
ns
t
PHL
Propagation Delay Time
V
DD
=
5V
130
220
ns
from Clear to Q
V
DD
=
10V
60
100
ns
V
DD
=
15V
50
80
ns
t
PLH
or t
PHL
Propagation Delay Time
V
DD
=
5V
300
480
ns
from Load to Q
V
DD
=
10V
120
190
ns
V
DD
=
15V
95
150
ns
t
TLH
or t
THL
Output Transition Time
V
DD
=
5V
100
200
ns
V
DD
=
10V
50
100
ns
V
DD
=
15V
40
80
ns
f
CL
Maximum Count Frequency
V
DD
=
5V
2.5
4
MHz
V
DD
=
10V
6
10
MHz
V
DD
=
15V
7.5
12.5
MHz
t
rCL
or t
fCL
Maximum Count Rise
V
DD
=
5V
15
µ
s
or Fall Time
V
DD
=
10V
5
µ
s
V
DD
=
15V
1
µ
s
t
WH
, t
WL
Minimum Count Pulse
V
DD
=
5V
120
200
ns
Width
V
DD
=
10V
35
80
ns
V
DD
=
15V
28
65
ns
t
WH
Minimum Clear
V
DD
=
5V
300
480
ns
Pulse Width
V
DD
=
10V
120
190
ns
V
DD
=
15V
95
150
ns
t
WL
Minimum Load
V
DD
=
5V
100
160
ns
Pulse Width
V
DD
=
10V
40
65
ns
V
DD
=
15V
32
55
ns
C
IN
Average Input Capacitance
Load and Data
5
7.5
pF
Inputs (A,B,C,D)
Count Up, Count
10
15
pF
Down and Clear
C
PD
Power Dissipation Capacity
(Note 5)
100
pF
5
www.fairchildsemi.com
CD401
92BC

· C
D
40
193BC
Timing Diagrams
CD40192BC
Sequence:
1. Clear outputs to zero.
2. Load (preset) to BCD seven.
3. Count up to eight, nine, carry, zero, one and two.
4. Count down to one, zero, borrow, nine, eight and seven.
CD40193BC
Sequence:
1. Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one and two.
4. Count down to one, zero, borrow, fifteen, fourteen and thirteen.