© 2000 Fairchild Semiconductor Corporation
DS005945
www.fairchildsemi.com
October 1987
Revised June 2000
CD401
0C
Hex Buff
ers (Non-
Inv
e
rt
ing)
CD4010C
Hex Buffers (Non-Inverting)
General Description
The CD4010C hex buffers are monolithic complementary
MOS (CMOS) integrated circuits. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swings essentially equal to the supply volt-
age. This results in high noise immunity over a wide supply
voltage range. No DC power other than that caused by
leakage current is consumed during static conditions. All
inputs are protected against static discharge. These gates
may be used as hex buffers, CMOS to DTL or TTL inter-
face or as CMOS current drivers. Conversion ranges are
from 3V to 15V providing V
CC
V
DD
. The devices also
have buffered outputs which improve transfer characteris-
tics by providing very high gain.
Features
s
Wide supply voltage range:
3.0V to 15V
s
Low power:
100 nW (typ.)
s
High noise immunity:
0.45 V
DD
(typ.)
s
High current sinking:
8 mA (min.) at V
O
=
0.5V
capability:
and V
DD
=
10V
Applications
· Automotive
· Data terminals
· Instrumentation
· Medical electronics
· Alarm system
· Industrial controls
· Remote metering
· Computers
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Schematic Diagram
Hex COS/MOS to DTL or TTL
converter (inverting).
Connect V
CC
to DTL or TTL supply.
Connect V
DD
to COS/MOS supply.
Order Number
Package Number
Package Description
CD4010CM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4010CN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
CD401
0C
Absolute Maximum Ratings
(Note 1)
Note 1: "Absolute Maximum Ratings indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which
the device is functional, but do not guarantee specific performance limits."
Note 2: This device should not be connected to circuits with the power on
because high transient voltage may cause permanent damage.
DC Electrical Characteristics
Note 3: I
D
N and I
D
P are tested one output at a time.
Voltage at Any Pin (Note 2)
V
SS
-
0.3V to V
SS
+
15.5V
Operating Temperature Range
-
45
°
C to
+
85
°
C
Storage Temperature Range (T
S
)
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
Operating Range (V
DD
)
V
SS
+
3V to V
SS
+
15V
Test Conditions
Limits
Symbol
Characteristics
(Volts)
-
40
°
C
+
25
°
C
+
85
°
C
Units
V
O
V
DD
Min
Max
Min
Typ
Max
Min
Max
I
CC
Quiescent Device
5
3
0.03
3
42
µ
A
Current
10
5
0.05
5
70
µ
A
P
D
Quiescent Device
5
15
0.15
15
210
µ
W
Dissipation/Package
10
50
0.5
50
700
µ
W
Output Voltage
5
0.01
0
0.01
0.05
V
V
OL
LOW Level
10
0.01
0
0.01
0.05
V
V
OH
HIGH Level
5
4.99
4.99
5
4.95
V
10
9.99
9.99
10
9.95
V
Noise Immunity
(All Inputs)
V
NL
V
O
1.5
5
1.6
1.5
2.25
1.4
V
V
O
3.0
10
3.2
3
4.5
2.9
V
V
NH
V
O
3.5
5
1.4
1.5
2.25
1.5
V
V
O
7.0
10
2.9
3
4.5
3
V
Output Drive Current
0.4
5
3.6
3
2.4
mA
I
D
N
N-Channel (Note 3)
0.5
10
9.6
8
6.4
mA
I
D
P
P-Channel (Note 3)
2.5
5
-
1.5
-
1.25
-
1
mA
9.5
10
-
0.72
-
0.6
-
0.48
mA
I
IN
Input Current
10
pA
3
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CD401
0C
AC Electrical Characteristics
(Note 4)
T
A
=
25
°
c, C
L
=
15 pF, unless otherwise noted. Typical Temperature coefficient for all values of V
DD
=
0.3%/
°
C
Note 4: AC Parameters are guaranteed by DC correlated testing.
Typical Application
Test Conditions
Limits
Symbol
Characteristics
V
DD
Min
Typ
Max
Units
(Volts)
t
PHL
Propagation Delay Time:
V
CC
=
V
DD
5
--
15
70
t
PLH
HIGH-to-LOW Level (t
PHL
)
10
--
10
40
ns
V
DD
=
10V
--
10
35
V
CC
=
5V
LOW-to-HIGH Level (t
PLH
)
V
CC
=
V
DD
5
--
50
100
10
--
25
70
V
DD
=
10V
--
15
40
ns
V
CC
=
5V
t
THL
Transition Time:
V
CC
=
V
DD
5
--
20
60
ns
t
TLH
HIGH-to-LOW Level (t
THL
)
10
--
16
50
LOW-to-HIGH Level (t
TLH
)
V
CC
=
V
DD
5
--
80
160
ns
10
--
50
120
Input Capacitance (C
I
)
Any Input
--
5
--
pF
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4
CD401
0C
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Line Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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CD401
0C
Hex Buff
ers (Non-
Inv
e
rt
ing)
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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