April 1989
Revised June 1999
9
403A
Fi
rst
-
I
n
Fir
s
t-
O
u
t
(FI
F
O
)
B
u
f
f
e
r
M
e
mory
© 1999 Fairchild Semiconductor Corporation
DS010193.prf
www.fairchildsemi.com
9403A
First-In First-Out (FIFO) Buffer Memory
General Description
The 9403A is an expandable fall-through type high-speed
First-In First-Out (FIFO) Buffer Memory optimized for high
speed disk or tape controllers and communication buffer
applications. It is organized as 16-words by 4-bits and may
be expanded to any number of words or any number of bits
in multiples of four. Data may be entered or extracted asyn-
chronously in serial or parallel, allowing economical imple-
mentation of buffer memories.
The 9403A has 3-STATE outputs which provide added ver-
satility and is fully compatible with all TTL families.
Features
s
Serial or parallel input
s
Serial or parallel output
s
Expandable without external logic
s
3-STATE outputs
s
Fully compatible with all TTL families
s
Slim 24-pin package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Order Number
Package Number Package Description
9403APC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide
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Unit Loading/Fan Out
Block Diagram
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
D
8
Parallel Data Inputs
2.0/0.667
40
µ
A/400
µ
A
D
S
Serial Data Input
2.0/0.667
40
µ
A/400
µ
A
P
L
Parallel Load Input
2.0/0.667
40
µ
A/400
µ
A
CPSI
Serial Input Clock
2.0/0.667
40
µ
A/400
µ
A
IES
Serial Input Enable
2.0/0.667
40
µ
A/400
µ
A
TTS
Transfer to Stack Input
2.0/0.667
40
µ
A/400
µ
A
OES
Serial Output Enable
2.0/0.667
40
µ
A/400
µ
A
TOS
Transfer Out Serial
2.0/0.667
40
µ
A/400
µ
A
TOP
Transfer Out Parallel
2.0/0.667
40
µ
A/400
µ
A
MR
Master Reset
2.0/0.667
40
µ
A/400
µ
A
OE
Output Enable
2.0/0.667
40
µ
A/400
µ
A
CPSO
Serial Output Clock
2.0/0.667
40
µ
A/400
µ
A
Q
0
- Q
3
Parallel Data Outputs
285/26.7
5.7 mA/16 mA
Q
S
Serial Data Output
285/26.7
5.7 mA/16 mA
IRF
Input Register Full
20/13.3
-
400
µ
A/8 mA
ORE
Output Register Empty
20/13.3
-
400
µ
A/8 mA
3
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9
403A
Functional Description
As shown in the block diagram the 49403A consists of
three sections:
1. An Input Register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
the F
3
flip-flop and resetting the other flip-flops. The Q out-
put of the last flip-flop (FC) is brought out as the "Input
Register Full" output (IRF). After initialization this output is
HIGH.
Parallel Entry--A HIGH on the PL input loads the D
0
-D
3
inputs into the F
0
-F
3
flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry--Data on the D
S
input is serially entered into
the F
3
, F
2
, F
1
, F
0
, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F
0
-F
3
. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 9403A resulting from a 64-bit serial
bit train. B
0
is the first bit, B
63
the last bit.
FIGURE 1. Conceptual Input Section
FIGURE 2. Final Positions in a 9403A Resulting from a 64-Bit Serial Train
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Transfer to the Stack--The outputs of Flip-Flops F
0
-F
3
feed the stack. A LOW level on the TTS input initiates a
"fall-through" action. If the top location of the stack is
empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10) in the control section records the fact that
data has been transferred to the stack. This prevents multi-
ple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initializa-
tion Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 9403A as in most modern FIFO designs, the MR
input only initializes the stack control section and does not
clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3-
STATE 4-bit parallel data bus or on a 3-STATE serial data
bus. The output section generates and receives the neces-
sary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.
FIGURE 3. Conceptual Output Section
Parallel Data Extraction--When the FIFO is empty after a
LOW pulse is applied to MR, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided the "Trans-
fer Out Parallel" (TOP) input is HIGH. As a result of the
data transfer ORE goes HIGH, indicating valid data on the
data outputs (provided the 3-STATE buffer is enabled).
TOP can now be used to clock out the next word. When
TOP goes LOW, ORE will go LOW indicating that the out-
put data has been extracted, but the data itself remains on
the output bus until the next HIGH level at TOP permits the
transfer of the next word (if available) into the Output Reg-
ister. During parallel data extraction CPSO should be LOW.
TOS should be grounded for single slice operation or con-
nected to the appropriate ORE for expanded operation
(see Expansion section).
TOP is not edge triggered. Therefore, if TOP goes HIGH
before data is available from the stack, but data does
become available before TOP goes LOW again, that data
will be transferred into the Output Register. However, inter-
nal control circuitry prevents the same data from being
transferred twice. If TOP goes HIGH and returns to LOW
before data is available from the stack, ORE remains LOW
indicating that there is no valid data at the outputs.
Serial Data Extraction--When the FIFO is empty after a
LOW pulse is applied to MR, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided TOS is
LOW and TOP is HIGH. As a result of the data transfer
ORE goes HIGH indicating valid data in the register. The 3-
STATE Serial Data Output, Q
S
, is automatically enabled
and puts the first data bit on the output bus. Data is serially
shifted out on the HIGH-to-LOW transition of CPSO. To
prevent false shifting, CPSO should be LOW when the new
word is being loaded into the Output Register. The fourth
transition empties the shift register, forces ORE output
LOW and disables the serial output, Q
S
(refer to Figure 3).
For serial operation the ORE output may be tied to the TOS
input, requesting a new word from the stack as soon as the
previous one has been shifted out.
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9
403A
EXPANSION
Vertical Expansion--The 9403A may be vertically
expanded to store more words without external parts. The
interconnection is necessary to form a 46-word by 4-bit
FIFO are shown in Figure 4. Using the same technique,
and FIFO of (15n
+
1)-words by 4-bits can be constructed,
where n is the number of devices. Note that expansion
does not sacrifice any of the 9403A's flexibility for serial/
parallel input and output.
FIGURE 4. A Vertical Expansion Scheme
Horizontal Expansion--The 9403A can also be horizon-
tally expanded to store long words (in multiples of four bits)
without external logic. The interconnections necessary to
form a 16-word by 12-bit FIFO are shown in Figure 5.
Using the same technique, any FIFO of 16 words by 4n bits
can be constructed, where n is the number of devices. The
IRF output of the right most device (most significant device)
is connected to the TTS inputs of all devices. Similarly, the
ORE output of the most significant device is connected to
the TOS inputs of all devices. As in the vertical expansion
scheme, horizontal expansion does not sacrifice any of the
9403A's flexibility for serial/parallel input and output.
Horizontal and Vertical Expansion--The 9403A can be
expanded in both the horizontal and vertical directions
without any external parts and without sacrificing any of its
FIFO's flexibility for serial/parallel input and output. The
interconnections necessary to form a 31-word by 16-bit
FIFO are shown in Figure 6. Using the same technique,
any FIFO of (15m
+
1)-words by (4n)-bits can be con-
structed, where m is the number of devices in a column
and n is the number of devices in a row. Figure 7 and Fig-
ure 8 show the timing diagrams for serial data entry and
extraction for the 31-word by 16-bit FIFO shown in Figure
6. The final position of data after serial insertion of 496 bits
into the FIFO array of Figure 6 is shown in Figure 9.
Interlocking Circuitry--Most conventual FIFO designs
provide status signals analogous to IRF and ORE. How-
ever, when these devices are operated in arrays, variations
in unit to unit operating speed require external gating to
assure all devices have completed an operation. The
9403A incorporates simple but effective "master/slave"
interlocking circuitry to eliminate the need for external gat-
ing.
In the 9403A array of Figure 6 devices 1 and 5 are defined
as "row masters" and the other devices are slaves to the
master in their row. No slave in a given row will initialize its
Input Register until it has received LOW on its IES input
from a row master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go
HIGH until their OES inputs have gone HIGH. This inter-
locking scheme ensures that new input data may be
accepted by the array when the IRF output of the final
slave in that row goes HIGH and that output data for the
array may be extracted when the ORE of the final slave in
the output row goes HIGH.
The row master is established by connecting its IES input
to ground while a slave receives it IES input from the IRF
output of the next higher priority device. When an array of
9403A FIFOs is initialized with a LOW on the MR inputs of
all devices, the IRF outputs of all devices will be HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization. Figure 10 is a conceptual logic diagram
of the internal circuitry which determines master/slave
operation. Whenever MR and IES are LOW, the Master
Latch is set. Whenever TTS goes LOW the Request Initial-
ization Flip-Flop will be set. If the Master Latch is HIGH, the
input Register will be immediately initialized and the
Request Initialization Flip-Flop reset. If the Master Latch is
reset, the Input Register is not initialized until IES goes
LOW. In array operation, activating the TTS initiates a rip-
ple input register initialization from the row master to the
last slave.
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack oper-
ation and sets the ORE Request Flip-Flop. If the Master
Latch is set, the last Output Register Flip-Flop is set and
ORE goes HIGH. If the Master latch is reset, the ORE out-
put will be LOW until an OES input is received.
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FIGURE 5. A Horizontal Expansion Scheme
FIGURE 6. A 31x16 FIFO Array
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403A
FIGURE 7. Serial Data Entry for Array of Figure 6
FIGURE 8. Serial Data Extraction for Array of Figure 6
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FIGURE 9. Final Position of a 496-Bit Serial Input
FIGURE 10. Conceptual Diagram, Interlocking Circuitry
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403A
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
°
C to
+
150
°
C
Ambient Temperature under Bias
-
55
°
C to
+
125
°
C
Junction Temperature under Bias
-
55
°
C to
+
175
°
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
°
C to
+
70
°
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.5
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.4
V
Min
I
OH
=
-
400
µ
A (IRF, ORE)
Voltage
10% V
CC
2.4
I
OH
=
-
5.7 mA (Q
n
, Q
s
)
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
8 mA (IRF, ORE)
Voltage
10% V
CC
0.5
I
OL
=
16 Ma (Q
n
, Q
s
)
I
IH
Input HIGH Current
40
µ
A
Max
V
IN
=
2.7V
I
BVI
Input HIGH Current Breakdown Test
100
µ
A
Max
V
IN
=
7.0V
I
IL
Input LOW Current
-
0.45
mA
Max
V
IN
=
0.4V
I
OZH
Output Leakage Current
100
µ
A
Max
V
OUT
=
2.4V
I
OZL
Output Leakage Current
-
100
µ
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
30
-
130
mA
Max
V
OUT
=
0V
I
CEX
Output HIGH Leakage Current
250
µ
A
Max
V
OUT
=
V
CC
I
CC
Power Supply Current
170
mA
Max
V
O
=
LOW
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AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
°
C
T
A
=
0
°
C to 70
°
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Figure
C
L
=
50 pF
C
L
=
50 pF
Number
Min
Max
Min
Max
t
PHL
Propagation Delay,
1.5
20.0
1.5
21.0
ns
Negative-Going
CPSI to IRF Output
Figure 11
t
PLH
Propagation Delay,
1.5
36.0
1.5
38.0
Figure 12
Negative-Going
TTS to IRF
t
PLH
Propagation Delay,
1.5
28.0
1.5
29.0
ns
Figure 13
t
PHL
Negative-Going
1.5
28.0
1.5
29.0
Figure 14
CPSO to Q
S
Output
t
PLH
Propagation Delay,
1.5
46.0
1.5
48.0
ns
t
PHL
Positive-Going
1.5
46.0
1.5
48.0
Figure 15
TOP to Outputs Q
0
-Q
3
t
PHL
Propagation Delay,
1.5
35.0
1.5
37.0
ns
Figure 13
Negative-Going
Figure 14
CPSO to ORE
t
PHL
Propagation Delay,
1.5
37.0
1.5
39.0
ns
Figure 15
Negative-Going
TOP to ORE
t
PLH
Propagation Delay,
1.5
47.0
1.5
49.0
Positive-Going
TOP to ORE
t
PLH
Propagation Delay,
1.5
42.5
1.5
45.0
ns
Figure 13
Negative-Going
Figure 14
TOS to Positive Going ORE
t
PLH
Propagation Delay,
1.5
28.0
1.5
29.0
ns
Positive-Going
PL to Negative-Going IRF
Figure 17
t
PLH
Propagation Delay,
1.5
24.0
1.5
25.0
Figure 18
Negative-Going
PL to Positive-Going IRF
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403A
AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
°
C
T
A
=
0
°
C to
+
70
°
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Figure
C
L
=
50 pF
C
L
=
50 pF
Number
Min
Max
Min
Max
t
PLH
Propagation Delay,
1.5
39.5
1.5
41.0
ns
Positive-Going
OES to ORE
t
PLH
Propagation Delay,
1.5
20.0
1.5
21.0
ns
Figure 18
Positive-Going
IES to Positive-Going IRF
t
PLH
Propagation Delay,
1.5
20.0
1.5
20.0
ns
MR to IRF
t
PHL
Propagation Delay,
1.5
33.0
1.5
35.0
ns
MR to ORE
t
PZH
Propagation Delay,
1.5
14.0
1.5
14.0
ns
t
PZL
OE to Q
0
, Q
1
, Q
2
, Q
3
1.5
14.0
1.5
14.0
t
PHZ
Propagation Delay,
1.5
14.0
1.5
14.0
t
PLZ
OE to Q
0
, Q
1
, Q
2
, Q
3
1.5
14.0
1.5
14.0
t
PZH
Propagation Delay,
1.5
16.5
1.5
17.0
ns
t
PZL
Negative-Going
1.5
17.0
1.5
17.0
OES to Q
S
t
PHZ
Propagation Delay,
1.5
14.0
1.5
14.0
t
PLZ
Negative-Going
1.5
14.0
1.5
14.0
OES to Q
S
t
PZH
Turn On Time
1.5
60.0
1.5
60.0
ns
t
PZL
TOS to Q
S
1.5
60.0
1.5
60.0
t
DFT
Fall Through Time
500
500
ns
Figure 16
t
AP
Parallel Appearance Time,
-
19.0
6.5
-
20.0
7.0
ns
ORE to Q
0
-Q
3
t
AS
Serial Appearance Time,
-
9.5
14.5
-
10.0
15.0
ORE to Q
S
t
DBU
Bubble-Up Time
470
500
ns
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AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
°
C
T
A
=
0
°
C to
+
70
°
C
Units
Figure
Number
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
15.5
16.0
ns
t
S
(L)
D
S
to Negative CPSI
15.5
16.0
Figure 11
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.0
Figure 12
t
H
(L)
D
S
to CPSI
2.0
2.0
t
S
(L)
Set-Time, LOW
18.0
18.0
ns
Figure 12
Negative-Going IES to CPSI
t
S
(L)
Set-Up Time, LOW
65.0
70.0
ns
Figure 12
Negative-Going TTS to CPSI
t
S
(H)
Set-Up time, HIGH or LOW
0
0
ns
t
S
(L)
Parallel Inputs to PL
0
0
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
Parallel Inputs to PL
0
0
t
W
(H)
CPSI Pulse Width
30
32
ns
Figure 11
t
W
(L)
HIGH or LOW
20
20
Figure 12
t
W
(H)
PL Pulse Width, HIGH
16.5
17.0
ns
Figure 17
Figure 18
t
W
(L)
TTS Pulse Width, LOW
16.0
17.0
ns
Figure 11
Serial or Parallel Mode
Figure 12
Figure 13
Figure 14
t
W
(L)
MR Pulse Width, LOW
15.0
15.0
ns
Figure 16
t
W
(H)
TOP Pulse Width
15.0
17.0
ns
Figure 15
t
W
(L)
HIGH or LOW
15.0
15.0
t
W
(H)
CPSO Pulse Width
17.0
17.0
ns
Figure 13
t
W
(L)
HIGH or LOW
17.0
18.0
Figure 14
t
REC
Recovery Time
16.5
19.0
ns
Figure 16
MR to Any Input
13
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403A
Timing Waveforms
Conditions: stack not full, IES, PL LOW
FIGURE 11. Serial Input, Unexpanded or Master Operation
Conditions: stack not full, IES HIGH when initiated, PL LOW
FIGURE 12. Serial Input, Expanded Slave Operation
Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 13. Serial Output, Unexpanded or Master Operation
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Timing Waveforms
(Continued)
Conditions: data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 14. Serial Output, Slave Operation
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 16. Fall Through Time
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403A
Timing Waveforms
(Continued)
Conditions: stack not full, IES LOW when initialized
FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
Conditions: stack not full, device initialized (Note 3) with IES HIGH
FIGURE 18. Parallel Load, Slave Mode
Note 3: Initialization requires a master reset to occur after power has been applied.
Note 4: TTS normally connected to IRF.
Note 5: If stack if full, IRF will stay LOW.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide
Package Number N24E
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