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Part Number 74LVTH652

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© 2000 Fairchild Semiconductor Corporation
DS012018
www.fairchildsemi.com
April 2000
Revised April 2000
7
4
L
V
TH65
2
Low V
o
l
t
a
ge
Oct
a
l T
r
ans
ceiver
/Regi
st
er w
i
th 3-
ST
A
T
E O
u
t
put
s
74LVTH652
Low Voltage Octal Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function. (See Functional
Description).
The LVTH652 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal transceiver/register is designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment. The LVTH652 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining
low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
-
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 652
s
Latch-up performance exceeds 500 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Order Number
Package Number
Package Description
74LVTH652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH652MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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L
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TH652
Pin Descriptions
Connection Diagram
Truth Table
(Note 1)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
A
0
­A
7
Data Register A Inputs/
3-STATE Outputs
B
0
­B
7
Data Register B Inputs/
3-STATE Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Select Inputs
OEAB, OEBA
Output Enable Inputs
Inputs
Inputs/Outputs
Operating Mode
OEAB
OEBA
CPAB
CPBA
SAB
SBA
A
0
thru A
7
B
0
thru B
7
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
X
X
Store A and B Data
X
H
H or L
X
X
Input
Not Specified
Store A, Hold B
H
H
X
X
Input
Output
Store A in Both Registers
L
X
H or L
X
X
Not Specified
Input
Hold A, Store B
L
L
X
X
Output
Input
Store B in Both Registers
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Store B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
3
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Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
LVTH652.
Data on the A or B data bus, or both can be stored in the
internal D-type flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D-type flip-flops by simulta-
neously enabling OEAB and OEBA. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
Storage
Real-Time Transfer
Bus A to Bus B
Transfer Storage
Data to A or B
OEAB
OEBA
CPAB
CPBA
SAB
SBA
L
L
X
X
X
L
OEAB
OEBA
CPAB
CPBA
SAB
SBA
X
H
X
X
X
L
X
X
X
X
L
H
X
X
OEAB
OEBA
CPAB
CPBA
SAB
SBA
H
H
X
X
L
X
OEAB
OEBA
CPAB
CPBA
SAB
SBA
H
L
H or L
H or L
H
H
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Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I
O
Absolute Maximum Rating must be observed.
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
4.6
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to
+
7.0
Output in HIGH or LOW State (Note 3)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
I
O
DC Output Current
64
V
O
>
V
CC
Output at HIGH State
mA
128
V
O
>
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
±
64
mA
I
GND
DC Ground Current per Ground Pin
±
128
mA
T
STG
Storage Temperature
-
65 to
+
150
°
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH Level Output Current
-
32
mA
I
OL
LOW Level Output Current
64
mA
T
A
Free-Air Operating Temperature
-
40
85
°
C
t/
V
Input Edge Rate, V
IN
=
0.8V­2.0V, V
CC
=
3.0V
0
10
ns/V
5
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DC Electrical Characteristics
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 7)
Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. Output under test held LOW.
Symbol
Parameter
V
CC
T
A
=-
40
°
C to
+
85
°
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
-
1.2
V
I
I
=
-
18 mA
V
IH
Input HIGH Voltage
2.7­3.6
2.0
V
V
O
0.1V or
V
IL
Input LOW Voltage
2.7­3.6
0.8
V
O
V
CC
-
0.1V
V
OH
Output HIGH Voltage
2.7­3.6
V
CC
-
0.2
V
I
OH
=
-
100
µ
A
2.7
2.4
V
I
OH
=
-
8 mA
3.0
2.0
V
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
=
100
µ
A
2.7
0.5
V
I
OL
=
24 mA
3.0
0.4
V
I
OL
=
16 mA
3.0
0.5
V
I
OL
=
32 mA
3.0
0.55
V
I
OL
=
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
µ
A
V
I
=
0.8V
-
75
µ
A
V
I
=
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
µ
A
(Note 4)
Current to Change State
-
500
µ
A
(Note 5)
I
I
Input Current
3.6
10
µ
A
V
I
=
5.5V
Control Pins
3.6
±
1
µ
A
V
I
=
0V or V
CC
Data Pins
3.6
-
5
µ
A
V
I
=
0V
1
µ
A
V
I
=
V
CC
I
OFF
Power OFF Leakage Current
0
±
100
µ
A
0V
V
I
or V
O
5.5V
I
PU/PD
Power Up/Down 3-STATE
0­1.5V
±
100
µ
A
V
O
=
0.5V to 3.0V
Output Current
V
I
=
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
-
5
µ
A
V
O
=
0.0V
I
OZH
3-STATE Output Leakage Current
3.6
5
µ
A
V
O
=
3.6V
I
OZH
+
3-STATE Output Leakage Current
3.6
10
µ
A
V
CC
<
V
O
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
A or B Port Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
I
CCZ
+
Power Supply Current
3.6
0.19
mA
V
CC
V
O
5.5V
Outputs Disabled
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
-
0.6V
(Note 6)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
=
25
°
C
Units
Conditions
(V)
Min
Typ
Max
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 8)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
-
0.8
V
(Note 8)