© 2000 Fairchild Semiconductor Corporation
DS012023
www.fairchildsemi.com
January 2000
Revised January 2000
7
4
L
V
TH16
646 Low
V
o
lt
age 1
6
-Bi
t
T
r
ansce
iver
/Regi
ste
r
wi
th
3-ST
A
T
E Out
puts
74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH16646 contains sixteen non-inverting bidirec-
tional registered bus transceivers providing multiplexed
transmission of data directly from the input bus or from the
internal storage registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. The DIR inputs determine the direction of data flow
through the device. The CPAB and CPBA inputs load data
into the registers on the LOW-to-HIGH transition (see
Functional Description).
The LVTH16646 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH16646 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining
low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides
glitch-free bus loading
s
Outputs source/sink
-
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 16646
s
Latch-up performance exceeds 500 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package Number
Package Description
74LVTH16646MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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74L
VTH16646
Connection Diagram
Pin Descriptions
Truth Table
(Note 1)
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition.
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control
pins.
Pin Names
Description
A
0
A
15
Data Register A Inputs/3-STATE Outputs
B
0
B
15
Data Register B Inputs/3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OE
1
, OE
2
Output Enable Inputs
DIR
n
Direction Control Inputs
Inputs
Data I/O
Output Operation Mode
OE
1
DIR
1
CPAB
1
CPBA
1
SAB
1
SBA
1
A
07
B
07
H
X
H or L
H or L
X
X
Isolation
H
X
X
X
X
Input
Input
Clock A
n
Data into A Register
H
X
X
X
X
Clock B
n
Data Into B Register
L
H
X
X
L
X
A
n
to B
n
--Real Time (Transparent Mode)
L
H
X
L
X
Input
Output Clock A
n
Data to A Register
L
H
H or L
X
H
X
A Register to B
n
(Stored Mode)
L
H
X
H
X
Clock A
n
Data into A Register and Output to B
n
L
L
X
X
X
L
B
n
to A
n
--Real Time (Transparent Mode)
L
L
X
X
L
Output
Input
Clock B
n
Data into B Register
L
L
X
H or L
X
H
B Register to A
n
(Stored Mode)
L
L
X
X
H
Clock B
n
into B Register and Output to A
n
3
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7
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TH16
646
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both. The select (SAB
n
, SBA
n
) controls can multiplex
stored and real-time. The examples shown below demon-
strate the four fundamental bus-management functions
that can be performed.
The direction control (DIR
n
) determines which bus will
receive data when OE
n
is LOW. In the isolation mode (OE
n
HIGH), A data may be stored in one register and/or B data
may be stored in the other register. When an output func-
tion is disabled, the input function is still enabled and may
be used to store and transmit data. Only one of the two
busses, A or B, may be driven at a time.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
Transfer Storage
Data to A or B
Storage
OE DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
OE DIR CPAB CPBA SAB SBA
L
L
X
H or L
X
H
L
H
H or L
X
H
X
OE DIR CPAB CPBA SAB SBA
L
H
X
L
X
L
L
X
X
L
H
X
X
X
X
H
X
X
X
X
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74L
VTH16646
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5
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TH16
646
Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I
O
Absolute Maximum Rating must be observed.
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
4.6
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to
+
7.0
Output in HIGH or LOW State (Note 3)
V
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
I
O
DC Output Current
64
V
O
>
V
CC
Output at HIGH State
mA
128
V
O
>
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
±
64
mA
I
GND
DC Ground Current per Ground Pin
±
128
mA
T
STG
Storage Temperature
-
65 to
+
150
°
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH-Level Output Current
-
32
mA
I
OL
LOW-Level Output Current
64
T
A
Free-Air Operating Temperature
-
40
85
°
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
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