© 2000 Fairchild Semiconductor Corporation
DS500251
www.fairchildsemi.com
September 2000
Revised September 2000
7
4
LCXZ162244 Low
V
o
lt
age 16-Bi
t Buff
er/
L
i
n
e
Dr
iver
wi
th 5V
T
o
l
e
rant
I
nput
s/Out
puts and 26
Seri
es Resist
ors
in
t
h
e
O
u
t
p
u
t
s
74LCXZ162244
Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant
Inputs/Outputs and 26
Series Resistors in the Outputs
General Description
The LCXZ162244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
When V
CC
is between 0 and 1.5V, the LCXZ162244 is in
the high impedance state during power up or power down.
this places the outputs in the high impedance (Z) state pre-
venting intermittent low impedance loading or glitching in
bus oriented applications.
The LCXZ162244 is designed for low voltage (2.7V or
3.3V) V
CC
applications with capability of interfacing to a 5V
signal environment.
In addition the outputs include 26
(nominal) series resis-
tors to reduce overshoot and undershoot and are designed
to sink/source 12 mA at V
CC
=
3.0V.
The LCXZ162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
Guaranteed power up/down high impedance
s
Supports live insertion/withdrawal
s
Outputs have equivalent 26
series resistors
s
2.7V3.6V V
CC
specifications provided
s
5.3 ns t
PD
max (V
CC
=
3.0V), 20
µ
A I
CC
max
s
±
12 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Note 1: Use this Order Number to receive devices in Tape and Reel.
Order Number
Package
Package Description
Number
74LCXZ162244MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TUBES]
74LCXZ162244MEX
(Note 1)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TAPE and REEL]
74LCXZ162244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LCXZ162244MTX
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
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2
74LCXZ162244
Connection Diagram
Logic Symbol
Pin Descriptions
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Functional Description
The LCXZ162244 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is nibble
(4 bits) controlled with each nibble functioning identically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The
3-STATE outputs are controlled by an Output Enable (OE
n
)
input for each nibble. When OE
n
is LOW, the outputs are in
2-state mode. When OE
n
is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Logic Diagram
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
I
0
I
15
Inputs
O
0
O
15
Outputs
Inputs
Outputs
Inputs
Outputs
OE
1
I
0
I
3
O
0
O
3
OE
3
I
8
I
11
O
8
O
11
L
L
L
L
L
L
L
H
H
L
H
H
H
X
Z
H
X
Z
Inputs
Outputs
Inputs
Outputs
OE
2
I
4
I
7
O
4
O
7
OE
4
I
12
I
15
O
12
O
15
L
L
L
L
L
L
L
H
H
L
H
H
H
X
Z
H
X
Z
3
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7
4
LCXZ162244
Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
(Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
7.0
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE or V
CC
=
01.5V
V
-
0.5 to V
CC
+
0.5
Output in HIGH or LOW State (Note 3)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
+
50
V
O
>
V
CC
I
O
DC Output Source/Sink Current
±
50
mA
I
CC
DC Supply Current per Supply Pin
±
100
mA
I
GND
DC Ground Current per Ground Pin
±
100
mA
T
STG
Storage Temperature
-
65 to
+
150
°
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
3-STATE
0
5.5
I
OH
/I
OL
Output Current
V
CC
=
3.0V
-
3.6V
±
12
mA
V
CC
=
2.7V
-
3.0V
±
8
T
A
Free-Air Operating Temperature
-
40
85
°
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
°
C to
+
85
°
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.7
-
3.6
2.0
V
V
IL
LOW Level Input Voltage
2.7
-
3.6
0.8
V
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
µ
A
2.7
-
3.6
V
CC
-
0.2
V
I
OH
=
-
4 mA
2.7
2.2
I
OH
=
-
6 mA
3.0
2.4
I
OH
=
-
8 mA
2.7
I
OH
=
-
12 mA
3.0
2.0
V
OL
LOW Level Output Voltage
I
OL
=
100
µ
A
2.7
-
3.6
0.2
V
I
OL
=
4 mA
2.7
0.4
I
OL
=
6 mA
3.0
0.55
I
OL
=
8 mA
2.7
0.6
I
OL
=
12 mA
3.0
0.8
I
I
Input Leakage Current
0
V
I
5.5V
2.7
-
3.6
±
5.0
µ
A
I
OZ
3-STATE Output Leakage
0
V
O
5.5V
2.7
-
3.6
±
5.0
µ
A
V
I
=
V
IH
or V
IL
I
OFF
Power-Off Leakage Current
V
I
or V
O
=
5.5V
0
10
µ
A
I
PU/PD
Power Up/Down
V
O
=
0.5V to V
CC
0
-
1.5
±
5.0
µ
A
3-STATE Output Current
V
I
=
GND or V
CC
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.7
-
3.6
225
µ
A
3.6V
V
I
, V
O
5.5V (Note 5)
2.7
-
3.6
±
225
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.7
-
3.6
500
µ
A
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4
74LCXZ162244
DC Electrical Characteristics
(Continued)
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
T
A
=
-
40
°
C to
+
85
°
C, R
L
=
500
Units
V
CC
=
3.3V
±
0.3V
V
CC
=
2.7V
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
PHL
Propagation Delay
1.0
5.3
1.0
6.0
ns
t
PLH
Data to Output
1.0
5.3
1.0
6.0
t
PZL
Output Enable Time
1.0
6.3
1.0
7.1
ns
t
PZH
1.0
6.3
1.0
7.1
t
PLZ
Output Disable Time
1.0
5.4
1.0
5.7
ns
t
PHZ
1.0
5.4
1.0
5.7
t
OSHL
Output to Output Skew (Note 6)
1.0
ns
t
OSLH
1.0
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
0.8
V
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
-
0.8
V
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
7
pF
C
OUT
Output Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10 MHz
20
pF
5
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7
4
LCXZ162244
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and t
rec
Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
R
= t
F
= 3ns)
V
I
C
L
6V for V
CC
=
3.3V, 2.7V
50 pF
V
CC
* 2 for V
CC
=
2.5V
30 pF
Symbol
V
CC
3.3V
±
0.3V
2.7V
V
mi
1.5V
1.5V
V
mo
1.5V
1.5V
V
x
V
OL
+
0.3V
V
OL
+
0.3V
V
y
V
OH
-
0.3V
V
OH
-
0.3V
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6
74LCXZ162244
Schematic Diagram
Generic for LCX Family
7
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7
4
LCXZ162244
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS48A
www.fairchildsemi.com
8
74LCXZ162244 Low
V
o
l
t
age 16-
B
i
t Buff
er/
L
i
ne
Dr
iver
wi
th 5V
T
o
l
e
rant
I
nput
s/Out
puts and 26
Ser
i
es
Resis
t
ors
i
n
t
he
O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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