© 2001 Fairchild Semiconductor Corporation
DS012575
www.fairchildsemi.com
October 1995
Revised March 2001
7
4
LCX841 Low
V
o
lt
age 10
-Bi
t
T
r
anspar
ent
Lat
c
h wi
th
5V T
o
l
e
ran
t
Input
s a
nd Out
puts
74LCX841
Low Voltage 10-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
General Description
The LCX841 consists of ten latches with 3-STATE outputs
for bus organized system applications. The device is
designed for low voltage (2.5V or 3.3V) V
CC
applications
with capability of interfacing to a 5V signal environment.
The LCX841 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V
-
3.6V V
CC
specifications provided
s
8.0 ns t
PD
max (V
CC
=
3.3V), 10
µ
A I
CC
max
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human Body Model
>
2000V
Machine Model
>
200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74LCX841WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LCX841MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX841MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
www.fairchildsemi.com
2
74LCX841
Pin Descriptions
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impendance
NC
=
No Change
Functional Description
The LCX841 consists of ten D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
D
0
D
9
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O
0
O
9
3-STATE Latch Outputs
Inputs
Internal
Output
Function
OE
LE
D
Q
O
X
X
X
X
Z
High Z
H
H
L
L
Z
High Z
H
H
H
H
Z
High Z
H
L
X
NC
Z
Latched
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
NC
NC
Latched
3
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7
4
LCX841
Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
(Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
7.0
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to V
CC
+
0.5
Output in HIGH or LOW State (Note 3)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
+
50
V
O
>
V
CC
I
O
DC Output Source/Sink Current
±
50
mA
I
CC
DC Supply Current per Supply Pin
±
100
mA
I
GND
DC Ground Current per Ground Pin
±
100
mA
T
STG
Storage Temperature
-
65 to
+
150
°
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
3-STATE
0
5.5
I
OH
/I
OL
Output Current
V
CC
=
3.0V
-
3.6V
±
24
mA
V
CC
=
2.7V
-
3.0V
±
12
V
CC
=
2.3V
-
2.7V
±
8
T
A
Free-Air Operating Temperature
-
40
85
°
C
t/
V
Input Edge Rate, V
IN
=
0.8V
-
2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
°
C to
+
85
°
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.3
-
2.7
1.7
V
2.7
-
3.6
2.0
V
IL
LOW Level Input Voltage
2.3
-
2.7
0.7
V
2.7
-
3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
µ
A
2.3
-
3.6
V
CC
-
0.2
V
I
OH
=
-
8 mA
2.3
1.8
I
OH
=
-
12 mA
2.7
2.2
I
OH
=
-
18 mA
3.0
2.4
I
OH
=
-
24 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OH
=
100
µ
A
2.3
-
3.6
0.2
V
I
OH
=
8 mA
2.3
0.6
I
OL
=
12 mA
2.7
0.4
I
OL
=
16 mA
3.0
0.4
I
OL
=
24 mA
3.0
0.55
I
I
Input Leakage Current
0
V
I
5.5V
2.3
-
3.6
±
5.0
µ
A
I
OZ
3-STATE Output Leakage
0
V
O
5.5V
2.3
-
3.6
±
5.0
µ
A
V
I
=
V
IH
or V
IL
I
OFF
Power-Off Leakage Current
V
I
or V
O
=
5.5V
0
10
µ
A
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4
74LCX841
DC Electrical Characteristics
(Continued)
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
°
C to
+
85
°
C
Units
(V)
Min
Max
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.3
-
3.6
10
µ
A
3.6V
V
I
, V
O
5.5V (Note 5)
2.3
-
3.6
±
10
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.3
-
3.6
500
µ
A
Symbol
Parameter
T
A
=
-
40
°
C to
+
85
°
C, R
L
=
500
Units
V
CC
=
3.3V
±
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
±
0.2V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
30 pF
Min
Max
Min
Max
Min
Max
t
PHL
Propagation Delay
1.5
7.0
1.5
7.5
1.5
8.4
ns
t
PLH
D
n
to O
n
1.5
7.0
1.5
7.5
1.5
8.4
t
PHL
Propagation Delay
1.5
7.0
1.5
7.5
1.5
8.4
ns
t
PLH
LE to O
n
1.5
7.0
1.5
7.5
1.5
8.4
t
PZL
Output Enable Time
1.5
8.0
1.5
8.5
1.5
9.6
ns
t
PZH
1.5
8.0
1.5
8.5
1.5
9.6
t
PLZ
Output Disable Time
1.5
6.5
1.5
7.0
1.5
7.8
ns
t
PHZ
1.5
6.5
1.5
7.0
1.5
7.8
t
OSHL
Output to Output Skew
1.0
ns
t
OSLH
(Note 6)
1.0
t
S
Setup Time D
n
to LE
2.5
2.5
4.0
ns
t
H
Hold Time D
n
to LE
1.5
1.5
2.0
ns
t
W
LE Pulse Width
3.3
3.3
4.0
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
0.6
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
-
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
-
0.6
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
7
pF
C
O
Output Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10 MHz
20
pF
5
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7
4
LCX841
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and t
rec
Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
r
= t
f
= 3ns)
Test
Switch
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6V at V
CC
=
3.3
±
0.3V
V
CC
x 2 at V
CC
=
2.5
±
0.2V
t
PZH
,t
PHZ
GND
Symbol
V
CC
3.3V
±
0.3V
2.7V
2.5V
±
0.2V
V
mi
1.5V
1.5V
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
x
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
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6
74LCX841
Schematic Diagram
Generic for LCX Family
7
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7
4
LCX841
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
www.fairchildsemi.com
8
74LCX841 Low
V
o
lt
age 10-Bi
t T
r
an
sparent
La
tch w
i
t
h
5V T
o
ler
ant Inp
u
ts and O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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