© 2001 Fairchild Semiconductor Corporation
DS012578
www.fairchildsemi.com
October 1995
Revised April 2001
7
4
LCX16841 Low
V
o
lt
age 20-Bi
t T
r
ans
p
arent
Lat
c
h w
i
th
5V T
o
ler
a
nt Inpu
ts and
Out
puts
74LCX16841
Low Voltage 20-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
General Description
The LCX16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX16841 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX16841 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V3.6V V
CC
specifications provided
s
5.5 ns t
PD
max (V
CC
=
3.3V), 20
µ
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
Package Description
74LCX16841MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LCX16841MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
D
0
D
19
Inputs
O
0
O
19
Outputs
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2
74LCX16841
Connection Diagram
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
O
0
=
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Functional Description
The LCX16841 contains twenty D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
20-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the D
n
enters the latches. In this condition the latches are
transparent, i.e. a latch output will change states each time
its D input changes. When LE
n
is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The
3-STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OE
n
is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
LE
1
OE
1
D
0
D
9
O
0
O
9
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
Inputs
Outputs
LE
2
OE
2
D
10
D
19
O
10
O
19
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
3
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7
4
LCX16841
Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
(Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
7.0
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to V
CC
+
0.5
Output in HIGH or LOW State (Note 3)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
+
50
V
O
>
V
CC
I
O
DC Output Source/Sink Current
±
50
mA
I
CC
DC Supply Current per Supply Pin
±
100
mA
I
GND
DC Ground Current per Ground Pin
±
100
mA
T
STG
Storage Temperature
-
65 to
+
150
°
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
3-STATE
0
5.5
I
OH
/I
OL
Output Current
V
CC
=
3.0V
-
3.6V
±
24
mA
V
CC
=
2.7V
-
3.0V
±
12
V
CC
=
2.3V
-
2.7V
±
8
T
A
Free-Air Operating Temperature
-
40
85
°
C
t/
V
Input Edge Rate, V
IN
=
0.8V
-
2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
°
C to
+
85
°
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.3
-
2.7
1.7
V
2.7
-
3.6
2.0
V
IL
LOW Level Input Voltage
2.3
-
2.7
0.7
V
2.7
-
3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
µ
A
2.3
-
3.6
V
CC
-
0.2
V
I
OH
=
-
8 mA
2.3
1.8
I
OH
=
-
12 mA
2.7
2.2
I
OH
=
-
18 mA
3.0
2.4
I
OH
=
-
24 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OL
=
100
µ
A
2.3
-
3.6
0.2
V
I
OL
=
8 mA
2.3
0.6
I
OL
=
12 mA
2.7
0.4
I
OL
=
16 mA
3.0
0.4
I
OL
=
24 mA
3.0
0.55
I
I
Input Leakage Current
0
V
I
5.5V
2.3
-
3.6
±
5.0
µ
A
I
OZ
3-STATE Output Leakage
0
V
O
5.5V
2.3
-
3.6
±
5.0
µ
A
V
I
=
V
IH
or V
IL
I
OFF
Power-Off Leakage Current
V
I
or V
O
=
5.5V
0
10
µ
A
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4
74LCX16841
DC Electrical Characteristics
(Continued)
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
°
C to
+
85
°
C
Units
(V)
Min
Max
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.3
-
3.6
20
µ
A
3.6V
V
I
, V
O
5.5V (Note 5)
2.3
-
3.6
±
20
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.3
-
3.6
500
µ
A
Symbol
Parameter
T
A
=
-
40
°
C to
+
85
°
C, R
L
=
500
Units
V
CC
=
3.3V
±
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
±
0.2V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
30 pF
Min
Max
Min
Max
Min
Max
t
PHL
Propagation Delay
1.5
5.5
1.5
6.0
1.5
6.6
ns
t
PLH
D
n
to O
n
1.5
5.5
1.5
6.0
1.5
6.6
t
PHL
Propagation Delay
1.5
5.5
1.5
6.5
1.5
6.6
ns
t
PLH
LE to O
n
1.5
5.5
1.5
6.5
1.5
6.6
t
PZL
Output Enable Time
1.5
6.5
1.5
7.0
1.5
8.5
ns
t
PZH
1.5
6.5
1.5
7.0
1.5
8.5
t
PLZ
Output Disable Time
1.5
6.5
1.5
7.0
1.5
7.8
ns
t
PHZ
1.5
6.5
1.5
7.0
1.5
7.8
t
OSHL
Output to Output Skew (Note 6)
1.0
ns
t
OSLH
1.0
t
S
Setup Time, D
n
to LE
2.5
2.5
3.0
ns
t
H
Hold Time, D
n
to LE
1.5
1.5
2.0
ns
t
W
LE Pulse Width
3.3
3.3
3.8
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
0.6
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
-
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
-
0.6
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
7
pF
C
O
Output Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10 MHz
20
pF
5
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7
4
LCX16841
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and t
rec
Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
r
= t
f
= 3ns)
Test
Switch
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6V at V
CC
=
3.3
±
0.3V
V
CC
x 2 at V
CC
=
2.5
±
0.2V
t
PZH
,t
PHZ
GND
Symbol
V
CC
3.3V
±
0.3V
2.7V
2.5V
±
0.2V
V
mi
1.5V
1.5V
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
x
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
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