© 1999 Fairchild Semiconductor Corporation
DS009523
www.fairchildsemi.com
May 1988
Revised August 1999
7
4F373 O
c
t
a
l
T
r
ansparent
Latch wit
h
3-
ST
A
T
E Output
s
74F373
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Features
s
Eight latches in a single package
s
3-STATE outputs for bus interfacing
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F373SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F373MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F373PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F373
Unit Loading/Fan Out
Functional Description
The 74F373 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance State
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
D
7
Data Inputs
1.0/1.0
20
µ
A/
-
0.6 mA
LE
Latch Enable Input (Active HIGH)
1.0/1.0
20
µ
A/
-
0.6 mA
OE
Output Enable Input (Active LOW)
1.0/1.0
20
µ
A/
-
0.6 mA
O
0
O
7
3-STATE Latch Outputs
150/40 (33.3)
-
3 mA/24 mA (20 mA)
Inputs
Output
LE
OE
D
n
O
n
H
L
H
H
H
L
L
L
L
L
X
O
n
(no change)
X
H
X
Z
3
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7
4F373
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
°
C to
+
150
°
C
Ambient Temperature under Bias
-
55
°
C to
+
125
°
C
Junction Temperature under Bias
-
55
°
C to
+
150
°
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
°
C to
+
70
°
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA
Voltage
I
IH
Input HIGH
5.0
µ
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
µ
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
µ
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
µ
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
µ
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OZH
Output Leakage Current
50
µ
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
µ
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
µ
A
0.0V
V
OUT
=
5.25V
I
CCZ
Power Supply Current
38
55
mA
Max
V
O
=
HIGH Z
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4
74F373
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
°
C
T
A
=
-
55
°
C to
+
125
°
C
T
A
=
0
°
C to
+
70
°
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
3.0
5.3
7.0
3.0
8.5
3.0
8.0
ns
t
PHL
D
n
to O
n
2.0
3.7
5.0
2.0
7.0
2.0
6.0
t
PLH
Propagation Delay
5.0
9.0
11.5
5.0
15.0
5.0
13.0
ns
t
PHL
LE to O
n
3.0
5.2
7.0
3.0
8.5
3.0
8.0
t
PZH
Output Enable Time
2.0
5.0
11.0
2.0
13.5
2.0
12.0
ns
t
PZL
2.0
5.6
7.5
2.0
10.0
2.0
8.5
t
PHZ
Output Disable Time
1.5
4.5
6.5
1.5
10.0
1.5
7.5
ns
t
PLZ
1.5
3.8
5.0
1.5
7.0
1.5
6.0
Symbol
Parameter
T
A
=
+
25
°
C
T
A
=
-
55
°
C to
+
125
°
C
T
A
=
0
°
C to
+
70
°
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.0
2.0
2.0
ns
t
S
(L)
D
n
to LE
2.0
2.0
2.0
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.0
3.0
t
H
(L)
D
n
to LE
3.0
4.0
3.0
t
W
(H)
LE Pulse Width, HIGH
6.0
6.0
6.0
ns
5
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7
4F373
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
74F373
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
7
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7
4F373 O
c
t
a
l
T
r
ansparent
Latch wit
h
3-
ST
A
T
E Output
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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