DS010891

www.fairchildsemi.com

August 1990

Revised November 1999

74
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Quad

2-I
nput

AND Gat

74ACTQ08
Quiet Series

Quad 2-Input AND Gate

General Description

The ACTQ08 contains four, 2-input AND gates and utilizes
Fairchild Quiet Series

technology to guarantee quiet out-

put switching and improved dynamic threshold perfor-
mance. FACT Quiet Series

features GTO

output control

and undershoot corrector in addition to a split ground bus
for superior ACMOS performance.

Features

reduced by 50%

Guaranteed simultaneous switching noise level and
dynamic threshold performance

Improved latch-up immunity

Outputs source/sink 24 mA

TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT

, Quiet Series

, FACT Quiet Series

and GTO

are trademarks of Fairchild Semiconductor Corporation.

Order Number

Package Number

Package Description

74ACTQ08SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body

74ACTQ08SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACTQ08PC

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names

Description

, B

Inputs

Outputs

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74ACTQ

Absolute Maximum Ratings

(Note 1)

Recommended Operating
Conditions

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation outside of databook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: DIP package.

Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.

Note 6: Max number of data inputs (n) switching. (n

1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:

3V to threshold (V

ILD

), 0V to threshold (V

IHD

), f

1 MHz.

Supply Voltage (V

)

0.5V to

7.0V

DC Input Diode Current (I

)

0.5V

20 mA

0.5V

20 mA

DC Input Voltage (V

)

0.5V to V

0.5V

DC Output Diode Current (I

)

0.5V

20 mA

0.5V

20 mA

DC Output Voltage (V

)

0.5V to V

0.5V

DC Output Source

or Sink Current (I

)

50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

)

50 mA

Storage Temperature (T

STG

)

C to

150

DC Latch-Up

Source or Sink Current

300 mA

Junction Temperature (T

)

PDIP

140

Supply Voltage (V

)

4.5V to 5.5V

Input Voltage (V

)

0V to V

Output Voltage (V

)

0V to V

Operating Temperature (T

)

C to

Minimum Input Edge Rate (

125 mV/ns

from 0.8V to 2.0V

@ 4.5V, 5.5V

Symbol

Parameter

C to

Units

Conditions

(V)

Typ

Guaranteed Limits

Minimum HIGH Level

4.5

1.5

2.0

OUT

0.1V

Input Voltage

5.5

1.5

2.0

or V

0.1V

Maximum LOW Level

4.5

1.5

0.8

OUT

0.1V

Input Voltage

5.5

1.5

0.8

or V

0.1V

Minimum HIGH Level

4.5

4.49

4.4

OUT

Output Voltage

5.5

5.49

5.4

or V

4.5

3.86

3.76

24 mA

5.5

4.86

4.76

24 mA (Note 2)

Maximum LOW Level

4.5

0.001

0.1

OUT

Output Voltage

5.5

0.001

0.1

or V

4.5

0.36

0.44

24 mA

5.5

0.36

0.44

24 mA (Note 2)

Maximum Input Leakage Current

5.5

0.1

1.0

, GND

CCT

Maximum I

/Input

5.5

0.6

1.5

2.1V

OLD

Minimum Dynamic

5.5

OLD

1.65V Max

OHD

Output Current (Note 3)

5.5

OHD

3.85V Min

Maximum Quiescent Supply Current

5.5

2.0

20.0

or GND

OLP

Quiet Output
Maximum Dynamic V

5.0

1.1

1.5

Figure 1, Figure 2
(Note 4)(Note 5)

OLV

Quiet Output
Minimum Dynamic V

5.0

0.6

1.2

Figure 1, Figure 2
(Note 4)(Note 5)

IHD

Minimum HIGH Level Dynamic Input Voltage

5.0

1.9

2.2

(Note 4)(Note 6)

ILD

Maximum LOW Level Dynamic Input Voltage

5.0

1.2

0.8

(Note 4)(Note 6)

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74
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AC Electrical Characteristics

Note 7: Voltage Range 5.0 is 5.0V

0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by design.

Capacitance

C to

Symbol

Parameter

(V)

50 pF

Units

(Note 7)

Min

Typ

Max

Min

Max

PLH

Propagation Delay Data to Output

5.0

2.5

6.0

6.5

2.5

7.0

PHL

Propagation Delay Data to Output

5.0

2.5

6.0

6.5

2.5

7.0

OSHL

Output to Output

5.0

0.5

1.0

OSLH

Skew (Note 8)

Symbol

Parameter

Typ

Units

Conditions

Input Capacitance

4.5

OPEN

Power Dissipation Capacitance

5.0V

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74ACTQ

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.

Equipment:

Hewlett Packard Model 8180A Word Generator

PC-163A Test Fixture

Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF,

500

2. Deskew the HFS generator so that no two channels

have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.

3. Terminate all inputs and outputs to ensure proper load-

ing of the outputs and that the input levels are at the
correct voltage.

4. Set the HFS generator to toggle all but one output at a

frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.

OHV

and V

OLP

are measured with respect to ground reference.

Input pulses have the following characteristics: f

1 MHz, t

3 ns, t

3 ns, skew

150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

5. Set the HFS generator input levels at 0V LOW and 3V

HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.

OLP

OLV

and V

OHP

OHV

· Determine the quiet output pin that demonstrates the

greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50

coaxial cable plugged into a standard

SMB type connector on the test fixture. Do not use an
active FET probe.

· Measure V

OLP

and V

OLV

on the quiet output during

worst case transition for active and enable. Measure
V

OHP

and V

OHV

on the quiet output during the worst

case active and enable transition.

· Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.

ILD

and V

IHD

· Monitor one of the switching outputs using a 50

coaxial

cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.

· First increase the input LOW voltage level, V

, until the

output begins to oscillator steps out a min of 2 ns. Oscil-
lation is defined as noise on the output LOW level that
exceeds V

limits, or on output HIGH levels that exceed

limits. The input LOW voltage level at which oscilla-

tion occurs is defined as V

ILD

· Next decrease the input HIGH voltage level, V

, until

the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

· Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74
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Q
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Quad

2-I
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AND Gat

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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Part Number 74ACTQ08