Document Outline
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- PIN DESCRIPTION BY FUNCTION
- FUNCTIONAL DESCRIPTION
- RECEIVER
- TRANSMITTER
- Transmit and Receive Terminations
- MICROPROCESSOR Parallel INTERFACE
- Table 16: Microprocessor interface signal description
- Microprocessor Register Tables
- Microprocessor Register Descriptions
- Table 19: Microprocessor Register #0, Bit Description
- Table 20: Microprocessor Register #1, Bit Description
- Table 21: Microprocessor Register #2, Bit Description
- Table 22: Microprocessor Register #3, Bit Description
- Table 23: Microprocessor Register #4, Bit Description
- Table 24: Microprocessor Register #5, Bit Description
- Table 25: Microprocessor Register #6, Bit Description
- Table 26: Microprocessor Register #7, Bit Description
- Table 27: Microprocessor Register #8, Bit Description
- Table 28: Microprocessor Register #9, Bit Description
- Table 29: Microprocessor Register #10, Bit Description
- Table 30: Microprocessor Register #11, Bit Description
- Table 31: Microprocessor Register #12, Bit Description
- Table 32: Microprocessor Register #13, Bit Description
- Table 33: Microprocessor Register #14, Bit Description
- Table 34: Microprocessor Register #15, Bit Description
- Table 35: Microprocessor Register #128, Bit Description
- clock select register
- ELECTRICAL CHARACTERISTICS
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
·
(510) 668-7000
·
FAX (510) 668-7017
·
www.exar.com
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2004
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83L38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100
, E1 (2.048Mbps) 75
or
120
,
or J1 110
applications.
In long-haul applications the XRT83L38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83L38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83L38 provides both a parallel Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75
,
100
,
110
and 120
for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
·
T1 Digital Cross-Connects (DSX-1)
·
ISDN Primary Rate Interface
·
CSU/DSU E1/T1/J1 Interface
·
T1/E1/J1 LAN/WAN Routers
·
Public switching Systems and PBX Interfaces
·
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
F
IGURE
1 B
LOCK
D
IAGRAM
OF
THE
XRT83L38 T1/E1/J1 LIU (H
OST
M
ODE
)
One of Eight channels, CHANNEL_n - (n= 0:7)
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
ICT
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
RTIP_n
RRING_n
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO_n
TTIP_n
TRING_n
TXON_n
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
DRIVE
MONITOR
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SELECT
NLCD ENABLE
QRSS ENABLE
µ
PTS1
µ
PTS2
D[7:0]
µ
PCLK
A[7:0]
RESET
MICROPROCESSOR CONTROLLER
TEST
DFM
TAOS
ENABLE
MCLKE1
MCLKT1
MCLKOUT
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
2
FEATURES
·
Fully integrated eight channel long-haul or short-
haul transceivers for E1,T1 or J1 applications
·
Adaptive Receive Equalizer for up to 36dB cable
attenuation
·
Programable Transmit Pulse Shaper for E1,T1 or J1
short-haul interfaces
·
Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping
available for both T1 and E1 modes
·
Transmit Line Build-Outs (LBO) for T1 long-haul
application from 0dB to -22.5dB in three 7.5dB
steps
·
Selectable receiver sensitivity from 0 to 36dB cable
loss for T1 @772kHz and 0 to 43dB for E1
@1024kHz
·
Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for E1 and 0 to 3dB of cable attenuation for T1
modes
·
Supports 75
and 120
(E1), 100
(T1) and 110
(J1) applications
·
Internal and/or external impedance matching for
75
, 100
,
110
and 120
·
Tri-State transmit output and receive input
capability for redundancy applications
·
Provides High Impedance for Tx and Rx during
power off
·
Transmit return loss meets or exceeds ETSI 300-
166 standard
·
On-chip digital clock recovery circuit for high input
jitter tolerance
·
Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO selectable either in transmit or receive path
·
On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources
·
High receiver interference immunity
·
On-chip transmit short-circuit protection and
limiting, and driver fail monitor output (DMO)
·
Receive loss of signal (RLOS) output
·
On-chip HDB3/B8ZS/AMI encoder/decoder
functions
·
QRSS pattern generator and detection for testing
and monitoring
·
Error and Bipolar Violation Insertion and Detection
F
IGURE
2 B
LOCK
D
IAGRAM
OF
THE
XRT83L38 T1/E1/J1 LIU (H
ARDWARE
M
ODE
)
One of Eight Channels, CHANNEL_n - (n=0 : 7)
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
ICT
MCLKE1
MCLKT1
CLKSEL[2:0]
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
RTIP_n
RRING_n
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO_n
TTIP_n
TRING_n
TXON_n
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SELECT
NLCD ENABLE
QRSS ENABLE
HARWARE CONTROL
TEST
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
DRIVE
MONITOR
DFM
MCLKOUT
TAOS_n
LOOP1_n
LOOP0_n
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
3
·
Receiver Line Attenuation Indication Output in 1dB
steps
·
Network Loop-Code Detection for automatic Loop-
Back Activation/Deactivation
·
Transmit All Ones (TAOS) and In-Band Network
Loop Up and Down code generators
·
Supports Local Analog, Remote, Digital and Dual
Loop-Back Modes
·
Meets or exceeds T1 and E1 short-haul and long-
haul network access specifications in ITU G.703,
G.775, G.736 and G.823; TR-TSY-000499; ANSI
T1.403 and T1.408; ETSI 300-166 and AT&T Pub
62411
·
Supports both Hardware and Host (parallel
Microprocessor) interface for programming
·
Programmable Interrupt
·
Low power dissipation
·
Logic inputs accept either 3.3V or 5V levels
·
Single 3.3V Supply Operation
·
208 pin TQFP or 225 ball BGA package
·
-40°C to +85°C Temperature Range
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT83L38IV
208 Lead TQFP (28 x 28 x 1.4mm)
-40
°
C to +85
°
C
XRT83L38IB
225 Ball BGA
-40
°
C to +85
°
C
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
4
F
IGURE
3 P
IN
O
UT
OF
THE
XRT83L38
XRT83L38
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
RNEG _3 / LCV_3
RCLK_3
RLO S_3
TNEG _3 / CO DES_3
TPO S_3 / T DATA_3
T CLK_3
T CLK_2
TPO S_2 / T DATA_2
TNEG _2 / CO DES_2
DMO _3
JASEL0
JASEL1
TXO N_0
TXO N_1
TXO N_2
TXO N_3
A[7] / LO O P1_3
A[6] / LO O P0_3
A[5] / LO O P1_2
A[4] / LO O P0_2
A[3] / LO O P1_1
A[2] / LO O P0_1
A[1] / LO O P1_0
A[0] / LO O P0_0
DVDD PreD river
DVDD Driver
DVDD
D GND
DG ND Driver
D GND PreDriver
CLKSEL0
CLKSEL1
CLKSEL2
W R_R /W / EQ C0
RD_DS / EQ C1
ALE_AS / EQ C2
CS / EQ C3
RD Y_DT ACK / EQ C4
TAO S_0
TAO S_1
TAO S_2
TAO S_3
DMO _0
TNEG _1 / CO DES_1
TPO S_1 / T DATA_1
T CLK_1
T CLK_0
TPO S_0 / T DATA_0
TNEG _0 / CO DES_0
RLO S_0
RCLK_0
RNEG _0 / LCV_0
RP
O
S
_
0
/
RDA
T
A
_
0
RV
DD_
0
RT
I
P
_
0
RRI
NG
_
0
Ex
VC
M_
0
A
G
ND_
0
TT
I
P
_
0
T
V
DD_
0
TR
I
N
G
_
0
DM
O
_
1
TR
I
N
G
_
1
T
V
DD_
1
TT
I
P
_
1
A
G
ND_
1
Ex
VC
M_
1
RRI
NG
_
1
RT
I
P
_
1
RV
DD_
1
RP
O
S
_
1
/
RDA
T
A
_
1
RNE
G
_
1 /
L
C
V
_
1
RCL
K
_
1
RL
O
S
_
1
MC
L
K
O
U
T
V
D
D
P
LL_1
V
D
D
P
LL_2
MC
L
KE1
MC
L
K
T
1
G
N
D
P
LL_1
G
N
D
P
LL_2
SR
/
D
R
RL
O
S
_
5
RCL
K
_
5
RNE
G
_
5 /
L
C
V
_
5
RP
O
S
_
5
/
RDA
T
A
_
5
RV
DD_
5
RT
I
P
_
5
RRI
NG
_
5
Ex
VC
M_
5
A
G
ND_
5
TT
I
P
_
5
T
V
DD_
5
TR
I
N
G
_
5
DM
O
_
5
TR
I
N
G
_
4
T
V
DD_
4
TT
I
P
_
4
A
G
ND_
4
Ex
VC
M_
4
RRI
NG
_
4
RT
I
P
_
4
RV
DD_
4
RP
O
S
_
4
/
RDA
T
A
_
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
RNEG _7/LCV_7
RCLK_7
RLO S_7
TNEG _7 / CO DES_7
TPO S_7 / TDAT A_7
TCLK_7
TCLK_6
TPO S_6 / TDAT A_6
TNEG _6 / CO DES_6
DMO _7
µ
PCLK / ATAO S
TXO N_7
TXO N_6
TXO N_5
TXO N_4
RXMU TE
ICT
TEST
TERSEL0
TERSEL1
TXT SEL
RXTSEL
RXRES0
RXRES1
HW _HOST
DVDD
DVDD
DG ND
DG ND
RESET
D[0] / LO O P0_7
D[1] / LO O P1_7
D[2] / LO O P0_6
D[3] / LO O P1_6
D[4] / LO O P0_5
D[5] / LO O P1_5
D[6] / LO O P0_4
D[7] / LO O P1_4
TAO S_7
TAO S_6
TAO S_5
TAO S_4
DMO _4
TNEG _5 / CO DES_5
TPO S_5 / TDAT A_5
TCLK_5
TCLK_4
TPO S_4 / TDAT A_4
TNEG _4 / CO DES_4
RLO S_4
RCLK_4
RNEG _4 / LCV_4
RP
O
S
_
3
/
RDA
T
A
_
3
RV
DD_3
RT
I
P
_
3
RRI
NG
_3
Ex
VC
M
_
3
A
G
ND_
3
TT
I
P
_
3
T
V
DD_
3
TR
I
N
G_
3
DM
O
_
2
TR
I
N
G_
2
T
V
DD_
2
TT
I
P
_
2
A
G
ND_
2
Ex
VC
M
_
2
RRI
NG
_2
RT
I
P
_
2
RV
DD_2
RP
O
S
_
2
/
RDA
T
A
_
2
RNE
G
_
2 /
L
C
V
_
2
RCLK
_
2
RLO
S
_
2
GA
U
G
E
uP
T
S
1 /
R
C
L
K
E
AG
N
D
Bi
a
s
DG
ND
µ
P
DV
DD
µ
P
AVD
D
Bi
a
s
uP
T
S
2 /
T
C
LK
E
IN
T
/ T
R
A
T
IO
RLO
S
_
6
RCLK
_
6
RNE
G
_
6 /
L
C
V
_
6
RP
O
S
_
6
/
RDA
T
A
_
6
RV
DD_6
RT
I
P
_
6
RRI
NG
_6
Ex
VC
M
_
6
A
G
ND_
6
TT
I
P
_
6
T
V
DD_
6
TR
I
N
G_
6
DM
O
_
6
TR
I
N
G_
7
T
V
DD_
7
TT
I
P
_
7
A
G
ND_
7
Ex
VC
M
_
7
RRI
NG
_7
RT
I
P
_
7
RV
DD_7
RP
O
S
_
7
/
RDA
T
A
_
7
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
5
NC4
NC12
R
TIP_3
RRING_3
NC1
1
RRING_2
R
TIP_2
RNEG_2
GAUGE
DVDDD_
µP
R
TIP_6
RRING_6
Nc10
NC9
RRING_7
R
TIP_7
R
VDD_7
NC3
18
RCLK_3
RPOS_3
TGND_3
RGND_3
TVDD_3
TTIP_2
RGND_2
DGND_µP
AGND_BI
AS
A
VDD_BIAS
RPOS_6
RGND_6
R
VDD_6
TRING_7
RGND_7
RPOS_7
DMO_6
RNEG_7
17
RLOS_3
RNEG_3
TTIP_3
R
VDDD
_3
TRING_3
TVDD_2
R
VDD_2
RCLK_2
P
TS1
RXON
INT
RNEG_6
TTIP_6
TTIP_7
TGND_7
TGND_6
RCLK_7
TCLK_6
16
TCLK_2
TNEG_3
DMO_2
RPOS_2
TGND_2
TRING_2
DGND_DR
RLOS_2
RLOS_6
DVDD_DR
P
TS2
RCLK_6
TVDD_6
TVDD_7
TRING_6
RLOS_7
TCLK_7
TPOS_6
15
JASEL0
TPOS_2
TCLK_3
TPOS_3
X
R
T83L3
8
(T
op V
i
ew)
225
Ball
BG
A
TNEG_7
TPOS_7
TNEG_6
DMO_7
14
TXON_0
JASEL1
DMO_3
TNEG_2
TXON_7
µPCLK
TXON_5
TXON_4
13
A[7]
TX0N_3
TXON_2
TXON_1
TXON_6
RXMUTE
TEST
ICT
12
A[
3]
A[
6]
A[
5]
A[
4]
TERS
EL0
TERS
EL1
RXTS
EL
TXTS
EL
11
A[1]
A[2]
A[0]
DVDD_
PDR
RXRES1
HW_HOST
DVDD_
PDR
RXRES0
10
DVDD
DGND
DGND_PDR
DVDD_DR
DVDD_DR
DGND_DR
D[1]
D[3]
9
C
LKSEL0
C
LKSEL1
C
LKSEL2
DGND_DR
DGND_PDR
RESET
D[2]
D[4]
8
A
LE_AS
CS
RD
_DS
WR
_R/W
D[0]
D[7]
D[6]
D[5]
7
RDY_D
T
A
CK
T
AOS_
1
T
AOS_
3
T
AOS_
0
T
AOS_
7
T
AOS_
4
T
AOS_
5
T
AOS_
6
6
T
AOS_2
TNEG_1
TPOS_0
DMO_0
R
VDD_1
DMO_4
TCLK_5
TPOS_5
TNEG_5
5
TPOS_
1
TCLK_0
TNEG_0
DMO_1
TVDD_0
TVDD_1
TTIP_1
RLOS_
1
DVDD_D
R
SR_DR
GNDPLL_2
RNEG_5
TRING_5
DMO_5
TVDD_4
RNEG_4
TNEG_4
TPOS_
4
4
TCLK_1
RCLK_0
RLOS_
0
TGND_0
TTIP_0
TRING_1
RGND_1
RCLK_1
VDDPLL_1
GNDPLL_1
RCLK_5
RPOS_
5
R
VDD_5
TGND_5
TGND_4
TCLK_4
RCLK_4
RLOS_
4
3
RNEG_0
RP
OS_0
R
VDD_0
R
GND_0
TRING_O
T
GND_1
RP
OS_1
RNEG_1
VDDPLL_2
D
GND_DR
RL
OS_5
R
GND_5
T
TIP_5
TRING_4
T
TIP_4
R
GND_4
RP
OS_4
R
VDD_4
2
NC1
NC5
RTIP_0
RRI
NG_0
NC6
RRI
NG_1
RTIP_1
MC
LKOUT
MCL
KE1
MCLKT1
RTIP_5
RRI
NG_5
NC7
TVDD_5
NC8
RRI
NG_4
RTIP_4
NC2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
A
PPLICATIONS
................................................................................................................................ 1
F
IGURE
1 B
LOCK
D
IAGRAM
OF
THE
XRT83L38 T1/E1/J1 LIU (H
OST
M
ODE
) .............................................................. 1
F
IGURE
2 B
LOCK
D
IAGRAM
OF
THE
XRT83L38 T1/E1/J1 LIU (H
ARDWARE
M
ODE
) ..................................................... 2
F
EATURES
...................................................................................................................................... 2
ORDERING INFORMATION .................................................................................................................... 3
F
IGURE
3 P
IN
O
UT
OF
THE
XRT83L38 ...................................................................................................................... 4
TABLE OF CONTENTS ..................................................................................................... I
PIN DESCRIPTION BY FUNCTION................................................................................... 5
R
ECEIVE
S
ECTIONS
........................................................................................................................ 5
T
RANSMITTER
S
ECTIONS
................................................................................................................ 7
M
ICROPROCESSOR
I
NTERFACE
..................................................................................................... 11
JITTER
A
TTENUATOR
..................................................................................................................... 14
C
LOCK
S
YNTHESIZER
................................................................................................................... 14
A
LARM
F
UNCTIONS
/R
EDUNDANCY
S
UPPORT
.................................................................................. 16
P
OWER
AND
G
ROUND
................................................................................................................... 20
PINS ONLY AVAILABLE IN BGA PACKAGE ............................................................................ 21
FUNCTIONAL DESCRIPTION ......................................................................................... 22
M
ASTER
C
LOCK
G
ENERATOR
........................................................................................................ 22
F
IGURE
4. T
WO
I
NPUT
C
LOCK
S
OURCE
.................................................................................................................... 22
F
IGURE
5. O
NE
I
NPUT
C
LOCK
S
OURCE
.................................................................................................................... 22
RECEIVER........................................................................................................................ 23
R
ECEIVER
I
NPUT
.......................................................................................................................... 23
T
ABLE
1: M
ASTER
C
LOCK
G
ENERATOR
.................................................................................................................... 23
R
ECEIVE
M
ONITOR
M
ODE
............................................................................................................. 24
R
ECEIVER
L
OSS
OF
S
IGNAL
(RLOS) ............................................................................................. 24
F
IGURE
6. S
IMPLIFIED
D
IAGRAM
OF
-15
D
B T1/E1 S
HORT
H
AUL
M
ODE
AND
RLOS C
ONDITION
.................................. 24
F
IGURE
7. S
IMPLIFIED
D
IAGRAM
OF
-29
D
B T1/E1 G
AIN
M
ODE
AND
RLOS C
ONDITION
.............................................. 25
F
IGURE
8. S
IMPLIFIED
D
IAGRAM
OF
-36
D
B T1/E1 L
ONG
H
AUL
M
ODE
AND
RLOS C
ONDITION
.................................... 25
R
ECEIVE
HDB3/B8ZS D
ECODER
.................................................................................................. 26
R
ECOVERED
C
LOCK
(RCLK) S
AMPLING
E
DGE
.............................................................................. 26
F
IGURE
9. S
IMPLIFIED
D
IAGRAM
OF
E
XTENDED
RLOS
MODE
(E1 O
NLY
) ................................................................... 26
F
IGURE
10. R
ECEIVE
C
LOCK
AND
O
UTPUT
D
ATA
T
IMING
........................................................................................... 26
J
ITTER
A
TTENUATOR
.................................................................................................................... 27
G
APPED
C
LOCK
(JA M
UST
BE
E
NABLED
IN
THE
T
RANSMIT
P
ATH
) .................................................. 27
T
ABLE
2: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
.............................................................. 27
A
RBITRARY
P
ULSE
G
ENERATOR
FOR
T1
AND
E
1 ........................................................................... 28
TRANSMITTER ................................................................................................................ 28
D
IGITAL
D
ATA
F
ORMAT
................................................................................................................. 28
T
RANSMIT
C
LOCK
(TCLK) S
AMPLING
E
DGE
.................................................................................. 28
F
IGURE
11. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
............................................................................................ 28
T
RANSMIT
HDB3/B8ZS E
NCODER
................................................................................................ 29
F
IGURE
12. T
RANSMIT
C
LOCK
AND
I
NPUT
D
ATA
T
IMING
............................................................................................ 29
T
ABLE
3: E
XAMPLES
OF
HDB3 E
NCODING
............................................................................................................... 29
T
ABLE
4: E
XAMPLES
OF
B8ZS E
NCODING
................................................................................................................ 29
D
RIVER
F
AILURE
M
ONITOR
(DMO) ............................................................................................... 30
T
RANSMIT
P
ULSE
S
HAPER
& L
INE
B
UILD
O
UT
(LBO)
CIRCUIT
........................................................ 30
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
................................................. 30
TRANSMIT AND RECEIVE TERMINATIONS ................................................................. 31
RECEIVER (C
HANNELS
0 - 7) ..................................................................................................... 31
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
II
Internal Receive Termination Mode.........................................................................................................31
T
ABLE
6: R
ECEIVE
T
ERMINATION
C
ONTROL
.............................................................................................................. 32
F
IGURE
13. S
IMPLIFIED
D
IAGRAM
FOR
THE
I
NTERNAL
R
ECEIVE
AND
T
RANSMIT
T
ERMINATION
M
ODE
........................... 32
T
ABLE
7: R
ECEIVE
T
ERMINATIONS
............................................................................................................................ 32
F
IGURE
14. S
IMPLIFIED
D
IAGRAM
FOR
T1
IN
THE
E
XTERNAL
T
ERMINATION
M
ODE
(RXTSEL= 0)................................ 33
TRANSMITTER (C
HANNELS
0 - 7) .............................................................................................. 34
Transmit Termination Mode.....................................................................................................................34
External Transmit Termination Mode ......................................................................................................34
F
IGURE
15. S
IMPLIFIED
D
IAGRAM
FOR
E1
IN
E
XTERNAL
T
ERMINATION
M
ODE
(RXTSEL= 0) ...................................... 34
T
ABLE
8: T
RANSMIT
T
ERMINATION
C
ONTROL
............................................................................................................ 34
T
ABLE
9: T
ERMINATION
S
ELECT
C
ONTROL
................................................................................................................ 34
REDUNDANCY APPLICATIONS............................................................................................... 35
T
ABLE
10: T
RANSMIT
T
ERMINATION
C
ONTROL
.......................................................................................................... 35
T
ABLE
11: T
RANSMIT
T
ERMINATIONS
........................................................................................................................ 35
TYPICAL REDUNDANCY SCHEMES ....................................................................................... 36
F
IGURE
16. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
S
ECTION
FOR
1:1 & 1+1 R
EDUNDANCY
.......................... 37
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
- R
ECEIVE
S
ECTION
FOR
1:1
AND
1+1 R
EDUNDANCY
.................................. 37
F
IGURE
18. S
IMPLIFIED
B
LOCK
D
IAGRAM
- T
RANSMIT
S
ECTION
FOR
N+1 R
EDUNDANCY
............................................. 38
F
IGURE
19. S
IMPLIFIED
B
LOCK
D
IAGRAM
- R
ECEIVE
S
ECTION
FOR
N+1 R
EDUNDANCY
............................................... 39
P
ATTERN
T
RANSMIT
AND
D
ETECT
F
UNCTION
................................................................................. 40
T
RANSMIT
A
LL
O
NES
(TAOS)....................................................................................................... 40
N
ETWORK
L
OOP
C
ODE
D
ETECTION
AND
T
RANSMISSION
................................................................ 40
T
ABLE
12: P
ATTERN
TRANSMISSION
CONTROL
.......................................................................................................... 40
T
ABLE
13: L
OOP
-C
ODE
D
ETECTION
C
ONTROL
.......................................................................................................... 40
T
RANSMIT
AND
D
ETECT
Q
UASI
-R
ANDOM
S
IGNAL
S
OURCE
(TDQRSS)........................................... 41
L
OOP
-B
ACK
M
ODES
..................................................................................................................... 42
L
OCAL
A
NALOG
L
OOP
-B
ACK
(ALOOP) ......................................................................................... 42
T
ABLE
14: L
OOP
-
BACK
CONTROL
IN
H
ARDWARE
MODE
.............................................................................................. 42
T
ABLE
15: L
OOP
-
BACK
CONTROL
IN
H
OST
MODE
....................................................................................................... 42
F
IGURE
20. L
OCAL
A
NALOG
L
OOP
-
BACK
SIGNAL
FLOW
.............................................................................................. 42
R
EMOTE
L
OOP
-B
ACK
(RLOOP).................................................................................................... 43
F
IGURE
21. R
EMOTE
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
RECEIVE
PATH
.................................. 43
F
IGURE
22. R
EMOTE
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
T
RANSMIT
PATH
............................... 43
D
IGITAL
L
OOP
-B
ACK
(DLOOP)..................................................................................................... 44
D
UAL
L
OOP
-B
ACK
........................................................................................................................ 44
F
IGURE
23. D
IGITAL
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
T
RANSMIT
PATH
................................ 44
F
IGURE
24. S
IGNAL
FLOW
IN
D
UAL
LOOP
-
BACK
MODE
............................................................................................... 44
MICROPROCESSOR PARALLEL INTERFACE..............................................................45
T
ABLE
16: M
ICROPROCESSOR
INTERFACE
SIGNAL
DESCRIPTION
................................................................................ 45
M
ICROPROCESSOR
R
EGISTER
T
ABLES
.......................................................................................... 46
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
.................................................................................................. 46
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
...................................................................................... 46
M
ICROPROCESSOR
R
EGISTER
D
ESCRIPTIONS
............................................................................... 50
T
ABLE
19: M
ICROPROCESSOR
R
EGISTER
#0, B
IT
D
ESCRIPTION
................................................................................ 50
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
................................................................................ 51
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
#2, B
IT
D
ESCRIPTION
................................................................................ 53
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
#3, B
IT
D
ESCRIPTION
................................................................................ 55
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
#4, B
IT
D
ESCRIPTION
................................................................................ 57
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
#5, B
IT
D
ESCRIPTION
................................................................................ 58
T
ABLE
25: M
ICROPROCESSOR
R
EGISTER
#6, B
IT
D
ESCRIPTION
................................................................................ 60
T
ABLE
26: M
ICROPROCESSOR
R
EGISTER
#7, B
IT
D
ESCRIPTION
................................................................................ 61
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
#8, B
IT
D
ESCRIPTION
................................................................................ 62
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
#9, B
IT
D
ESCRIPTION
................................................................................ 62
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
#10, B
IT
D
ESCRIPTION
.............................................................................. 63
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
#11, B
IT
D
ESCRIPTION
.............................................................................. 63
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
#12, B
IT
D
ESCRIPTION
.............................................................................. 64
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
III
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
#13, B
IT
D
ESCRIPTION
.............................................................................. 64
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
#14, B
IT
D
ESCRIPTION
.............................................................................. 65
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
#15, B
IT
D
ESCRIPTION
.............................................................................. 65
T
ABLE
35: M
ICROPROCESSOR
R
EGISTER
#128, B
IT
D
ESCRIPTION
............................................................................ 66
CLOCK SELECT REGISTER........................................................................................... 67
F
IGURE
25. R
EGISTER
0
X
81
H
S
UB
R
EGISTERS
......................................................................................................... 67
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
#129, B
IT
D
ESCRIPTION
............................................................................ 67
T
ABLE
37: M
ICROPROCESSOR
R
EGISTER
#130, B
IT
D
ESCRIPTION
............................................................................ 69
T
ABLE
38: M
ICROPROCESSOR
R
EGISTER
#131, B
IT
D
ESCRIPTION
............................................................................ 71
T
ABLE
39: M
ICROPROCESSOR
R
EGISTER
#192, B
IT
D
ESCRIPTION
............................................................................ 72
ELECTRICAL CHARACTERISTICS................................................................................ 73
T
ABLE
40: A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................ 73
T
ABLE
41: DC D
IGITAL
I
NPUT
AND
O
UTPUT
E
LECTRICAL
C
HARACTERISTICS
.............................................................. 73
T
ABLE
42: XRT83L38 P
OWER
C
ONSUMPTION
........................................................................................................ 73
T
ABLE
43: E1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
......................................................................................... 74
T
ABLE
44: T1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
.......................................................................................... 75
T
ABLE
45: E1 T
RANSMIT
R
ETURN
L
OSS
R
EQUIREMENT
............................................................................................ 75
T
ABLE
46: E1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
.................................................................................... 76
T
ABLE
47: T1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
.................................................................................... 76
F
IGURE
26. ITU G.703 P
ULSE
T
EMPLATE
................................................................................................................ 77
T
ABLE
48: T
RANSMIT
P
ULSE
M
ASK
S
PECIFICATION
................................................................................................... 77
F
IGURE
27. DSX-1 P
ULSE
T
EMPLATE
(
NORMALIZED
AMPLITUDE
) .............................................................................. 78
T
ABLE
49: DSX1 I
NTERFACE
I
SOLATED
PULSE
MASK
AND
CORNER
POINTS
................................................................ 78
T
ABLE
50: AC E
LECTRICAL
C
HARACTERISTICS
......................................................................................................... 79
F
IGURE
28. T
RANSMIT
C
LOCK
AND
I
NPUT
D
ATA
T
IMING
............................................................................................ 79
M
ICROPROCESSOR
I
NTERFACE
I/O T
IMING
.................................................................................... 80
Intel Interface Timing - Asynchronous..................................................................................................... 80
F
IGURE
29. R
ECEIVE
C
LOCK
AND
O
UTPUT
D
ATA
T
IMING
........................................................................................... 80
F
IGURE
30. I
NTEL
A
SYNCHRONOUS
P
ROGRAMMED
I/O I
NTERFACE
T
IMING
................................................................ 80
T
ABLE
51: A
SYNCHRONOUS
M
ODE
1 - I
NTEL
8051
AND
80188 I
NTERFACE
T
IMING
.................................................... 81
Motorola Asychronous Interface Timing.................................................................................................. 82
F
IGURE
31. M
OTOROLA
68K A
SYNCHRONOUS
P
ROGRAMMED
I/O I
NTERFACE
T
IMING
................................................ 82
T
ABLE
52: A
SYNCHRONOUS
- M
OTOROLA
68K - I
NTERFACE
T
IMING
S
PECIFICATION
................................................... 82
F
IGURE
32. M
ICROPROCESSOR
I
NTERFACE
T
IMING
- R
ESET
P
ULSE
W
IDTH
............................................................... 82
P
ACKAGE
D
IMENSIONS
................................................................................................................. 83
208 L
EAD
TQFP ............................................................................................................................... 83
(28
X
28
X
1.4
MM
)............................................................................................................................. 83
225 B
ALL
P
LASTIC
B
ALL
G
RID
A
RRAY
(B
OTTOM
V
IEW
) ....................................................................... 84
(19.0
X
19.0
X
1.0
MM
)...................................................................................................................... 84
ORDERING INFORMATION ...................................................................................................... 85
REVISIONS................................................................................................................................ 85
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
5
PIN DESCRIPTION BY FUNCTION
RECEIVE SECTIONS
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
RLOS_0
RLOS_1
RLOS_2
RLOS_3
RLOS_4
RLOS_5
RLOS_6
RLOS_7
206
22
135
159
55
31
126
102
C3
H4
H15
A16
V3
L2
J15
T15
O
Receiver Loss of Signal for Channel_ 0:
This output signal goes "High" for at least one RCLK_0 cycle to indicate loss
of signal at the receive 0 input. RLOS will remain "High" for the entire dura-
tion of the Loss of Signal detected by the receiver logic.
See "Receiver Loss of Signal (RLOS)" on page 24.
Receiver Loss of Signal for Channel _1
Receiver Loss of Signal for Channel _2
Receiver Loss of Signal for Channel _3
Receiver Loss of Signal for Channel _4
Receiver Loss of Signal for Channel_ 5
Receiver Loss of Signal for Channel _6
Receiver Loss of Signal for Channel _7
RCLK_0
RCLK_1
RCLK_2
RCLK_3
RCLK_4
RCLK_5
RCLK_6
RCLK_7
207
21
136
158
54
32
125
103
B3
H3
H16
A17
U3
L3
M15
U16
O
Receiver Clock Output for Channel _0
Receiver Clock Output for Channel _1
Receiver Clock Output for Channel _2
Receiver Clock Output for Channel _3
Receiver Clock Output for Channel _4
Receiver Clock Output for Channel _5
Receiver Clock Output for Channel _6
Receiver Clock Output for Channel _7
RNEG_0
LCV_0
RNEG_1
LCV_1
RNEG_2
LCV_2
RNEG_3
LCV_3
RNEG_4
LCV_4
RNEG_5
LCV_5
RNEG_6
LCV_6
RNEG_7
LCV_7
208
208
20
137
157
53
33
124
104
A2
A2
H2
H18
B16
T4
M4
M16
V17
O
Receiver Negative Data Output for Channel_0 - Dual-Rail mode
This signal is the receive negative-rail output data.
Line Code Violation Output for Channel_0 - Single-Rail mode
This signal goes "High" for one RCLK_0 cycle to indicate a code violation is
detected in the received data of Channel _0. If AMI coding is selected, every
bipolar violation received will cause this pin to go "High".
Receiver Negative Data Output for Channel _1
Line Code Violation Output for Channel _1
Receiver Negative Data Output for Channel _2
Line Code Violation Output for Channel _2
Receiver Negative Data Output for Channel _3
Line Code Violation Output for Channel _3
Receiver Negative Data Output for Channel _4
Line Code Violation Output for Channel _4
Receiver Negative Data Output for Channel _5
Line Code Violation Output for Channel _5
Receiver Negative Data Output for Channel _6
Line Code Violation Output for Channel _6
Receiver Negative Data Output for Channel _7
Line Code Violation Output for Channel _7
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
6
RPOS_0
RDATA_0
RPOS_1
RDATA_1
RPOS_2
RDATA_2
RPOS_3
RDATA_3
RPOS_4
RDATA_4
RPOS_5
RDATA_5
RPOS_6
RDATA_6
RPOS_7
RDATA_7
1
1
19
138
156
52
34
123
105
B2
B2
G2
D15
B17
U2
M3
L17
T17
O
Receiver Positive Data Output for Channel _0 - Dual-Rail mode
This signal is the receive positive-rail output data sent to the Framer.
Receiver NRZ Data Output for Channel _0 - Single-Rail mode
This signal is the receive output data.
Receiver Positive Data Output for Channel _1
Receiver NRZ Data Output for Channel _1
Receiver Positive Data Output for Channel _2
Receiver NRZ Data Output for Channel _2
Receiver Positive Data Output for Channel _3
Receiver NRZ Data Output for Channel _3
Receiver Positive Data Output for Channel _4
Receiver NRZ Data Output for Channel _4
Receiver Positive Data Output for Channel _5
Receiver NRZ Data Output for Channel _5
Receiver Positive Data Output for Channel _6
Receiver NRZ Data Output for Channel 6
Receiver Positive Data Output for Channel _7
Receiver NRZ Data Output for Channel _7
RTIP_0
RTIP_1
RTIP_2
RTIP_3
RTIP_4
RTIP_5
RTIP_6
RTIP_7
3
17
140
154
50
36
121
107
C1
G1
G18
C18
U1
L1
L18
T18
I
Receiver Differential Tip Input for Channel _0
Positive differential receive input from the line
Receiver Differential Tip Input for Channel _1
Receiver Differential Tip Input for Channel _2
Receiver Differential Tip Input for Channel _3
Receiver Differential Tip Input for Channel _4
Receiver Differential Tip Input for Channel _5
Receiver Differential Tip Input for Channel _6
Receiver Differential Tip Input for Channel _7
RRING_0
RRING_1
RRING_2
RRING_3
RRING_4
RRING_5
RRING_6
RRING_7
4
16
141
153
49
37
120
108
D1
F1
F18
D18
T1
M1
M18
R18
I
Receiver Differential Ring Input for Channel _0
Negative differential receive input from the line
Receiver Differential Ring Input for Channel _1
Receiver Differential Ring Input for Channel _2
Receiver Differential Ring Input for Channel _3
Receiver Differential Ring Input for Channel _4
Receiver Differential Ring Input for Channel _5
Receiver Differential Ring Input for Channel _6
Receiver Differential Ring Input for Channel _7
RXMUTE
89
T12
I
Receive Data Muting
When a LOS condition occurs, the outputs RPOS_n/RNEG_n will be muted,
(forced to ground) to prevent data chattering.
Tie this pin "Low" to disable the muting function.
N
OTES
:
1.
This pin is internally pulled "High" with a 50k
resistor.
2.
In Hardware mode, all receive channels share the same RXMUTE
control function.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
7
TRANSMITTER SECTIONS
RXRES1
RXRES0
81
82
R10
V10
I
Receive External Resistor Control Pins - Hardware mode
Receive External Resistor Control Pin 1:
Receive External Resistor Control Pin 0:
These pins determine the value of the external Receive fixed resistor
according to the following table:
N
OTE
: These pins are internally pulled "Low" with a 50k
resistor.
RCLKE
µPTS1
133
133
J16
J16
I
Receive Clock Edge - Hardware mode
Set this pin "High" to sample RPOS_N/RNEG_n on the falling edge of
RCLK_n. With this pin tied "Low", output data are updated on the rising edge
of RCLK_n.
Microprocessor Type Select Input pin 1 - Host mode
This pin along with µPTS2 (pin 128) is used to select the microprocessor
type.
See "Microprocessor Type Select Input Pins - Host Mode:" on page 12.
N
OTE
: This pin is internally pulled "Low" with a 50k
resistor.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
TCLKE
µPTS2
128
128
L15
L15
I
Transmit Clock Edge - Hardware mode
Set this pin "High" to sample transmit input data on the rising edge of
TCLK_n. With this pin tied "Low", input data are sampled on the falling
edge of TCLK_n.
Microprocessor Type Select Input pin 2 - Host mode
This pin along with µPTS1 (pin 133) selects the microprocessor type.
See
"Microprocessor Type Select Input Pins - Host Mode:" on page 12.
N
OTE
: This pin is internally pulled "Low" with a 50k
resistor.
TTIP_0
TTIP_1
TTIP_2
TTIP_3
TTIP_4
TTIP_5
TTIP_6
TTIP_7
7
13
144
150
46
40
117
111
E3
G4
F17
C16
R2
N2
N16
P16
O
Transmitter Tip Output for Channel _0
Positive differential transmit output to the line.
Transmitter Tip Output for Channel _1
Transmitter Tip Output for Channel _2
Transmitter Tip Output for Channel _3
Transmitter Tip Output for Channel _4
Transmitter Tip Output for Channel _5
Transmitter Tip Output for Channel _6
Transmitter Tip Output for Channel _7
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
RXRES 1
0
0
Required Fixed External
RX Resistor
No External Fixed R esistor
240
RXRES0
0
1
1
1
210
150
0
1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
8
TRING_0
TRING_1
TRING_2
TRING_3
TRING_4
TRING_5
TRING_6
TRING_7
9
11
146
148
44
42
115
113
E2
F3
F15
E16
P2
N4
R15
P17
O
Transmitter Ring Output for Channel _0
Negative differential transmit output to the line.
Transmitter Ring Output for Channel _1
Transmitter Ring Output for Channel _2
Transmitter Ring Output for Channel _3
Transmitter Ring Output for Channel _4
Transmitter Ring Output for Channel _5
Transmitter Ring Output for Channel _6
Transmitter Ring Output for Channel _7
TPOS_0
TDATA_0
TPOS_1
TDATA_1
TPOS_2
TDATA_2
TPOS_3
TDATA_3
TPOS_4
TDATA_4
TPOS_5
TDATA_5
TPOS_6
TDATA_6
TPOS_7
TDATA_7
204
201
164
161
57
60
97
100
C5
A4
B14
D14
V4
U5
V15
T14
I
Transmitter Positive Data Input for Channel _0 - Dual-Rail mode
This signal is the positive-rail input data for transmitter 0.
Transmitter 0 Data Input - Single-Rail mode
This pin is used as the NRZ input data for transmitter 0.
Transmitter Positive Data Input for Channel _1
Transmitter 1 Data Input
Transmitter Positive Data Input for Channel _2
Transmitter 2 Data Input
Transmitter Positive Data Input for Channel _3
Transmitter 3 Data Input
Transmitter Positive Data Input for Channel _4
Transmitter 4 Data Input
Transmitter Positive Data Input for Channel _5
Transmitter 5 Data Input
Transmitter Positive Data Input for Channel _6
Transmitter 6 Data Input
Transmitter Positive Data Input for Channel _7
Transmitter 7 Data Input
N
OTE
: Internally pulled "Low" with a 50k
resistor for each channel.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
9
TNEG_0
CODES_0
TNEG_1
CODES_1
TNEG_2
CODES_2
TNEG_3
CODES_3
TNEG_4
CODES_4
TNEG_5
CODES_5
TNEG_6
CODES_6
TNEG_7
CODES_7
205
205
200
165
160
56
61
96
101
C4
C4
B5
D13
B15
U4
V5
U14
R14
I
Transmitter Negative NRZ Data Input for Channel _0
Dual-Rail mode
This signal is the negative-rail input data for transmitter 0.
Single-Rail mode
This pin can be left unconnected.
Coding Select for Channel _0 - Hardware mode and Single-Rail mode
Connecting this pin "Low" enables HDB3 in E1 or B8ZS in T1 encoding and
decoding for Channel _0. Connecting this pin "High" selects AMI data for-
mat.
Transmitter Negative NRZ Data Input for Channel _1
Coding Select for Channel _1
Transmitter Negative NRZ Data Input for Channel _2
Coding Select for Channel _2
Transmitter Negative NRZ Data Input for Channel _3
Coding Select for Channel _3
Transmitter Negative NRZ Data Input for Channel _4
Coding Select for Channel _4
Transmitter Negative NRZ Data Input for Channel _5
Coding Select for Channel _5
Transmitter Negative NRZ Data Input for Channel _6
Coding Select for Channel _6
Transmitter Negative NRZ Data Input for Channel _7
Coding Select for Channel _7
N
OTE
: Internally pulled "Low" with a 50k
resistor for each channel.
TCLK_0
TCLK_1
TCLK_2
TCLK_3
TCLK_4
TCLK_5
TCLK_6
TCLK_7
203
202
163
162
58
59
98
99
B4
A3
A15
C14
T3
T5
V16
U15
I
Transmitter Clock Input for Channel _0 - Host mode and Hardware
mode
E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm.
During normal operation TCLK_0 is used for sampling input data at
TPOS_0/TDATA_0 and TNEG_0/CODES_0 while MCLK is used as the
timing reference for the transmit pulse shaping circuit.
Transmitter Clock Input for Channel _1
Transmitter Clock Input for Channel _2
Transmitter Clock Input for Channel _3
Transmitter Clock Input for Channel _4
Transmitter Clock Input for Channel _5
Transmitter Clock Input for Channel _6
Transmitter Clock Input for Channel _7
N
OTE
: Internally pulled "Low" with a 50k
resistor for all channels.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
10
TAOS_0
TAOS_1
TAOS_2
TAOS_3
TAOS_4
TAOS_5
TAOS_6
TAOS_7
195
196
197
198
63
64
65
66
D6
B6
A5
C6
T6
U6
V6
R6
I
Transmit All Ones for Channel _0 - Hardware mode
Setting this pin "High" enables the transmission of an "All Ones" Pattern
from Channel _0. A "Low" level stops the transmission of the "All Ones"
Pattern.
Transmit All Ones for Channel _1
Transmit All Ones for Channel _2
Transmit All Ones for Channel _3
Transmit All Ones for Channel _4
Transmit All Ones for Channel _5
Transmit All Ones for Channel _6
Transmit All Ones for Channel _7
N
OTE
: Internally pulled "Low" with a 50k
resistor for all channels.
TXON_0
TXON_1
TXON_2
TXON_3
TXON_4
TXON_5
TXON_6
TXON_7
169
170
171
172
90
91
92
93
A13
D12
C12
B12
V13
U13
R12
R13
I
Transmitter Turn On for Channel _0
Hardware mode
Setting this pin "High" turns on the Transmit and Receive Sections of Chan-
nel _0. When TXON_0 = "0" then TTIP_0 and TRING_0 driver outputs will
be tri-stated.
In Host mode
The TXON_n bits in the channel control registers turn each channel Trans-
mit and Receive section ON or OFF. However, control of the on/off function
can be transferred to the Hardware pins by setting the TXONCNTL bit (bit
7) to "1" in the register at address hex 0x82.
Transmitter Turn On for Channel _1
Transmitter Turn On for Channel _2
Transmitter Turn On for Channel _3
Transmitter Turn On for Channel _4
Transmitter Turn On for Channel _5
Transmitter Turn On for Channel _6
Transmitter Turn On for Channel _7
N
OTE
: Internally pulled "Low" with a 50k
resistor for all channels.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
11
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
HW_HOST
80
T10
I
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie
"High" to select Hardware mode.
For Host mode, this pin must be tied "Low".
N
OTE
: Internally pulled "High" with a 50k
resistor.
WR_R/W
EQC0
190
190
D7
D7
I
Write Input (Read/Write) - Host mode:
Intel bus timing: A "Low" pulse on WR selects a write operation when CS pin
is "Low".
Motorola bus timing: A "High" pulse on R/W selects a read operation and a
"Low" pulse on R/W selects a write operation when CS is "Low".
Equalizer Control Input pin 0 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
See "Receive Equalizer Control and Transmit Line
Build-Out Settings" on page 30.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
RD_DS
EQC1
191
191
C7
C7
I
Read Input (Data Strobe) - Host mode
Intel bus timing: A "Low" pulse on RD selects a read operation when the CS
pin is "Low".
Motorola bus timing: A "Low" pulse on DS indicates a read or write operation
when the CS pin is "Low".
Equalizer Control Input pin 1 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
See "Receive Equalizer Control and Transmit Line
Build-Out Settings" on page 30.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
ALE_AS
EQC2
192
192
A7
A7
I
Address Latch Input (Address Strobe) - Host mode
Intel bus timing: The address inputs are latched into the internal register on
the falling edge of ALE.
Motorola bus timing: The address inputs are latched into the internal register
on the falling edge of AS.
Equalizer Control Input pin 2 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
See "Receive Equalizer Control and Transmit Line
Build-Out Settings" on page 30.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
CS
EQC3
193
193
B7
B7
I
Chip Select Input - Host mode:
This signal must be "Low" in order to access the parallel port.
Equalizer Control Input pin 3 - Hardware mode:
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
See "Receive Equalizer Control and Transmit Line
Build-Out Settings" on page 30.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
12
RDY_DTACK
EQC4
194
194
A6
A6
O
I
Ready Output (Data Transfer Acknowledge Output) - Host mode
Intel bus timing: RDY is asserted "High" to indicate the device has completed
a read or write operation.
Motorola bus timing: DTACK is asserted "Low" to indicate the device has
completed a read or write cycle.
Equalizer Control Input pin 4 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
See "Receive Equalizer Control and Transmit Line
Build-Out Settings" on page 30.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
µPTS1
µPTS2
RCLKE
TCLKE
133
128
133
128
J16
L15
J16
L15
I
Microprocessor Type Select Input Pins - Host Mode:
Microprocessor Type Select Input Bit 1
Microprocessor Type Select Input Bit 2
Receive Clock Edge - Hardware mode
See "Receive Clock Edge - Hardware mode" on page 7.
Transmit Clock Edge - Hardware mode
See "Transmit Clock Edge - Hardware mode" on page 7.
N
OTE
: These pins are internally pulled "Low" with a 50k
resistor.
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
T7
U7
V7
V8
V9
U8
U9
R7
T7
U7
V7
V8
V9
U8
U9
R7
I/O
Microprocessor Read/Write Data Bus Pins - Host mode
Data Bus[7]
Data Bus[6]
Data Bus[5]
Data Bus[4]
Data Bus[3]
Data Bus[2]
Data Bus[1]
Data Bus[0]
Loop-back Control Pins, Bits [1:0] Channel_[7:4] - Hardware Mode
Pins 67-74 and 173-180 control which Loop-Back mode is selected per chan-
nel.
See "Loop-back Control Pins, Bits [1:0] Channel_[7:0]" on page 17.
N
OTE
: Internally pulled "Low" with a 50k
resistor for all channels.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
µ
P T S 2
µ
P T S 1
0
0
0
1
1
0
µ
P T yp e
68H C11, 8051, 80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Motorola 860 (sync.)
1
1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
13
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
LOOP1_3
LOOP0_3
LOOP1_2
LOOP0_2
LOOP1_1
LOOP0_1
LOOP1_0
LOOP0_0
173
174
175
176
177
178
179
180
173
174
175
176
177
178
179
180
A12
B11
C11
D11
A11
B10
A10
C10
A12
B11
C11
D11
A11
B10
A10
C10
I
Microprocessor Interface Address Bus Pins - Host mode:
Microprocessor Interface Address Bus[7]
Microprocessor Interface Address Bus[6]
Microprocessor Interface Address Bus[5]
Microprocessor Interface Address Bus[4]
Microprocessor Interface Address Bus[3]
Microprocessor Interface Address Bus[2]
Microprocessor Interface Address Bus[1]
Microprocessor Interface Address Bus[0]
Loop-back Control Pins, Bits [1:0] Channel_[3:0]
In Hardware mode, pins 67-74 and 173-180 control which Loop-Back mode is
selected per channel.
See "Loop-back Control Pins, Bits [1:0] Channel_[7:0]" on
page 17.
N
OTE
: These pins are internally pulled "Low" with a 50k
resistor.
µPCLK
ATAOS
94
94
T13
T13
I
Microprocessor Clock Input - Host Mode:
Input clock for synchronous microprocessor operation. Maximum clock rate is
54 MHz.
N
OTE
: This pin is internally pulled "Low" with a 50k
resistor for asynchronous
microprocessor interface when no clock is present.
Automatic Transmit "All Ones" - Hardware mode
This pin functions as an Automatic Transmit "All Ones".
See "Automatic Trans-
mit "All Ones" Pattern - Hardware Mode" on page 16.
INT
TRATIO
127
127
L16
L16
O
I
Interrupt Output - Host mode
This pin goes "Low" to indicate an alarm condition has occurred within the
device. Interrupt generation can be globally disabled by setting the GIE bit to a
"0" in the command control register.
Transmitter Transformer Ratio Select - Hardware mode
The function of this pin is to select the transmitter transformer ratio.
See "Trans-
mitter Transformer Ratio Select - Hardware mode" on page 16.
N
OTE
: This pin is an open drain output and requires an external 10k
pull-up
resistor.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
14
JITTER ATTENUATOR
CLOCK SYNTHESIZER
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
JASEL0
JASEL1
167
168
A14
B13
I
Jitter Attenuator Select Pins Hardware Mode
Jitter Attenuator select Bit 0
Jitter Attenuator select Bit 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the
receive path or to disable it.
N
OTE
: These pins are internally pulled "Low" with 50k
resistors.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
MCLKOUT
23
H1
O
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1 or
E1 rate based upon the mode of operation.
MCLKT1
27
K1
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy
better than ±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the
T1 mode.
N
OTES
:
1.
All channels of the XRT83L38 must be operated at the same clock
rate, either T1, E1 or J1.
2.
See pin 26 description for further explanation for the usage of this pin.
3.
Internally pulled "Low" with a 50k
resistor.
MCLKE1
26
J1
I
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle
of 40% to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that
clock should be connected to both MCLKE1 and MCLKT1 inputs for proper
operation.
N
OTES
:
1.
All channels of the XRT83L38 must be operated at the same clock
rate, either T1, E1 or J1.
2.
Internally pulled "Low" with a 50k
resistor.
Disabled
Transmit
Receive
Receive
JA Path
JA BW Hz
--------
32/32
32/32
64/64
FIFO Size
-----
3
3
3
-----
10
10
1.5
0
0
1
1
JASEL1
0
1
0
1
JASEL0
T1
E1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
15
CLKSEL0
CLKSEL1
CLKSEL2
187
188
189
A8
B8
C8
I
Clock Select inputs for Master Clock Synthesizer - Hardware mode
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that
can be used to generate a master clock from an external accurate clock source
according to the table below.
In Hardware mode, the MCLKRATE control signal is generated from the state
of EQC[4:0] inputs.
In Host mode, the state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits. See
Table 36
register
address 10000001
N
OTE
: These pins are internally pulled "Low" with a 50k
resistor.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
2 0 4 8
2 0 4 8
2 0 4 8
1 5 4 4
M C LKE1
kHz
8
1 6
1 6
5 6
8
5 6
6 4
6 4
1 2 8
2 5 6
2 5 6
1 2 8
2 0 4 8
2 0 4 8
1 5 4 4
1 5 4 4
M C LKT1
kH z
1 5 4 4
X
X
X
1 5 4 4
X
X
X
X
X
X
X
2 0 4 8
1 5 4 4
2 0 4 8
C LKO UT/
kHz
1 5 4 4
2 0 4 8
1 5 4 4
2 0 4 8
1 5 4 4
2 0 4 8
1 5 4 4
2 0 4 8
1 5 4 4
2 0 4 8
1 5 4 4
2 0 4 8
1 5 4 4
0
0
1
1
CLKSE L0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
CLKSE L1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
C LKSE L2
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
1 5 4 4
2 0 4 8
X
X
2 0 4 8
1 5 4 4
0
1
0
1
M CLK RATE
1
0
1
0
0
1
0
1
1
0
1
0
0
1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
16
ALARM FUNCTIONS/REDUNDANCY SUPPORT
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
GAUGE
134
J18
I
Twisted Pair Cable Wire Gauge Select - Hardware Mode
Connect this pin "High" to select 26 Gauge wire. Connect this pin "Low" to
select 22 and 24 gauge wire for all channels.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
DMO_0
DMO_1
DMO_2
DMO_3
DMO_4
DMO_5
DMO_6
DMO_7
199
10
147
166
62
43
114
95
D5
D4
C15
C13
R5
P4
U17
V14
O
Driver Failure Monitor Channel _0:
This pin transitions "High" if a short circuit condition is detected in the transmit
driver of Channel _0, or no transmit output pulse is detected for more than 128
TCLK_0 cycles.
Driver Failure Monitor Channel _1
Driver Failure Monitor Channel _2
Driver Failure Monitor Channel _3
Driver Failure Monitor Channel _4
Driver Failure Monitor Channel _5
Driver Failure Monitor Channel _6
Driver Failure Monitor Channel _7
ATAOS
µPCLK
94
94
T13
T13
I
Automatic Transmit "All Ones" Pattern - Hardware Mode
A "High" level on this pin enables the automatic transmission of an "All Ones"
AMI pattern from the transmitter of any channel that the receiver of that chan-
nel has detected an LOS condition. A "Low" level on this pin disables this func-
tion.
Note: All channels share the same ATAOS control function.
Microprocessor Clock Input - Host mode
See "Microprocessor Clock Input - Host Mode:" on page 13.
N
OTE
: This pin is internally pulled "Low" for asynchronous microprocessor
interface when no clock is present.
TRATIO
INT
127
127
L16
L16
I
O
Transmitter Transformer Ratio Select - Hardware mode
In external termination mode (TXTSEL = 0), setting this pin "High" selects a
transformer ratio of 1:2 for the transmitter. A "Low" on this pin sets the trans-
mitter transformer ratio to 1:2.45. In the internal termination mode the trans-
mitter transformer ratio is permanently set to 1:2 and the state of this pin is
ignored.
Interrupt Output - Host mode
This pin is asserted "Low" to indicate an alarm condition.
See "Interrupt Output
- Host mode" on page 13.
N
OTE
: This pin is an open drain output and requires an external 10k
pull-up
resistor.
RESET
75
T8
I
Hardware Reset (Active "Low"):
When this pin is tied "Low" for more than 10µs, the device is put in the reset
state.
N
OTE
: This pin is internally pulled "High" with a 50k
resistor.
SR/DR
30
K4
I
Single-Rail/Dual-Rail Data Format:
Connect this pin "Low" to select transmit and receive data format in Dual-Rail
mode. In this mode, HDB3 or B8ZS encoder and decoder are not available.
Connect this pin "High" to select single-rail data format.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
17
LOOP1_0
LOOP0_0
LOOP1_1
LOOP0_1
LOOP1_2
LOOP0_2
LOOP1_3
LOOP0_3
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
A[1]
A[0]
A[3]
A[2]
A[5]
A[4]
A[7]
A[6]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
179
180
177
178
175
176
173
174
67
68
69
70
71
72
73
74
179
180
177
178
175
176
173
174
67
68
69
70
71
72
73
74
A10
C10
A11
B10
C11
D11
A12
B11
T7
U7
V7
V8
V9
U8
U9
R7
A10
C10
A11
B10
C11
D11
A12
B11
T7
U7
V7
V8
V9
U8
U9
R7
I
Loop-back Control Pins, Bits [1:0] Channel_[7:0]
Loop-back Control bit 1, Channel _0
Loop-back Control bit 0, Channel _0
Loop-back Control bit 1, Channel _1
Loop-back Control bit 0, Channel _1
Loop-back Control bit 1, Channel _2
Loop-back Control bit 0, Channel _2
Loop-back Control bit 1, Channel _3
Loop-back Control bit 0, Channel _3
Loop-back Control bit 1, Channel _4
Loop-back Control bit 0, Channel _4
Loop-back Control bit 1, Channel _5
Loop-back Control bit 0, Channel _5
Loop-back Control bit 1, Channel _6
Loop-back Control bit 0, Channel _6
Loop-back Control bit 1, Channel _7
Loop-back Control bit 0, Channel _7
In Hardware mode, these pins control the Loop-Back mode for each
channel_n per the following table.
Microprocessor Address A[7:0] and Data Bus Pins D[7:0] - Host mode
These pins are microprocessor address and data bus pins.
See "Microproces-
sor Interface Address Bus Pins - Host mode:" on page 13.
and
see "Micropro-
cessor Read/Write Data Bus Pins - Host mode" on page 12.
N
OTE
: These pins are internally pulled "Low" with a 50k
resistor.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
LOOP1_n
LOOP0_n
0
0
0
1
1
0
1
1
MODE
Normal Mode No Loop-Back Channel_n
Local Loop-Back Channel_n
Remote Loop-Back Channel_n
Digital Loop-Back Channel_n
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
18
EQC4
EQC3
EQC2
EQC1
EQC0
RDY_DTACK
CS
ALE_AS
RD_DS
WR_R/W
194
193
192
191
190
194
193
192
191
190
A6
B7
A7
C7
D7
A6
B7
A7
C7
D7
I
O
I
I
I
I
Equalizer Control Input 4 - Hardware mode
This pin together with pins EQC[3:0] is used to control the transmit pulse
shaping, transmit line build-out (LBO) and receive monitoring while operating
at one of either the T1, E1 or J1 clock rates/modes.
See "Receive Equalizer
Control and Transmit Line Build-Out Settings" on page 30.
for description of
Transmit Equalizer Control bits.
Equalizer Control Input 3
Equalizer Control Input 2
Equalizer Control Input 1
Equalizer Control Input 0
N
OTES
:
1.
In Hardware mode all transmit channels share the same pulse
setting controls function.
2.
All channels of an XRT83L38 must operate at the same clock rate,
either the T1, E1 or J1 modes.
In Host mode, these pins perform various microprocessor functions.
See
"Microprocessor Interface" on page 11.
N
OTE
: Internally pulled "Low" with a 50k
resistor.
RXTSEL
83
U11
I
Receiver Termination Select
In Hardware mode, when this pin is "Low" the receive line termination is
determined only by an external resistor. When "High", the receive termination
is realized by the internal resistor or the combination of internal and external
resistors. These conditions are described in the table below.
N
OTE
: In Hardware mode all channels share the same RXTSEL control
function.
In Host mode, the RXTSEL_n bits in the channel control registers determine
if the receiver termination is external or internal. However, the function of RXT-
SEL can be transferred to the Hardware pin by setting the TERCNTL bit (bit
6) to "1" in the register address hex 0x82.
N
OTE
: This pin is internally pulled "Low" with a 50k
resistor.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
RXTSEL
RX Termination
0
1
External
Internal
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
19
TXTSEL
84
V11
I
Transmit Termination Select - Hardware Mode
When this pin is "Low" the transmit line termination is determined only by an
external resistor. When "High", the transmit termination is realized only by the
internal resistor.
N
OTES
:
1.
This pin is internally pulled "Low" with a 50k
resistor.
2.
In Hardware mode all channels share the same TXTSEL control
function.
TERSEL1
TERSEL0
85
86
T11
R11
I
Termination Impedance Select bit 1:
Termination Impedance Select bit 0:
In the Hardware mode and in the internal termination mode (TXTSEL="1"
and RXTSEL="1") TERSEL[1:0] control the transmit and receive termination
impedance according to the following table.
In the internal termination mode the receiver termination of each receiver is
realized completely by internal resistors or by the combination of internal and
one fixed external resistor (see description of RXRES[1:0] pins).
In the internal termination mode the transformer ratio of 1:2 or 1:2.45 and
1:1 is required for transmitter and receiver respectively with the transmitter
output AC coupled to the transformer.
N
OTES
:
1.
This pin is internally pulled "Low" with a 50k
resistor.
2.
In Hardware mode, all channels share the same TERSEL control
function.
3.
In the external termination mode a 1:2 or 1:2.45 transformer ratio
must be used for the transmitter.
TEST
87
U12
I
Manufacturing Test:
N
OTE
: For normal operation this pin must be tied to ground.
ICT
88
V12
I
In-Circuit Testing (Active "Low"):
When this pin is tied "Low", all output pins are forced to a high impedance
state for in-circuit testing.
Pulling RESET and ICT pins "Low" simultaneously will put the chip in factory
test mode. This condition should not be permitted during normal operation.
N
OTE
: This pin is internally pulled "High" with a 50k
resistor.
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
TXTSEL
TX Termination
0
1
External
Internal
0
1
1
0
1
1
0
0
100
110
75
120
Termination
TERSEL1
TERSEL0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
20
POWER AND GROUND
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
TGND_0
TGND_1
TGND_2
TGND_3
TGND_4
TGND_5
TGND_6
TGND_7
6
14
143
151
47
39
118
110
D3
F2
E15
C17
R3
P3
T16
R16
****
Transmitter Analog Ground for Channel _0
Transmitter Analog Ground for Channel _1
Transmitter Analog Ground for Channel _2
Transmitter Analog Ground for Channel _3
Transmitter Analog Ground for Channel _4
Transmitter Analog Ground for Channel _5
Transmitter Analog Ground for Channel _6
Transmitter Analog Ground for Channel _7
TVDD_0
TVDD_1
TVDD_2
TVDD_3
TVDD_4
TVDD_5
TVDD_6
TVDD_7
8
12
145
149
45
41
116
112
E4
F4
F16
E17
R4
P1
N15
P15
****
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _0
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _1
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _2
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _3
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _4
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _5
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _6
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _7
RVDD_0
RVDD_1
RVDD_2
RVDD_3
RVDD_4
RVDD_5
RVDD_6
RVDD_7
2
18
139
155
51
35
122
106
C2
E5
G16
D16
V2
N3
N17
U18
****
Receiver Analog Positive Supply (3.3V± 5%) for Channel _0
Receiver Analog Positive Supply (3.3V± 5%) for Channel _1
Receiver Analog Positive Supply (3.3V± 5%) for Channel _2
Receiver Analog Positive Supply (3.3V± 5%) for Channel _3
Receiver Analog Positive Supply (3.3V± 5%) for Channel _4
Receiver Analog Positive Supply (3.3V± 5%) for Channel _5
Receiver Analog Positive Supply (3.3V± 5%) for Channel _6
Receiver Analog Positive Supply (3.3V± 5%) for Channel _7
RGND_0
RGND_1
RGND_2
RGND_3
RGND_4
RGND_5
RGND_6
RGND_7
5
15
142
152
48
38
119
109
D2
G3
G17
D17
T2
M2
M17
R17
****
Receiver Analog Ground for Channel_0
Receiver Analog Ground for Channel_1
Receiver Analog Ground for Channel_2
Receiver Analog Ground for Channel_3
Receiver Analog Ground for Channel_4
Receiver Analog Ground for Channel_5
Receiver Analog Ground for Channel_6
Receiver Analog Ground for Channel_7
AVDD Bias
VDDPLL_1
VDDPLL_2
129
24
25
K17
J3
J2
****
Analog Positive Supply (3.3V± 5%)
Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)
Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)
AGND Bias
GNDPLL_1
GNDPLL_2
132
28
29
J17
K3
L4
****
Analog Ground
Analog Ground for Master Clock Synthesizer PLL
Analog Ground for Master Clock Synthesizer PLL
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
21
PINS ONLY AVAILABLE IN BGA PACKAGE
DVDD_DRV
DVDD_PRE
DVDD
µ
P
DVDD_PRE
DVDD_DRV
DVDD
78
79
130
181
182
183
R9
U10
K18
D10
K15
A9
****
Digital Positive Supply (3.3V± 5%)
Digital Positive Supply (3.3V± 5%)
Digital Positive Supply (3.3V± 5%)
Digital Positive Supply (3.3V± 5%)
Digital Positive Supply (3.3V± 5%)
Digital Positive Supply (3.3V± 5%)
DGND_PRE
DGND_DRV
DGND µP
DGND
DGND_DRV
DGND_PRE
76
77
131
184
185
186
R8
T9
H17
B9
D8
C9
****
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
DVDD_DRV
DVDD_DRV
N/A
J4
D9
****
Digital Positive Supply (3.3V± 5%)
Digital Positive Supply (3.3V± 5%)
DGND_DRV
DGND_DRV
N/A
G15
K2
****
Digital Ground
Digital Ground
RXON
N/A
K16
I
Receiver On - Harware Mode
Writing a "1" to this pin in Hardware mode turns on the Receive Sections
of all channels. Writing a "0" shuts off the Receiver Sections of all chan-
nels.
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
N/A
A1
V1
V18
A18
B1
E1
N1
R1
P18
N18
E18
B18
****
No Connect Pins
S
IGNAL
N
AME
TQFP
P
IN
#
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
22
FUNCTIONAL DESCRIPTION
The XRT83L38 is a fully integrated long-haul and short-haul transceiver intended for T1, J1 or E1 systems.
Simplified block diagrams of the chip are shown in
Figure 1
, Host mode and
Figure 2
, Hardware mode. The
XRT83L38 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet cable loss)
for T1 and from 0 to 43dB at 1024kHz for E1 systems.
In T1 applications, the XRT83L38 can generate five transmit pulse shapes to meet the short-haul Digital Cross-
connect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB
and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generators for
each channel that can be used for output pulse shaping allowing performance improvement over a wide variety
of conditions (The arbitrary pulse generators are available in both T1 and E1). The operation and configuration
of the XRT83L38 can be controlled through a parallel microprocessor Host interface or Hardware control.
MASTER CLOCK GENERATOR
Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or
E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.
There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are
available these clocks can be connected to the respective pins. All channels of a given XRT83l38 must be
operated at the same clock rate, either T1, E1 or J1 modes.
In systems that have only one master clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz,
16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according
to
Table 1
.
N
OTE
: EQC[4:0] determine the T1/E1 operating mode. See
Table 5
for details.
F
IGURE
4. T
WO
I
NPUT
C
LOCK
S
OURCE
F
IGURE
5. O
NE
I
NPUT
C
LOCK
S
OURCE
MCLKE1
MCLKT1
MCLKOUT
1.544MHz
or
2.048MHz
2.048MHz
+/-50ppm
1.544MHz
+/-50ppm
Two Input C lock Sources
MCLKE1
MCLKT1
MCLK OUT
1.544MHz
or
2.048MHz
One Input Clock Source
Input Clock Options
8kHz
16kHz
56kHz
64kHz
128kHz
256kHz
1.544MHz
2.048MHz
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
23
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
T
ABLE
1: M
ASTER
C
LOCK
G
ENERATOR
MCLKE1
K
H
Z
MCLKT1
K
H
Z
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
M
ASTER
C
LOCK
K
H
Z
2048
2048
0
0
0
0
2048
2048
2048
0
0
0
1
1544
2048
1544
0
0
0
0
2048
1544
1544
0
0
1
1
1544
1544
1544
0
0
1
0
2048
2048
1544
0
0
1
1
1544
8
x
0
1
0
0
2048
8
x
0
1
0
1
1544
16
x
0
1
1
0
2048
16
x
0
1
1
1
1544
56
x
1
0
0
0
2048
56
x
1
0
0
1
1544
64
x
1
0
1
0
2048
64
x
1
0
1
1
1544
128
x
1
1
0
0
2048
128
x
1
1
0
1
1544
256
x
1
1
1
0
2048
256
x
1
1
1
1
1544
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
24
RECEIVE MONITOR MODE
In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles
input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1
applications, refer to
Table 5
for details. This feature is available in both Hardware and Host modes.
RECEIVER LOSS OF SIGNAL (RLOS)
For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both
analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to
count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = "1") or 175 consecutive zeros
in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above
the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more
than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in
hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more
than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and
register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt
causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically
reset upon read (RUR), and the INT pin will return high.
Analog RLOS
Setting the Receiver Inputs to -15dB T1/E1 Short Haul Mode
By setting the receiver inputs to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal.
N
OTE
: This is the only setting that refers to cable loss (frequency), not flat loss (resistive).
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See
Figure 6
for a simplified
diagram.
Setting the Receiver Inputs to -29dB T1/E1 Gain Mode
By setting the receiver inputs to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and
make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal.
N
OTE
: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency).
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
F
IGURE
6. S
IMPLIFIED
D
IAGRAM
OF
-15dB T1/E1 S
HORT
H
AUL
M
ODE
AND
RLOS C
ONDITION
Norm alized up to +15dB Max
Norm alized up to +15dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
25
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See
Figure 7
for a simplified diagram.
Setting the Receiver Inputs to -36dB T1/E1 Long Haul Mode
By setting the receiver inputs to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +36dB normalizing the T1 input signal. This setting
refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to
0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an
additional -9dB. The total cable loss at RLOS declaration is typically -45dB (-36dB + -9dB). A 3dB hysteresis
was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a
total cable attenuation of -42dB. See
Figure 8
for a simplified diagram.
E1 Extended RLOS
E1: Setting the Receiver Inputs to Extended RLOS
By setting the receiver inputs to extended RLOS, the equalizer will detect the incoming amplitude and make
adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to
cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding
the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB.
F
IGURE
7. S
IMPLIFIED
D
IAGRAM
OF
-29dB T1/E1 G
AIN
M
ODE
AND
RLOS C
ONDITION
F
IGURE
8. S
IMPLIFIED
D
IAGRAM
OF
-36dB T1/E1 L
ONG
H
AUL
M
ODE
AND
RLOS C
ONDITION
Norm alized up to +29dB Max
Norm alized up to +29dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
Norm alized up to +36dB Max
Norm alized up to +36dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
26
The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See
Figure 9
for a simplified diagram.
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a "1" is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
RCLK for all eight channels. Writing a "0" to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
F
IGURE
9. S
IMPLIFIED
D
IAGRAM
OF
E
XTENDED
RLOS
MODE
(E1 O
NLY
)
F
IGURE
10. R
ECEIVE
C
LOCK
AND
O
UTPUT
D
ATA
T
IMING
Norm alized up to +45dB Max
Norm alized up to +45dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
27
JITTER ATTENUATOR
To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive
signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set "High" the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO
length will not be available in this mode. Jitter attenuator controls are available on a per channel basis in the
Host mode and on a global basis in the Hardware mode.
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)
The XRT83L38 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width of the 8-Channel LIU is shown in Table 2.
N
OTE
: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.
T
ABLE
2: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
FIFO D
EPTH
M
AXIMUM
G
AP
W
IDTH
32-Bit
20 UI
64-Bit
50 UI
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
28
ARBITRARY PULSE GENERATOR FOR T1 AND E1
The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit
binary word by programming the appropriate channel register. This allows the system designer to set the
overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is
set to "1", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set
to "0", the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 11.
N
OTE
: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern
to the line. For E1 arbitrary mode, see global register 0xC0h.
TRANSMITTER
DIGITAL DATA FORMAT
Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is
available under both Hardware and Host control modes, on a global basis. The dual or single-rail data format
is determined by the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In
single-rail mode, transmit clock and NRZ data are applied to TCLK_n and TPOS_n/TDATA_n pins respectively.
In single-rail and Hardware mode the TNEG_n/CODES_n input can be used as the CODES function. With
TNEG_n/CODES_n tied "Low", HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes
respectively. With TNEG_n/CODES_n tied "High", the AMI coding scheme is selected. In both dual or single-
rail modes of operations, the transmitter converts digital input data to a bipolar format before being transmitted
to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n are clocked into the XRT83L38 under the
synchronization of TCLK_n. With a "0" written to the TCLKE interface bit, or by pulling the TCLKE pin "Low",
input data is sampled on the falling edge of TCLK_n. The sampling edge is inverted with a "1" written to TCLKE
interface bit, or by connecting the TCLKE pin "High".
F
IGURE
11. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
1
2
3
4
5
6
7
8
Segment
Register
1
0xn8
2
0xn9
3
0xna
4
0xnb
5
0xnc
6
0xnd
7
0xne
8
0xnf
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
29
TRANSMIT HDB3/B8ZS ENCODER
The Encoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode
and with HDB3 encoding selected, any sequence with four or more consecutive zeros in the input serial data
from TPOS_n/TDATA_n, will be removed and replaced with 000V or B00V, where "B" indicates a pulse
conforming with the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 Encoding
is shown in
Table 3
. In a T1 system, an input data sequence with eight or more consecutive zeros will be
removed and replaced using the B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS)
encoding scheme is shown in
Table 4
. Writing a "
1
" into the CODES_n interface bit or connecting the TNEG_n/
CODES_n pin to a "High" level selects the AMI coding for both E1 or T1 systems.
F
IGURE
12. T
RANSMIT
C
LOCK
AND
I
NPUT
D
ATA
T
IMING
T
ABLE
3: E
XAMPLES
OF
HDB3 E
NCODING
N
UMBER
OF
PULSE
BEFORE
NEXT
4
ZEROS
N
EXT
4
BITS
Input
0000
HDB3 (case1)
odd
000V
HDB3 (case2)
even
B00V
T
ABLE
4: E
XAMPLES
OF
B8ZS E
NCODING
C
ASE
1
P
RECEDING
P
ULSE
N
EXT
8 B
ITS
Input
+
00000000
B8ZS
000VB0VB
AMI Output
+
000+ -0- +
C
ASE
2
Input
-
00000000
B8ZS
000VB0VB
AMI Output
-
000- +0+ -
TCLK
R
TCLK
F
TCLK
TPOS/TDATA
or
TNEG
T
SU
T
HO
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
30
DRIVER FAILURE MONITOR (DMO)
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding
DMO pin goes "High" and remains "High" until a valid transmit pulse is detected. In Host mode, the failure of
the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any
transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both
Hardware and Host modes on a per channel basis.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode
transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip
supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform
generator for arbitrary transmit output pulse shapes (The arbitrary pulse generators are available for both T1
and E1). Transmit Line Build-Outs for T1 long-haul application are supported from 0dB to -22.5dB in three
7.5dB steps. The choice of the transmit pulse shape and LBO under the control of the interface bits are
summarized in
Table 5
. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-
to-Customer Installation specification, Annex-E.
N
OTE
: EQC[4:0] determine the T1/E1 operating mode of the XRT83L38. When EQC4 = "1" and EQC3 = "1", the XRT83L38
is in the E1 mode, otherwise it is in the T1/J1 mode. For details on how to enable the E1 arbitrary mode, see global
register 0xC0h.
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
EQC4 EQC3
EQC2
EQC1
EQC0
E1/T1 M
ODE
& R
ECEIVE
S
ENSITIVITY
T
RANSMIT
LBO
C
ABLE
C
ODING
0
0
0
0
0
T1 Long Haul/36dB
0dB
100
/ TP
B8ZS
0
0
0
0
1
T1 Long Haul/36dB
-7.5dB
100
/ TP
B8ZS
0
0
0
1
0
T1 Long Haul/36dB
-15dB
100
/ TP
B8ZS
0
0
0
1
1
T1 Long Haul/36dB
-22.5dB
100
/ TP
B8ZS
0
0
1
0
0
T1 Long Haul/45dB
0dB
100
/ TP
B8ZS
0
0
1
0
1
T1 Long Haul/45dB
-7.5dB
100
/ TP
B8ZS
0
0
1
1
0
T1 Long Haul/45dB
-15dB
100
/ TP
B8ZS
0
0
1
1
1
T1 Long Haul/45dB
-22.5dB
100
/ TP
B8ZS
0
1
0
0
0
T1 Short Haul/15dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1
0
0
1
T1 Short Haul/15dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
0
1
0
1
0
T1 Short Haul/15dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
0
1
0
1
1
T1 Short Haul/15dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
0
1
1
0
0
T1 Short Haul/15dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
31
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83L38 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 7)
I
NTERNAL
R
ECEIVE
T
ERMINATION
M
ODE
0
1
1
0
1
T1 Short Haul/15dB
Arbitrary Pulse
100
/ TP
B8ZS
0
1
1
1
0
T1 Gain Mode/29dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1
1
1
1
T1 Gain Mode/29dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
1
0
0
0
0
T1 Gain Mode/29dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
1
0
0
0
1
T1 Gain Mode/29dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
1
0
0
1
0
T1 Gain Mode/29dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
1
0
0
1
1
T1 Gain Mode/29dB
Arbitrary Pulse
100
/ TP
B8ZS
1
0
1
0
0
T1 Gain Mode/29dB
0dB
100
/ TP
B8ZS
1
0
1
0
1
T1 Gain Mode/29dB
-7.5dB
100
/ TP
B8ZS
1
0
1
1
0
T1 Gain Mode/29dB
-15dB
100
/ TP
B8ZS
1
0
1
1
1
T1 Gain Mode/29dB
-22.5dB
100
/ TP
B8ZS
1
1
0
0
0
E1 Long Haul/36dB
ITU G.703/Arbitrary
75
Coax
HDB3
1
1
0
0
1
E1 Long Haul/36dB
ITU G.703/Arbitrary
120
TP
HDB3
1
1
0
1
0
E1 Long Haul/43dB
ITU G.703/Arbitrary
75
Coax
HDB3
1
1
0
1
1
E1 Long Haul/43dB
ITU G.703/Arbitrary
120
TP
HDB3
1
1
1
0
0
E1 Short Haul
ITU G.703/Arbitrary
75
Coax
HDB3
1
1
1
0
1
E1 Short Haul
ITU G.703/Arbitrary
120
TP
HDB3
1
1
1
1
0
E1 Gain Mode
ITU G.703/Arbitrary
75
Coax
HDB3
1
1
1
1
1
E1 Gain Mode
ITU G.703/Arbitrary
120
TP
HDB3
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
EQC4 EQC3
EQC2
EQC1
EQC0
E1/T1 M
ODE
& R
ECEIVE
S
ENSITIVITY
T
RANSMIT
LBO
C
ABLE
C
ODING
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
32
In Hardware mode, RXTSEL (Pin 83) can be tied "High" to select internal termination mode for all receive
channels or tied "Low" to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83L38 is set for external termination mode at power up or at Hardware reset.
In Host mode, bit 7 in the appropriate channel register, (
Table 20, "Microprocessor Register #1, Bit
Description," on page 51
), is set "High" to select the internal termination mode for that specific receive channel.
If the internal termination mode (RXTSEL = "1") is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in
Table 7
.
N
OTE
: In Hardware mode, pins RXRES[1:0] control all channels.
T
ABLE
6: R
ECEIVE
T
ERMINATION
C
ONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
F
IGURE
13. S
IMPLIFIED
D
IAGRAM
FOR
THE
I
NTERNAL
R
ECEIVE
AND
T
RANSMIT
T
ERMINATION
M
ODE
T
ABLE
7: R
ECEIVE
T
ERMINATIONS
RXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
R
ext
R
int
M
ODE
0
x
x
x
x
R
ext
T1/E1/J1
1
0
0
0
0
100
T1
1
0
1
0
0
110
J1
1
1
0
0
0
75
E1
T1
TTIP
TRING
5
8
1:2
75
, 100
110
or 120
4
1
0.68
µ
F
R
int
R
int
TTIP
TRING
T X
Line Driver
T2
RTIP
RRING
1
4
1:1
8
5
RTIP
RRIN G
R X
Equalizer
R
int
Channel _n
TPO S
TN EG
TC LK
RPOS
R N EG
RC LK
75
, 100
110
or 120
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
33
Figure 14
is a simplified diagram for T1 (100
) in the external receive and transmit termination mode.
Figure 15
is a simplified diagram for E1 (75
) in the external receive and transmit termination mode.
1
1
1
0
0
120
E1
1
0
0
0
1
240
172
T1
1
0
1
0
1
240
204
J1
1
1
0
0
1
240
108
E1
1
1
1
0
1
240
240
E1
1
0
0
1
0
210
192
T1
1
0
1
1
0
210
232
J1
1
1
0
1
0
210
116
E1
1
1
1
1
0
210
280
E1
1
0
0
1
1
150
300
T1
1
0
1
1
1
150
412
J1
1
1
0
1
1
150
150
E1
1
1
1
1
1
150
600
E1
F
IGURE
14. S
IMPLIFIED
D
IAGRAM
FOR
T1
IN
THE
E
XTERNAL
T
ERMINATION
M
ODE
(RXTSEL= 0)
T
ABLE
7: R
ECEIVE
T
ERMINATIONS
RXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
R
ext
R
int
M
ODE
3 .1
3 .1
T T IP
T R IN G
R T IP
R R IN G
X R T 8 3 L 3 8 L IU
1 0 0
1 0 0
1 0 0
1 :2 .4 5
1 :1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
34
TRANSMITTER (CHANNELS 0 - 7)
T
RANSMIT
T
ERMINATION
M
ODE
In Hardware mode, TXTSEL (Pin 84) can be tied "High" to select internal termination mode for all transmit
channels or tied "Low" for external termination. Individual channel control can be done only in Host mode. In
Host mode, bit 6 in the appropriate register for a given channel is set "High" to select the internal termination
mode for that specific transmit channel, see
Table 20, "Microprocessor Register #1, Bit Description," on
page 51
.
In internal mode, no external resistors are used. An external capacitor of 0.68
µ
F is used for proper operation of
the internal termination circuitry, see
Figure 13
.
E
XTERNAL
T
RANSMIT
T
ERMINATION
M
ODE
By default the XRT83L38 is set for external termination mode at power up or at Hardware reset.
When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of
the external resistors is chosen for a specific application according to the turns ratio selected by TRATIO (Pin
127) in Hardware mode or bit 0 in the appropriate register for a specific channel in Host mode, see
Table 10
and
Table 22, "Microprocessor Register #3, Bit Description," on page 55
.
Figure 14
is a simplified block
diagram for T1 (100
) in the external termination mode.
Figure 15
is a simplified block diagram for E1 (75
) in
the external termination mode.
F
IGURE
15. S
IMPLIFIED
D
IAGRAM
FOR
E1
IN
E
XTERNAL
T
ERMINATION
M
ODE
(RXTSEL= 0)
T
ABLE
8: T
RANSMIT
T
ERMINATION
C
ONTROL
TXTSEL
TX TERMINATION
T
X
T
RANSFORMER
R
ATIO
0
EXTERNAL
1:2.45
1
INTERNAL
1:2
T
ABLE
9: T
ERMINATION
S
ELECT
C
ONTROL
TERSEL1
TERSEL0
TERMINATION
0
0
100
0
1
110
1
0
75
1
1
120
9 .1
9 .1
T T IP
T R IN G
R T IP
R R IN G
7 5
X R T 8 3L 38 L IU
75
75
1 :2 .4 5
1 :1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
35
Table 11
summarizes the transmit terminations.
REDUNDANCY APPLICATIONS
Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has
a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without
losing data. System designers can achieve this by implementing common redundancy schemes with the
XRT83L38 Line Interface Unit (LIU). The XRT83L38 offers features that are tailored to redundancy applications
while reducing the number of components and providing system designers with solid reference designs. These
features allow system designers to implement redundancy applications that ensure reliability. The Internal
Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy schemes.
PROGRAMMING CONSIDERATIONS
In many applications switching the control of the transmitter outputs and the receiver line impedance to
hardware control will provide faster transmitter ON/OFF switching.
T
ABLE
10: T
RANSMIT
T
ERMINATION
C
ONTROL
TRATIO
T
URNS
R
ATIO
0
1:2.45
1
1:2
T
ABLE
11: T
RANSMIT
T
ERMINATIONS
TERSEL1
TERSEL0
TXTSEL
TRATIO
R
int
n
R
ext
C
ext
0=
EXTERNAL
SET
BY
CONTROL
BITS
n, R
ext
,
AND
C
ext
ARE
SUGGESTED
SETTINGS
1=
INTERNAL
T1
100
0
0
0
0
0
2.45
3.1
0
0
0
0
1
0
2
3.1
0
0
0
1
x
12.5
2
0
0.68
µ
F
J1
110
0
1
0
0
0
2.45
3.1
0
0
1
0
1
0
2
3.1
0
0
1
1
x
13.75
2
0
0.68
µ
F
E1
75
1
0
0
0
0
2.45
6.2
0
1
0
0
1
0
2
9.1
0
1
0
1
x
9.4
2
0
0.68
µ
F
E1
120
1
1
0
0
0
2.45
6.2
0
1
1
0
1
0
2
9.1
0
1
1
1
x
15
2
0
0.68
µ
F
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
36
In Host Mode, there are two bits in register 130 (82H) that control the transmitter outputs and the Rx line
impedance select, TXONCNTL (Bit 7) and TERCNTL (Bit 6).
Setting bit-7 (TXONCNTL) to a "1" transfers the control of the Transmit On/Off function to the TXON_n
Hardware control pins. (Pins 90 through 93 and pins 169 through 172).
Setting bit-6 (TERCNTL) to a "1" transfers the control of the Rx line impedance select (RXTSEL) to the
RXTSEL Hardware control pin (pin 83).
Either mode works well with redundancy applications. The user can determine which mode has the fastest
switching time for a unique application.
TYPICAL REDUNDANCY SCHEMES
s
·1:1 One backup card for every primary card (Facility Protection)
s
·1+1 One backup card for every primary card (Line Protection)
s
·N+1One backup card for N primary cards
1:1 REDUNDANCY
A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1
redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates
the need for external relays and provides one bill of materials for all interface modes of operation. The transmit
and receive sections of the LIU device are described separately.
1+1 REDUNDANCY
A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on
the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active.
The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are
described separately.
TRANSMIT 1:1 & 1+1 REDUNDANCY
For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for
Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate
impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for
blocking DC bias. See
Figure 16
for a simplified block diagram of the transmit section for 1:1 and 1+1
redundancy scheme.
N
OTE
: For simplification, the over voltage protection circuitry was omitted.
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
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RECEIVE 1:1 & 1+1 REDUNDANCY
For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance
mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is
no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design
feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup
card to Internal Impedance mode, then the primary card to External Impedance mode. See
Figure 17
for a
simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme.
N
OTE
: For simplification, the over voltage protection circuitry was omitted.
F
IGURE
16. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
S
ECTION
FOR
1:1 & 1+1 R
EDUNDANCY
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
- R
ECEIVE
S
ECTION
FOR
1:1
AND
1+1 R
EDUNDANCY
T 1 /E 1 L in e
B a ckp la n e In te rfa ce
P rim a ry C a rd
B a cku p C a rd
X R T 8 3 L 3 8
X R T 8 3 L 3 8
T x
T x
L in e In te rfa ce C a rd
0 .6 8
µ
F
0 .6 8
µ
F
T xT S E L =1 , In te rn a l
T xT S E L =1 , In te rn a l
1 :2 o r 1 :2 .4 5
R xT S E L =0 , E xte rn a l
R xT S E L =1 , In te rn a l
B a ckp la n e In te rfa ce
P rim a ry C a rd
B a cku p C a rd
X R T 8 3 L 3 8
X R T 8 3 L 3 8
R x
L in e In te rfa ce C a rd
T 1 /E 1 L in e
R x
1 :1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
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N+1 REDUNDANCY
N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,
external relays are necessary when using this redundancy scheme. The advantage of relays is that they create
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83L38 are described separately.
TRANSMIT
For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68
µ
F capacitor is used in series with TTIP for blocking DC bias. See
Figure 18
for a simplified block diagram
of the transmit section for an N+1 redundancy scheme.
N
OTE
: For simplification, the over voltage protection circuitry was omitted.
F
IGURE
18. S
IMPLIFIED
B
LOCK
D
IAGRAM
- T
RANSMIT
S
ECTION
FOR
N+1 R
EDUNDANCY
B a ckp lan e In terfa ce
P rim a ry C a rd
X R T 83 L3 8
T x
Lin e In te rfac e C ard
0 .68
µ
F
T 1/E 1 Lin e
P rim ary C a rd
X R T 83 L3 8
T x
P rim a ry C a rd
X R T 83 L 38
T x
B a cku p C a rd
X R T 83 L 38
T x
T 1 /E 1 L ine
T 1 /E 1 L ine
T xT S E L=1 , Internal
T xT S E L=1 , Internal
T xT S E L=1 , Internal
T xT S E L = 1 , Inte rn a l
1:2 or 1 :2 .4 5
1 :2 o r 1:2.4 5
1:2 or 1 :2.45
0 .68
µ
F
0 .68
µ
F
0.6 8
µ
F
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
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RECEIVE
For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode.
The receivers on the backup card should be programmed for external impedance mode. Since there is no
external resistor in the circuit, the receivers on the backup card will be high impedance. Select the impedance
for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal
impedance mode, then the primary card to external impedance mode. See
Figure 19
. for a simplified block
diagram of the receive section for a N+1 redundancy scheme.
N
OTE
: For simplification, the over voltage protection circuitry was omitted.
F
IGURE
19. S
IMPLIFIED
B
LOCK
D
IAGRAM
- R
ECEIVE
S
ECTION
FOR
N+1 R
EDUNDANCY
B a ckp la n e In te rfa ce
P rim a ry C a rd
X R T 8 3 L 3 8
R x
L in e In te rfa ce C a rd
P rim a ry C a rd
X R T 8 3 L 3 8
R x
P rim a ry C a rd
X R T 8 3 L 3 8
R x
B a cku p C a rd
X R T 8 3 L 3 8
R x
R xT S E L =1 , In te rn a l
R xT S E L =1 , In te rn a l
R xT S E L =1 , In te rn a l
R xT S E L =1 , E xte rn a l
T 1 /E 1 L in e
T 1 /E 1 L in e
T 1 /E 1 L in e
1 :1
1 :1
1 :1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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PATTERN TRANSMIT AND DETECT FUNCTION
Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each
channel can be independently programmed to transmit an All Ones pattern by applying a "High" level to the
corresponding TAOS_n pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation
and detection independently for each channel according to
Table 12
.
TRANSMIT ALL ONES (TAOS)
This feature is available in both Hardware and Host modes. With the TAOS_n pin connected to a "High" level
or when interface bits TXTEST2="1", TXTEST1="0" and TXTEST0="1" the transmitter ignores input from
TPOS_n/TDATA_n and TNEG_n/CODES_n pins and sends a continuous AMI encoded all "Ones" signal to the
line, using TCLK_n clock as the reference. In addition, when the Hardware pin and interface bit ATAOS is
activated, the chip will automatically transmit the All "Ones" data from any channel that detects an RLOS
condition. This feature is not available on a per channel basis. TCLK_n must NOT be tied "Low".
NETWORK LOOP CODE DETECTION AND TRANSMISSION
This feature is available in Host mode only. When the interface bits TXTEST2="1", TXTEST1="1" and
TXTEST0="0" the chip is enabled to transmit the "00001" Network Loop-Up Code from the selected channel
requesting a Loop-Back condition from the remote terminal. Simultaneously setting the interface bits
NLCDE1="0" and NLCDE0="1" enables the Network Loop-Up code detection in the receiver. If the "00001"
Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface
register is set indicating that the remote terminal has activated remote Loop-Back and the chip is receiving its
own transmitted data. When the interface bits TXTEST2="1", TXTEST1="1" and TXTEST0="1" the chip is
enabled to transmit the Network Loop-Down Code (TLDC) "001" from the selected channel requesting the
remote terminal the removal of the Loop-Back condition.
In the Host mode each channel is capable of monitoring the contents of the receive data for the presence of
Loop-Up or Loop-Down code from the remote terminal. In the Host mode the two interface bits NLCDE[1:0]
control the Loop-Code detection independently for each channel according to
Table 13
.
Setting the interface bits to NLCDE1="0" and NLCDE0="1" activates the detection of the Loop-Up code in the
receive data. If the "00001" Network Loop-Up code is detected in the receive data for longer than 5 seconds,
the NLCD interface bit is set to "1" and stays in this state for as long as the receiver continues to receive the
T
ABLE
12: P
ATTERN
TRANSMISSION
CONTROL
TXTEST2
TXTEST1
TXTEST0
T
EST
P
ATTERN
0
x
x
None
1
0
0
TDQRSS
1
0
1
TAOS
1
1
0
TLUC
1
1
1
TLDC
T
ABLE
13: L
OOP
-C
ODE
D
ETECTION
C
ONTROL
NLCDE1
NLCDE0
CONDITION
0
0
Disable Loop-Code Detection
0
1
Detect Loop-Up Code in Receive Data
1
0
Detect Loop-Down Code in Receive Data
1
1
Automatic Loop-Code detection and Remote Loop-Back Activation
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
41
Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every
transition of NLCD. The host has the option to ignore the request from the remote terminal, or to respond to the
request and manually activate Remote Loop-Back. The host can subsequently activate the detection of the
Loop-Down Code by setting NLCDE1="1" and NLCDE0="0". In this case, receiving the "001" Loop-Down Code
for longer than 5 seconds will set the NLCD bit to "1" and if the NLCD interrupt is enabled, the chip will initiate
an interrupt on every transition of NLCD. The host can respond to the request from the remote terminal and
remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1="0" and NLCDE0="1") and Loop-
Down (NLCDE1="1" and NLCDE0="0") Code detection modes, the NLCD interface bit will be set to "1" upon
receiving the corresponding code in excess of 5 seconds in the receive data. The chip will initiate an interrupt
any time the status of the NLCD bit changes and the Network Loop-code interrupt is enabled.
In the Host mode, setting the interface bits NLCDE1="1" and NLCDE0="1" enables the automatic Loop-Code
detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to "110". As this mode is
initiated, the state of the NLCD interface bit is reset to "0" and the chip is programmed to monitor the receive
input data for the Loop-Up Code. If the "00001" Network Loop-Up Code is detected in the receive data for
longer than 5 seconds in addition to the NLCD bit in the interface register being set, Remote Loop-Back is
automatically activated. The chip stays in remote Loop-Back even if it stops receiving the "00001" pattern. After
the chip detects the Loop-Up code, sets the NLCD bit and enters Remote Loop-Back, it automatically starts
monitoring the receive data for the Loop-Down code. In this mode however, the NLCD bit stays set even if the
receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote Loop-Back is still
in effect. Remote Loop-Back is removed if the chip detects the "001" Loop-Down code for longer than 5
seconds. Detecting the "001" code also results in resetting the NLCD interface bit and initiating an interrupt.
The Remote Loop-Back can also be removed by taking the chip out of the Automatic detection mode by
programming it to operate in a different state. The chip will not respond to remote Loop-Back request if Local
Analog Loop-Back is activated locally. When programmed in Automatic detection mode the NLCD interface bit
stays "High" for the whole time the Remote Loop-Back is activated and initiates an interrupt any time the status
of the NLCD bit changes provided the Network Loop-code interrupt is enabled.
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)
Each channel of XRT83L38 includes a QRSS pattern generation and detection block for diagnostic purposes
that can be activated only in the Host mode by setting the interface bits TXTEST2="1", TXTEST1="0" and
TXTEST0="0". For T1 systems, the QRSS pattern is a 2
20
-1pseudo-random bit sequence (PRBS) with no
more than 14 consecutive zeros. For E1 systems, the QRSS pattern is 2
15
-1 PRBS with an inverted output.
With QRSS and Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD
interface bit, all main functional blocks within the transceiver can be verified.
When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD
changes from "Low" to "High". After pattern synchronization, any bit error will cause QRPD to go "Low" for one
clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.
With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the
INSBER interface bit from "0" to "1". Bipolar violation can also be inserted either in the QRSS pattern, or input
data when operating in the single-rail mode by transitioning the INSBPV interface bit from "0" to "1". The state
of INSBER and INSBPV bits are sampled on the rising edge of the TCLK_n. To insure the insertion of the bit
error or bipolar violation, a "0" should be written in these bit locations before writing a "1".
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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LOOP-BACK MODES
The XRT83L38 supports several Loop-Back modes under both Hardware and Host control. In Hardware
mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently according to
Table 14
.
In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. Each channel can
be programmed independently according to
Table 15
.
LOCAL ANALOG LOOP-BACK (ALOOP)
With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83L38 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in
Figure 20
.
In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.
T
ABLE
14: L
OOP
-
BACK
CONTROL
IN
H
ARDWARE
MODE
LOOP1
LOOP0
L
OOP
-
BACK
M
ODE
0
0
None
0
1
Analog
1
0
Remote
1
1
Digital
T
ABLE
15: L
OOP
-
BACK
CONTROL
IN
H
OST
MODE
LOOP2
LOOP1
LOOP0
L
OOP
-
BACK
M
ODE
0
X
X
None
1
0
0
Dual
1
0
1
Analog
1
1
0
Remote
1
1
1
Digital
F
IGURE
20. L
OCAL
A
NALOG
L
OOP
-
BACK
SIGNAL
FLOW
Rx
Data &
Clock
Recovery
Decoder
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Tx
Encoder
Timing
Control
JA
TTIP
TRING
RTIP
RRING
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
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REMOTE LOOP-BACK (RLOOP)
With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in
Figure 21
.
In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in
Figure 22
.
F
IGURE
21. R
EMOTE
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
RECEIVE
PATH
F
IGURE
22. R
EMOTE
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
T
RANSMIT
PATH
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
JA
Tx
Decoder
Timing
Control
Rx
Clock &
Data
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
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DIGITAL LOOP-BACK (DLOOP)
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in
Figure 23
.
DUAL LOOP-BACK
Figure 24
depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path
will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
F
IGURE
23. D
IGITAL
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
T
RANSMIT
PATH
F
IGURE
24. S
IGNAL
FLOW
IN
D
UAL
LOOP
-
BACK
MODE
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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MICROPROCESSOR PARALLEL INTERFACE
XRT83L38 is equipped with a microprocessor interface for easy device configuration. The parallel port of the
XRT83L38 is compatible with both Intel and Motorola address and data buses. The XRT83L38 has an 8-bit
address A[7:0] input and 8-bit bi-directional data bus D[7:0]. The signals required for a generic microprocessor
to access the internal registers are described in
Table 16
.
T
ABLE
16: M
ICROPROCESSOR
INTERFACE
SIGNAL
DESCRIPTION
D[7:0]
Data Input (Output): 8 bits bi-directional Read/Write data bus for register access.
A[7:0]
Address Input: 8 bit address to select internal register location.
µ
PTS1
µ
PTS2
Microprocessor Type Select:
µ
PCLK
Microprocessor Clock Input: Input clock for synchronous microprocessor operation. Maximum
clock speed is 54MHz. This pin is internally pulled "Low" for asynchronous microprocessor operation
when no clock is present.
ALE_AS
Address Latch Input (Address Strobe):
-Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE.
-Motorola bus timing, the address inputs are latched into the internal register on the falling edge of
AS.
CS
Chip Select Input: This signal must be "Low" in order to access the parallel port.
RD_DS
Read Input (Data Strobe):
-Intel bus timing, a "Low" pulse on RD selects a read operation when CS pin is "Low".
-Motorola bus timing, a "Low" pulse on DS indicates a read or write operation when CS pin is "Low".
WR_R/W
Write Input (Read/Write):
-Intel bus timing, a "Low" pulse on WR selects a write operation when CS pin is "Low".
-Motorola bus timing, a "High" pulse on R/W selects a read operation and a "Low" pulse on R/W
selects a write operation when CS pin is "Low".
RDY_DTACK
Ready Output (Data Transfer Acknowledge Output):
-Intel bus timing, RDY is asserted "High" to indicate the XRT83L38 has completed a read or write
operation.
-Motorola bus timing, DTACK is asserted "Low" to indicate the XRT83L38 has completed a read or
write operation.
INT
Interrupt Output: This pin is asserted "Low" to indicate an interrupt caused by an alarm condition in
the device status registers. The activation of this pin can be blocked by setting the GIE bit to "0" in the
Command Control register.
µ
P T S 2
µ
P T S 1
0
0
0
1
1
0
µ
P T yp e
6 8 H C 1 1 , 8 0 5 1 , 8 0 C 1 8 8 (a syn c.)
M o to ro la 6 8 K (a syn c.)
In te l x8 6 (syn c.)
In te l i9 6 0 , M o to ro la 8 6 0 (syn c.)
1
1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 8 byte
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in
Table 17
and
Table 18
respectively.
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
R
EGISTER
N
UMBER
R
EGISTER
A
DDRESS
F
UNCTION
HEX
BINARY
0 - 15
0x00 - 0x0F
00000000 - 00001111
Channel 0 Control Registers
16 - 31
0x10 -0x1F
00010000 - 00011111
Channel 1 Control Registers
32 - 47
0x20 - 0x2F
00100000 - 00101111
Channel 2 Control Registers
48 - 63
0x30 - 0x3F
00110000 - 00111111
Channel 3 Control Registers
64 - 79
0x40 - 0x4F
01000000 - 01001111
Channel 4 Control Registers
80 - 95
0x50 - 0x5F
01010000 - 01011111
Channel 5 Control Registers
96-111
0x60 - 0x6F
01100000 - 01101111
Channel 6 Control Registers
112 - 127
0x70 - 0x7F
01110000 - 01111111
Channel 7 Control Registers
128 - 131
0x80 - 0x83
10000000 - 10000011
Command Control registers for all 8 channels
132 -139
0x84 - 0x8B
10000100 - 10001011
R/W registers reserved for testing channels 0-3
140 - 191
0x8C - 0xBF
10001100 - 10111111
Reserved
192
0xC0
11000000
Command Control register for all 8 channels
193 - 195
0xC1 - 0xC3
11000001 - 11000011
Reserved
196 - 203
0xC4 - 0xCB
11000100 - 11001011
R/W registers reserved for testing channels 4-7
204 - 253
0xCC - 0xFD
11001100 - 11111101
Reserved
254
0xFE
11111110
Device "ID"
255
0xFF
11111111
Device "Revision ID"
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
R
EG
. #
A
DDRESS
R
EG
.
T
YPE
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Channel 0 Control Registers
0
00000000
Hex 0x00
R/W
Reserved
Reserved
RXON_n
EQC4_n
EQC3_n
EQC2_n
EQC1_n
EQC0_n
1
00000001
Hex 0x01
R/W
RXTSEL_n
TXTSEL_n
TERSEL1_n
TERSEL0_n
JASEL1_n
JASEL0_n
JABW_n
FIFOS_n
2
00000010
Hex 0x02
R/W
INVQRSS_n
TXTEST2_n
TXTEST1_n
TXTEST0_n
TXON_n
LOOP2_n
LOOP1_n
LOOP0_n
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
47
3
00000011
Hex 0x03
R/W
NLCDE1_n
NLCDE0_n
CODES_n
RXRES1_n
RXRES0_n
INSBPV_n
INSBER_n
TRATIO_n
4
00000100
Hex 0x04
R/W
Reserved
DMOIE_n
FLSIE_n
LCVIE_n
NLCDIE_n
AISDIE_n
RLOSIE_n
QRPDIE_n
5
00000101
Hex 0x05
RO
Reserved
DMO_n
FLS_n
LCV_n
NLCD_n
AISD_n
RLOS_n
QRPD_n
6
00000110
Hex 0x06
RUR
Reserved
DMOIS_n
FLSIS_n
LCVIS_n
NLCDIS_n
AISDIS_n
RLOSIS_n
QRPDIS_n
7
00000111
Hex 0x07
RO
Reserved
Reserved
CLOS5_n
CLOS4_n
CLOS3_n
CLOS2_n
CLOS1_n
CLOS0_n
8
00001000
Hex 0x08
R/W
X
B6S1_n
B5S1_n
B4S1_n
B3S1_n
B2S1_n
B1S1_n
B0S1_n
9
00001001
Hex 0x09
R/W
X
B6S2_n
B5S2_n
B4S2_n
B3S2_n
B2S2_n
B1S2_n
B0S2_n
10
00001010
Hex 0x0A
R/W
X
B6S3_n
B5S3_n
B4S3_n
B3S3_n
B2S3_n
B1S3_n
B0S3_n
11
00001011
Hex 0x0B
R/W
X
B6S4_n
B5S4_n
B4S4_n
B3S4_n
B2S4_n
B1S4_n
B0S4_n
12
00001100
Hex 0x0C
R/W
X
B6S5_n
B5S5_n
B4S5_n
B3S5_n
B2S5_n
B1S5_n
B0S5_n
13
00001101
Hex 0x0D
R/W
X
B6S6_n
B5S6_n
B4S6_n
B3S6_n
B2S6_n
B1S6_n
B0S6_n
14
00001110
Hex 0x0E
R/W
X
B6S7_n
B5S7_n
B4S7_n
B3S7_n
B2S7_n
B1S7_n
B0S7_n
15
00001111
Hex 0x0F
R/W
X
B6S8_n
B5S8_n
B4S8_n
B3S8_n
B2S8_n
B1S8_n
B0S8_n
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Command Control Global Registers for all 8 channels
16-31
0001xxxx
Hex 0x10-
0x1F
R/W
Channel 1Control Register (see Registers 0-15 for description)
32-47
0010xxxx
Hex 0x20-
ox2F
R/W
Channel 2 Control Register (see Registers 0-15 for description)
48-63
0011xxxx
Hex 0x30-
0x3F
R/W
Channel 3 Control Register (see Registers 0-15 for description)
64-79
0100xxxx
Hex 0x40-
0x4F
R/W
Channel 4 Control Register (see Registers 0-15 for description)
80-95
0101xxxx
Hex 0x50-
0x5F
R/W
Channel 5 Control Register (see Registers 0-15 for description)
96-111
0110xxxx
Hex 0x60-
0x6F
R/W
Channel 6 Control Register (see Registers 0-15 for description)
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
R
EG
. #
A
DDRESS
R
EG
.
T
YPE
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
48
112-127
0111xxxx
Hex 0x70-
0x7F
R/W
Channel 7 Control Register (see Registers 0-15 for description)
Command Control Registers for All 8 Channels
128
10000000
Hex 0x80
R/W
SR/DR
ATAOS
RCLKE
TCLKE
DATAP
Reserved
GIE
SRESET
129
10000001
Hex 0x81
R/W
Reserved
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
RXMUTE
EXLOS
ICT
130
10000010
Hex 0x82
R/W
TXONCNTL
TERCNTL
Reserved
Reserved
MONITOR_3
MONITOR_2
MONITOR_1
MONITOR_0
131
10000011
Hex 0x83
R/W
GAUGE1
GAUGE0
Reserved
Reserved
SL_1
SL_0
EQG_1
EQG_0
Test Registers for channels 0 - 3
132
10000100
R/W
Test byte 0
133
10000101
R/W
Test byte 1
134
10000110
R/W
Test byte 2
135
10000111
R/W
Test byte 3
136
10001000
R/W
Test byte 4
137
10001001
R/W
Test byte 5
138
10001010
R/W
Test byte 6
139
10001011
R/W
Test byte 7
Unused Registers
140-191
100011xx
Command Control Register for All 8 Channels
192
11000000
Hex 0xC0
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E1Arben
Unused Registers
193-195
110000xx
Test Registers for channels 4 - 7
196
11000100
R/W
Test byte 0
197
11000101
R/W
Test byte 0
198
11000110
R/W
Test byte 0
199
11000111
R/W
Test byte 0
200
11001000
R/W
Test byte 0
201
11001001
R/W
Test byte 0
202
11001010
R/W
Test byte 0
203
11001011
R/W
Test byte 0
Unused Registers
204
11001100
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
R
EG
. #
A
DDRESS
R
EG
.
T
YPE
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
49
....
253
11111101
ID Registers
254
11111110
Hex 0xFE
RO
DEVICE ID hex: FD - Binary 11111101
255
11111111
Hex 0xFF
RO
DEVICE "Revision ID"
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
R
EG
. #
A
DDRESS
R
EG
.
T
YPE
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
50
MICROPROCESSOR REGISTER DESCRIPTIONS
T
ABLE
19: M
ICROPROCESSOR
R
EGISTER
#0, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000000
00010000
00100000
00110000
01000000
01010000
01100000
01110000
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6
Reserved
R/W
D5
RXON_n
Receiver ON: Writing a "1" into this bit location turns on the
Receive Section of channel n. Writing a "0" shuts off the
Receiver Section of channel n.
N
OTES
:
1.
This bit provides independent turn-off or turn-on
control of each receiver channel.
2.
In Hardware mode all receiver channels are always
on in the TQFP package. In the BGA packace all
receiver channels can be turned on or off together by
applying the appropriate signal to the RXON pin (#
K16).
R/W
0
D4
EQC4_n
Equalizer Control bit 4: This bit together with EQC[3:0] are
used for controlling transmit pulse shaping, transmit line build-
out (LBO) and receive monitoring for either T1 or E1 Modes of
operation.
See
Table 5
for description of Equalizer Control bits.
R/W
0
D3
EQC3_n
Equalizer Control bit 3: See bit D4 description for function of
this bit
R/W
0
D2
EQC2_n
Equalizer Control bit 2: See bit D4 description for function of
this bit
R/W
0
D1
EQC1_n
Equalizer Control bit 1: See bit D4 description for function of
this bit
R/W
0
D0
EQC0_n
Equalizer Control bit 0: See bit D4 description for function of
this bit
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
51
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000001
00010001
00100001
00110001
01000001
01010001
01100001
01110001
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
RXTSEL_n
Receiver Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the receiver according to the following table;
R/W
0
D6
TXTSEL_n
Transmit Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the transmitter according to the following table;
R/W
0
D5
TERSEL1_n
Termination Impedance Select1:
In Host mode and in internal termination mode, (TXTSEL = "1"
and RXTSEL = "1") TERSEL[1:0] control the transmit and
receive termination impedance according to the following
table;
In the internal termination mode, the receiver termination of
each receiver is realized completely by internal resistors or by
the combination of internal and one fixed external resistor.
In the internal termination mode, the transmitter output should
be AC coupled to the transformer.
R/W
0
D4
TERSEL0_n
Termination Impedance Select bit 0:
R/W
0
RXTSEL
RX Termination
0
1
External
Internal
TXTSEL
TX Termination
0
1
External
Internal
TERSEL1 TERSEL0
0
0
0
1
1
0
1
1
Termination
100
110
75
120
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
52
D3
JASEL1_n
Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits
are used to disable or place the jitter attenuator of each chan-
nel independently in the transmit or receive path.
R/W
0
D2
JASEL0_n
Jitter Attenuator select bit 0: See description of bit D3 for the
function of this bit.
R/W
0
D1
JABW_n
Jitter Attenuator Bandwidth Select: In E1 mode, set this bit
to "1" to select a 1.5Hz Bandwidth for the Jitter Attenuator. The
FIFO length will be automatically set to 64 bits. Set this bit to
"0" to select 10Hz Bandwidth for the Jitter Attenuator in E1
mode. In T1 mode the Jitter Attenuator Bandwidth is perma-
nently set to 3Hz, and the state of this bit has no effect on the
Bandwidth.
R/W
0
D0
FIFOS_n
FIFO Size Select: See table of bit D1 above for the function of
this bit.
R/W
0
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
JASEL1
bit D3
JASEL0
bit D2
0
0
0
1
1
0
1
1
JA Path
JA Disabled
JA in Transmit Path
JA in Receive Path
JA in Receive Path
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
0
1
1
0
0
1
1
JABW
bit D1
T1
T1
T1
T1
E1
E1
E1
E1
Mode
32
64
32
64
32
64
64
64
FIFO
Size
3
3
3
3
10
10
1.5
1.5
JA B-W
Hz
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
53
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
#2, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000010
00010010
00100010
00110010
01000010
01010010
01100010
01110010
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
INVQRSS_n
Invert QRSS Pattern: When TQRSS is active, Writing a "1" to
this bit inverts the polarity of transmitted QRSS pattern. Writing
a "0" sends the QRSS pattern with no inversion.
R/W
0
D6
TXTEST2_n
Transmit Test Pattern bit 2: This bit together with TXTEST1
and TXTEST0 are used to generate and transmit test patterns
according to the following table:
TDQRSS (Transmit/Detect Quasi-Random Signal): This
condition when activated enables Quasi-Random Signal
Source generation and detection for the selected channel
number n. In a T1 system QRSS pattern is a 2
20
-1 pseudo-
random bit sequence (PRBS) with no more than 14 consecu-
tive zeros. In a E1 system, QRSS is a 2
15
-1 PRBS pattern.
TAOS (Transmit All Ones): Activating this condition enables
the transmission of an All Ones Pattern from the selected
channel number n.
TLUC (Transmit Network Loop-Up Code): Activating this
condition enables the Network Loop-Up Code of "00001" to be
transmitted to the line for the selected channel number n.
When Network Loop-Up code is being transmitted, the
XRT83L38 will ignore the Automatic Loop-Code detection and
Remote Loop-Back activation (NLCDE1 ="1", NLCDE0 ="1", if
activated) in order to avoid activating Remote Digital Loop-
Back automatically when the remote terminal responds to the
Loop-Back request.
TLDC (Transmit Network Loop-Down Code): Activating this
condition enables the network Loop-Down Code of "001" to be
transmitted to the line for the selected channel number n.
R/W
0
D5
TXTEST1_n
Transmit Test pattern bit 1: See description of bit D6 for the
function of this bit.
R/W
0
0
0
0
1
1
0
1
1
1
1
1
1
X
X
0
No Pattern
TDQRSS
TAOS
TLUC
Test Pattern
TLDC
TXTEST1
TXTEST0
TXTEST2
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
54
D4
TXTEST0_n
Transmit Test Pattern bit 0: See description of bit D6 for the
function of this bit.
R/W
0
D3
TXON_n
Transmitter ON: Writing a "1" into this bit location turns on the
Transmit and Receive Sections of channel n. Writing a "0"
shuts off the Transmit Section of channel n. In this mode,
TTIP_n and TRING_n driver outputs will be tri-stated for power
reduction or redundancy applications.
R/W
0
D2
LOOP2_n
Loop-Back control bit 2: This bit together with the LOOP1
and LOOP0 bits control the Loop-Back modes of the chip
according to the following table:
D1
LOOP1_n
Loop-Back control bit 1: See description of bit D2 for the
function of this bit.
R/W
0
D0
LOOP0_n
Loop-Back control bit 0: See description of bit D2 for the
function of this bit.
R/W
0
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
#2, B
IT
D
ESCRIPTION
LOOP2
0
1
1
1
1
LOOP1
X
0
0
1
1
LOOP0
X
0
1
0
1
Loop-Back Mode
No Loop-Back
Dual Loop-Back
Analog Loop-Back
Remote Loop-Back
Digital Loop-Back
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
55
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
#3, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000011
00010011
00100011
00110011
01000011
01010011
01100011
01110011
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
NLCDE1_n
Network Loop Code Detection Enable Bit 1:
This bit together with NLCDE0_n control the Loop-Code detec-
tion of each channel.
When NLCDE1 ="0" and NLCDE0 = "1" or NLCDE1 = "1" and
NLCDE0 = "0", the chip is manually programmed to monitor
the receive data for the Loop-Up or Loop-Down code respec-
tively.When the presence of the "00001" or "001" pattern is
detected for more than 5 seconds, the status of the NLCD bit is
set to "1" and if the NLCD interrupt is enabled, an interrupt is
initiated.The Host has the option to control the Loop-Back
function manually.
Setting the NLCDE1 = "1" and NLCDE0 = "1" enables the
Automatic Loop-Code detection and Remote Loop-Back acti-
vation mode. As this mode is initiated, the state of the NLCD
interface bit is reset to "0" and the chip is programmed to mon-
itor the receive data for the Loop-Up code. If the "00001" pat-
tern is detected for longer than 5 seconds, the NLCD bit is set
"1", Remote Loop-Back is activated and the chip is automati-
cally programmed to monitor the receive data for the Loop-
Down code. The NLCD bit stays set even after the chip stops
receiving the Loop-Up code. The Remote Loop-Back condition
is removed when the chip receives the Loop-Down code for
more than 5 seconds or if the Automatic Loop-Code detection
mode is terminated.
R/W
0
D6
NLCDE0_n
Network Loop Code Detection Enable Bit 0:
See description of D7 for function of this bit.
R/W
0
NLCDE1
NLCDE0
0
0
0
1
1
0
1
1
Function
Disable Loop-code
detection
Detect Loop-Up code
in receive data
Detect Loop-Down
code in receive data
Automatic Loop-Code
detection
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
56
D5
CODES_n
Encoding and Decoding Select:
Writing a "0" to this bits selects HDB3 or B8ZS encoding and
decoding for channel number n. Writing "1" selects an AMI
coding scheme. This bit is only active when single rail mode is
selected.
R/W
0
D4
RXRES1_n
Receive External Resistor Control Pin 1: In Host mode, this bit
along with the RXRES0_n bit selects the value of the external
Receive fixed resistor according to the following table;
R/W
0
D3
RXRES0_n
Receive External Resistor Control Pin 0: For function of this
bit see description of D4 the RXRES1_n bit.
R/W
0
D2
INSBPV_n
Insert Bipolar Violation: When this bit transitions from "0" to
"1", a bipolar violation is inserted in the transmitted data
stream of the selected channel number n. Bipolar violation can
be inserted either in the QRSS pattern, or input data when
operating in single-rail mode. The state of this bit is sampled
on the rising edge of the respective TCLK_n.
N
OTE
: To ensure the insertion of a bipolar violation, a "0"
should be written in this bit location before writing a
"1".
R/W
0
D1
INSBER_n
Insert Bit Error: With TDQRSS enabled, when this bit transi-
tions from "0" to "1", a bit error will be inserted in the transmit-
ted QRSS pattern of the selected channel number n. The state
of this bit is sampled on the rising edge of the respective
TCLK_n.
N
OTE
: To ensure the insertion of bit error, a "0" should be
written in this bit location before writing a "1".
R/W
0
D0
TRATIO_n
Transformer Ratio Select: In the external termination mode,
writing a "1" to this bit selects a transformer ratio of 1:2 for the
transmitter. Writing a "0" sets the transmitter transformer ratio
to 1:2.45. In the internal termination mode the transmitter
transformer ratio is permanently set to 1:2 and the state of this
bit has no effect.
R/W
0
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
#3, B
IT
D
ESCRIPTION
R XR E S1_n
0
0
R equired Fixed E xternal
R X R esistor
N o external Fixed
R esistor
240
R XR E S0_n
0
1
1
1
210
150
0
1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
57
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
#4, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000100
00010100
00100100
00110100
01000100
01010100
01100100
01110100
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
RO
0
D6
DMOIE_n
DMO Interrupt Enable: Writing a "1" to this bit enables DMO
interrupt generation, writing a "0" masks it.
R/W
0
D5
FLSIE_n
FIFO Limit Status Interrupt Enable: Writing a "1" to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a "0" to masks it.
R/W
0
D4
LCVIE_n
Line Code Violation Interrupt Enable: Writing a "1" to this bit
enables Line Code Violation interrupt generation, writing a "0"
masks it.
R/W
0
D3
NLCDIE_n
Network Loop-Code Detection Interrupt Enable: Writing a
"1" to this bit enables Network Loop-code detection interrupt
generation, writing a "0" masks it.
R/W
0
D2
AISDIE_n
AIS Interrupt Enable: Writing a "1" to this bit enables Alarm
Indication Signal detection interrupt generation, writing a "0"
masks it.
R/W
0
D1
RLOSIE_n
Receive Loss of Signal Interrupt Enable: Writing a "1" to this
bit enables Loss of Receive Signal interrupt generation, writing
a "0" masks it.
R/W
0
D0
QRPDIE_n
QRSS Pattern Detection Interrupt Enable: Writing a "1" to
this bit enables QRSS pattern detection interrupt generation,
writing a "0" masks it.
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
58
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
#5, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000101
00010101
00100101
00110101
01000101
01010101
01100101
01110101
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
RO
0
D6
DMO_n
Driver Monitor Output: This bit is set to a "1" to indicate
transmit driver failure is detected. The value of this bit is based
on the current status of DMO for the corresponding channel. If
the DMOIE bit is enabled, any transition on this bit will gener-
ate an Interrupt.
RO
0
D5
FLS_n
FIFO Limit Status: This bit is set to a "1" to indicate that the jit-
ter attenuator read/write FIFO pointers are within +/- 3 bits. If
the FLSIE bit is enabled, any transition on this bit will generate
an Interrupt.
RO
0
D4
LCV_n
Line Code Violation: This bit is set to a "1" to indicate that the
receiver of channel n is currently detecting a Line Code Viola-
tion or an excessive number of zeros in the B8ZS or HDB3
modes. If the LCVIE bit is enabled, any transition on this bit will
generate an Interrupt.
RO
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
59
D3
NLCD_n
Network Loop-Code Detection:
This bit operates differently in the Manual or the Automatic
Network Loop-Code detection modes.
In the Manual Loop-Code detection mode, (NLCDE1 = "0"
and NLCDE0 = "1" or NLCDE1 = "1" and NLCDE0 = "0") this
bit gets set to "1" as soon as the Loop-Up ("00001") or Loop-
Down ("001") code is detected in the receive data for longer
than 5 seconds. The NLCD bit stays in the "1" state for as long
as the chip detects the presence of the Loop-code in the
receive data and it is reset to "0" as soon as it stops receiving
it. In this mode, if the NLCD interrupt is enabled, the chip will
initiate an interrupt on every transition of the NLCD.
When the Automatic Loop-code detection mode, (NLCDE1
= "1" and NLCDE0 ="1") is initiated, the state of the NLCD
interface bit is reset to "0" and the chip is programmed to mon-
itor the receive input data for the Loop-Up code. This bit is set
to a "1" to indicate that the Network Loop Code is detected for
more than 5 seconds. Simultaneously the Remote Loop-Back
condition is automatically activated and the chip is pro-
grammed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays in the "1" state for as long as
the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up code. Remote Loop-Back is
removed if the chip detects the "001" pattern for longer than 5
seconds in the receive data.Detecting the "001" pattern also
results in resetting the NLCD interface bit and initiating an
interrupt provided the NLCD interrupt enable bit is active.
When programmed in Automatic detection mode, the
NLCD interface bit stays "High" for the entire time the Remote
Loop-Back is active and initiate an interrupt anytime the status
of the NLCD bit changes. In this mode, the Host can monitor
the state of the NLCD bit to determine if the Remote Loop-
Back is activated.
RO
0
D2
AISD_n
Alarm Indication Signal Detect: This bit is set to a "1" to indi-
cate All Ones Signal is detected by the receiver. The value of
this bit is based on the current status of Alarm Indication Signal
detector of channel n. If the AISDIE bit is enabled, any transi-
tion on this bit will generate an Interrupt.
RO
0
D1
RLOS_n
Receive Loss of Signal: This bit is set to a "1" to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal of channel n. If the
RLOSIE bit is enabled, any transition on this bit will generate
an Interrupt.
RO
0
D0
QRPD_n
Quasi-random Pattern Detection: This bit is set to a "1" to
indicate the receiver is currently in synchronization with QRSS
pattern. The value of this bit is based on the current status of
Quasi-random pattern detector of channel n. If the QRPDIE bit
is enabled, any transition on this bit will generate an Interrupt.
RO
0
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
#5, B
IT
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
60
T
ABLE
25: M
ICROPROCESSOR
R
EGISTER
#6, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000110
00010110
00100110
00110110
01000110
01010110
01100110
01110110
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
RO
0
D6
DMOIS_n
Driver Monitor Output Interrupt Status: This bit is set to a
"1" every time the DMO status has changed since last read.
N
OTE
: This bit is reset upon read.
RUR
0
D5
FLSIS_n
FIFO Limit Interrupt Status: This bit is set to a "1" every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) sta-
tus has changed since last read.
N
OTE
: This bit is reset upon read.
RUR
0
D4
LCVIS_n
Line Code Violation Interrupt Status: This bit is set to a "1"
every time when LCV status has changed since last read.
N
OTE
: This bit is reset upon read.
RUR
0
D3
NLCDIS_n
Network Loop-Code Detection Interrupt Status: This bit is
set to a "1" every time when NLCD status has changed since
last read.
N
OTE
: This bit is reset upon read.
RUR
0
D2
AISDIS_n
AIS Detection Interrupt Status: This bit is set to a "1" every
time when AISD status has changed since last read.
N
OTE
: This bit is reset upon read.
RUR
0
D1
RLOSIS_n
Receive Loss of Signal Interrupt Status: This bit is set to a
"1" every time RLOS status has changed since last read.
N
OTE
: This bit is reset upon read.
RUR
0
D0
QRPDIS_n
Quasi-Random Pattern Detection Interrupt Status: This bit
is set to a "1" every time when QRPD status has changed
since last read.
N
OTE
: This bit is reset upon read.
RUR
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
61
T
ABLE
26: M
ICROPROCESSOR
R
EGISTER
#7, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00000111
00010111
00100111
00110111
01000111
01010111
01100111
01110111
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
RO
0
D6
Reserved
RO
0
D5
CLOS5_n
Cable Loss bit 5: CLOS[5:0]_n are the six bit receive selec-
tive equalizer setting which is also a binary word that repre-
sents the cable attenuation indication within ±1dB. CLOS5_n
is the most significant bit (MSB) and CLOS0_n is the least sig-
nificant bit (LSB).
RO
0
D4
CLOS4_n
Cable Loss bit 4: See description of D5 for function of this bit.
RO
0
D3
CLOS3_n
Cable Loss bit 3: See description of D5 for function of this bit.
RO
0
D2
CLOS2_n
Cable Loss bit 2: See description of D5 for function of this bit.
RO
0
D1
CLOS1_n
Cable Loss bit 1: See description of D5 for function of this bit.
RO
0
D0
CLOS0_n
Cable Loss bit 0: See description of D5 for function of this bit.
RO
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
62
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
#8, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001000
00011000
00101000
00111000
01001000
01011000
01101000
01111000
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S1_n -
B0S1_n
Arbitrary Transmit Pulse Shape, Segment 1:The shape of
each channel's transmitted pulse can be made independently
user programmable by selecting "Arbitrary Pulse" mode in
Table 5
. The arbitrary pulse is divided into eight time seg-
ments whose combined duration is equal to one period of
MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the first time segment. B6S1_n-
B0S1_n is in signed magnitude format with B6S1_n as the
sign bit and B0S1_n as the least significant bit (LSB).
R/W
0
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
#9, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001001
00011001
00101001
00111001
01001001
01011001
01101001
01111001
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S2_n -
B0S2_n
Arbitrary Transmit Pulse Shape, Segment 2
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the second time segment. B6S2_n-
B0S2_n is in signed magnitude format with B6S2_n as the
sign bit and B0S2_n as the least significant bit (LSB).
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
63
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
#10, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001010
00011010
00101010
00111010
01001010
01011010
01101010
01111010
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S3_n -
B0S3_n
Arbitrary Transmit Pulse Shape, Segment 3
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the third time segment. B6S3_n-
B0S3_n is in signed magnitude format with B6S3_n as the
sign bit and B0S3_n as the least significant bit (LSB).
R/W
0
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
#11, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001011
00011011
00101011
00111011
01001011
01011011
01101011
01111011
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S4_n -
B0S4_n
Arbitrary Transmit Pulse Shape, Segment 4
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the fourth time segment. B6S4_n-
B0S4_n is in signed magnitude format with B6S4_n as the
sign bit and B0S4_n as the least significant bit (LSB).
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
64
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
#12, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001100
00011100
00101100
00111100
01001100
01011100
01101100
01111100
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S5_n -
B0S5_n
Arbitrary Transmit Pulse Shape, Segment 5
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the fifth time segment. B6S5_n-
B0S5_n is in signed magnitude format with B6S5_n as the
sign bit and B0S5_n as the least significant bit (LSB).
R/W
0
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
#13, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001101
00011101
00101101
00111101
01001101
01011101
01101101
01111101
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S6_n -
B0S6_n
Arbitrary Transmit Pulse Shape, Segment 6
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the sixth time segment. B6S6_n-
B0S6_n is in signed magnitude format with B6S6_n as the
sign bit and B0S6_n as the least significant bit (LSB).
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
65
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
#14, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001110
00011110
00101110
00111110
01001110
01011110
01101110
01111110
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S7_n -
B0S7_n
Arbitrary Transmit Pulse Shape, Segment 7
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the seventh time segment.
B6S7_n-B0S7_n is in signed magnitude format with B6S7_n
as the sign bit and B0S7_n as the least significant bit (LSB).
R/W
0
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
#15, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
00001111
00011111
00101111
00111111
01001111
01011111
01101111
01111111
C
HANNEL
_n
C
HANNEL
_0
C
HANNEL
_1
C
HANNEL
_2
C
HANNEL
_3
C
HANNEL
_4
C
HANNEL
_5
C
HANNEL
_6
C
HANNEL
_7
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
N
AME
D7
Reserved
R/W
0
D6-D0
B6S8_n -
B0S8_n
Arbitrary Transmit Pulse Shape, Segment 8
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in
Table 5
. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the eighth time segment. B6S8_n-
B0S8_n is in signed magnitude format with B6S8_n as the
sign bit and B0S8_n as the least significant bit (LSB).
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
66
T
ABLE
35: M
ICROPROCESSOR
R
EGISTER
#128, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
10000000
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
SR/DR
Single-rail/Dual-rail Select: Writing a "1" to this bit configures
all 8 channels in the XRT83L38 to operate in the Single-rail
mode.
Writing a "0" configures the XRT83L38 to operate in Dual-rail
mode.
R/W
0
D6
ATAOS
Automatic Transmit All Ones Upon RLOS: Writing a "1" to
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.
Writing a "0" disables this feature.
R/W
0
D5
RCLKE
Receive Clock Edge: Writing a "1" to this bit selects receive
output data of all channels to be updated on the negative edge
of RCLK.
Wring a "0" selects data to be updated on the positive edge of
RCLK.
R/W
0
D4
TCLKE
Transmit Clock Edge: Writing a "0" to this bit selects transmit
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.
Writing a "1" selects the rising edge of the TCLK_n for sam-
pling.
R/W
0
D3
DATAP
DATA Polarity: Writing a "0" to this bit selects transmit input
and receive output data of all channels to be active "High".
Writing a "1" selects an active "Low" state.
R/W
0
D2
Reserved
0
D1
GIE
Global Interrupt Enable: Writing a "1" to this bit globally
enables interrupt generation for all channels.
Writing a "0" disables interrupt generation.
R/W
0
D0
SRESET
Software Reset
µ
P Registers: Writing a "1" to this bit longer
than 10µs initiates a device reset through the microprocessor
interface. All internal circuits are placed in the reset state with
this bit set to a "1" except the microprocessor register bits.
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
67
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x81h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, register 0x81h can be broken down into two sub-registers with the MSB being bits
D[7:3] and the LSB being bits D[2:0] as shown in Figure 25. Note: Bit D[7] is a reserved bit.
F
IGURE
25. R
EGISTER
0
X
81
H
S
UB
R
EGISTERS
Programming Examples:
Example 1: Changing bits D[7:3]
If bits D[7:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[2:0]
If bits D[2:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (MSB) and then change bits D[2:0] (LSB) on the SECOND write, or vice-
versa. No order or sequence is necessary.
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
#129, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
10000001
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
Reserved
R/W
0
D0
D1
D2
D3
D4
D5
D6
D7
MSB
LSB
Clock Selection Bits
ExLOS, ICT
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
68
D6
CLKSEL2
Clock Select Inputs for Master Clock Synthesizer bit 2:
In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
R/W
0
D5
CLKSEL1
Clock Select inputs for Master Clock Synthesizer bit 1:
See description of bit D6 for function of this bit.
R/W
0
D4
CLKSEL0
Clock Select inputs for Master Clock Synthesizer bit 0:
See description of bit D6 for function of this bit.
R/W
0
D3
MCLKRATE
Master clock Rate Select: The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = "0", and the T1/J1 clock when MCLKRATE =
"1".
R/W
0
D2
RXMUTE
Receive Output Mute: Writing a "1" to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a "0" state for
any channel that detects an RLOS condition.
N
OTE
: RCLK is not muted.
R/W
0
D1
EXLOS
Extended LOS: Writing a "1" to this bit extends the number of
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a "0" reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
R/W
0
D0
ICT
In-Circuit-Testing: Writing a "1" to this bit configures all the
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to "1" is equivalent to connecting
the Hardware ICT pin 88 to ground.
R/W
0
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
#129, B
IT
D
ESCRIPTION
2048
2048
2048
1544
M C LKE1
kH z
8
16
16
56
8
56
64
64
128
256
256
128
2048
2048
1544
1544
M CLKT1
kH z
1544
X
X
X
1544
X
X
X
X
X
X
X
2048
1544
2048
C LK OUT/
kH z
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
0
1
1
C LK SEL0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
C LK SEL1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
CLKSEL2
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
1544
2048
X
X
2048
1544
0
1
0
1
M C LK RATE
1
0
1
0
0
1
0
1
1
0
1
0
0
1
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
69
T
ABLE
37: M
ICROPROCESSOR
R
EGISTER
#130, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
10000010
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
TXONCNTL
Transmit On Control:
In Host mode, setting this bit to "1" transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.
N
OTE
: This provides a faster On/Off capability for redundancy
application.
R/W
0
D6
TERCNTL
Termination Control.
In Host mode, setting this bit to "1" transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
N
OTE
: This provides a faster On/Off capability for redundancy
application.
R/W
0
D5-D4
Reserved
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
70
D3
MONITOR_3 Protected Monitoring: With protected monitoring enabled,
the receiver 7 inputs at RTIP_7 and RRING_7 are internally
connected to one of the other seven transmit and receive
channels.Receiver 7 recovers the input data and clock and
output them to RPOS_7/RNEG_7 and RCLK_7 respectively. In
addition, the data to be monitored can be routed to TTIP_7 and
TRING_7 by means of activating Remote Loop-Back for chan-
nel 7.
With MONITOR_[3:0] bits set to "0", the Protected Monitoring
feature is disabled and the XRT83L38 is configured as an octal
line transceiver.
Protected Monitoring Channel Select
R/W
0
D2
MONITOR_2 Protected Monitoring:
See description for MONITOR_3
R/W
0
D1
MONITOR_1 Protected Monitoring:
See description for MONITOR_3
R/W
0
D0
MONITOR_0 Protected Monitoring:
See description for MONITOR_3
R/W
0
T
ABLE
37: M
ICROPROCESSOR
R
EGISTER
#130, B
IT
D
ESCRIPTION
Monitor_3
Selection
0
0
0
0
No Monitoring
0
0
0
1
Receiver 0
0
0
1
0
Receiver 1
0
0
1
1
Receiver 2
0
1
0
0
Receiver 3
0
1
0
1
Receiver 4
0
1
1
0
Receiver 5
0
1
1
1
Receiver 6
1
0
0
0
No Monitoring
1
0
0
1
Transmitter 0
1
0
1
0
Transmitter 1
1
0
1
1
Transmitter 2
1
1
0
0
Transmitter 3
1
1
0
1
Transmitter 4
1
1
1
0
Transmitter 5
1
1
1
1
Transmitter 6
Monitor_2 Monitor_1 Monitor_0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
71
T
ABLE
38: M
ICROPROCESSOR
R
EGISTER
#131, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
10000000
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
GAUGE1
Wire Gauge Selector Bit 1:
This bit together with bit D6 are used to select wire gauge size
as shown in the table below.
R/W
0
D6
GAUGE0
Wire Gauge Selector Bit 0:
See bit D7.
R/W
0
D5
Reserved
R/W
0
D4
Reserved
R/W
0
D3
SL_1
Slicer Level Control bit 1: This bit and bit D2 control the slic-
ing level for the slicer per the following table.
R/W
0
D2
SL_0
Slicer Level Control bit 0: See description bit D3.
R/W
0
D1
EQG_1
Equalizer Gain Control bit 1: This bit together with bit D0
control the gain of the equalizer as shown in the table below.
R/W
0
D0
EQG_0
Equalizer Gain Control bit 0: See description of bit D1
R/W
0
GAUGE1
0
1
1
0
GAUGE0
0
1
0
1
Wire Size
22 and 24 Gauge
26 Gauge
24 Gauge
22 Gauge
SL_1
SL_0
0
0
0
1
1
0
1
1
Slicer Mode
Normal
Decrease by 5% from Normal
Increase by 5% from Normal
Normal
EQG_1
EQG_0
0
0
0
1
1
0
1
1
Equalizer Gain
Normal
Reduce Gain by 1 dB
Reduce Gain by 3 dB
Normal
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
72
T
ABLE
39: M
ICROPROCESSOR
R
EGISTER
#192, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
11000000
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D[7:1]
Reserved
These register bits are not used.
R/W
0
D0
E1Arben
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually con-
trolled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
R/W
0
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
73
ELECTRICAL CHARACTERISTICS
T
ABLE
40: A
BSOLUTE
M
AXIMUM
R
ATINGS
Storage Temperature...................-65°C to + 150°C
Operating Temperature.............-40°C to + 85°C
Supply Voltage..........................-0.5V to + 3.8V
V
In
.................................................-0.5V to + 5.5V
T
ABLE
41: DC D
IGITAL
I
NPUT
AND
O
UTPUT
E
LECTRICAL
C
HARACTERISTICS
VDD=3.3V±5%,
T
A
=25°C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
S
YMBOL
M
IN
.
T
YP
.
M
AX
.
U
NITS
Power Supply Voltage
VDD
3.13
3.3
3.46
V
Input High Voltage
V
IH
2.0
-
5.0
V
Input Low Voltage
V
IL
-0.5
-
0.8
V
Output High Voltage @ IOH = 2.0mA
V
OH
2.4
-
-
V
Output Low Voltage @IOL = 2mA.
V
OL
-
-
0.4
V
Input Leakage Current (except Input pins
with Pull-up or Pull- down resistor).
I
L
-
-
±10
µ
A
Input Capacitance
C
I
-
5.0
-
pF
Output Load Capacitance
C
L
-
-
25
pF
T
ABLE
42: XRT83L38 P
OWER
C
ONSUMPTION
VDD=3.3V±5%,
T
A
=25°C,
UNLESS
OTHERWISE
SPECIFIED
M
ODE
S
UPPLY
V
OLTAGE
I
MPEDANCE
TERMINATION
R
ESISTOR
T
RANSFORMER
R
ATIO
T
YP
.
M
AX
.
U
NIT
T
EST
C
ONDITIONS
R
ECEIVER
T
RANSMITTER
E1
3.3V
75
Internal
1:1
1:2
1.96
2.16
W
100% "1's"
E1
3.3V
120
Internal
1:1
1:2
1.85
2.04
W
100% "1's"
T1
3.3V
100
Internal
1:1
1:2
1.95
2.15
W
100% "1's"
---
3.3V
---
External
---
---
429
472
mW
All transmitters off
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
74
T
ABLE
43: E1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
VDD=3.3V±5%,
T
A
= -40°
TO
85°C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NIT
T
EST
C
ONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS De-asserted
10
15
12.5
175
20
255
dB
dB
Cable attenuation @1024kHz
ITU-G.775, ETSI 300 233
Receiver Sensitivity
(Short Haul with cable loss)
11
dB
With nominal pulse amplitude of 3.0V
for 120
and 2.37V for 75
applica-
tion. With -18dB interference signal
added.
Receiver Sensitivity
(Long Haul with cable loss)
Nominal
Extended
0
0
36
43
dB
dB
With nominal pulse amplitude of 3.0V
for 120
and 2.37V for 75
applica-
tion. With -18dB interference signal
added.
Input Impedance
13
k
Input Jitter Tolerance:
1 Hz
10kHz-100kHz
37
0.2
UIpp
UIpp
ITU G.823
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
-
36
-0.5
kHz
dB
ITU G.736
Jitter Attenuator Corner Fre-
quency (-3dB curve) (JABW=0)
(JABW=1)
-
10
1.5
-
Hz
Hz
ITU G.736
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
14
20
16
-
-
dB
dB
dB
ITU-G.703
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
75
T
ABLE
44: T1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
VDD=3.3V±5%,
T
A
=-40°
TO
85°C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NIT
T
EST
C
ONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS Clear
100
15
12.5
175
20
-
250
-
-
dB
% ones
Cable attenuation @772kHz
ITU-G.775, ETSI 300 233
Receiver Sensitivity
(Short Haul with cable loss)
12
-
dB
With nominal pulse amplitude of 3.0V
for 100
termination
Receiver Sensitivity
(Long Haul with cable loss)
0
-
36
dB
With nominal pulse amplitude of 3.0V
for 100
termination
Input Impedance
13
-
k
Jitter Tolerance:
1Hz
10kHz - 100kHz
138
0.4
-
-
-
-
UIpp
AT&T Pub 62411
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
-
-
9.8
-
0.1
KHz
dB
TR-TSY-000499
Jitter Attenuator Corner Fre-
quency
(-3dB curve)
-
6
-Hz
AT&T Pub 62411
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
-
-
-
20
25
25
-
-
-
dB
dB
dB
T
ABLE
45: E1 T
RANSMIT
R
ETURN
L
OSS
R
EQUIREMENT
F
REQUENCY
R
ETURN
L
OSS
G.703/CH-PTT
ETS 300166
51-102kHz
8dB
6dB
102-2048kHz
14dB
8dB
2048-3072kHz
10dB
8dB
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
76
T
ABLE
46: E1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
VDD=3.3V±5%,
T
A
=-40°
TO
85°C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NIT
T
EST
C
ONDITIONS
AMI Output Pulse Amplitude:
75
Application
120
Application
2.185
2.76
2.37
3.00
2.555
3.24
V
V
Transformer with 1:2 ratio and internal
termination.
Output Pulse Width
224
244
264
ns
Output Pulse Width Ratio
0.95
-
1.05
-
ITU-G.703
Output Pulse Amplitude Ratio
0.95
-
1.05
-
ITU-G.703
Jitter Added by the Transmitter Out-
put
-
0.025
0.05
UIpp
Broad Band with jitter free TCLK
applied to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
8
14
10
-
-
-
-
-
-
dB
dB
dB
ETSI 300 166, CHPTT
T
ABLE
47: T1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
VDD=3.3V±5%,
T
A
=-40°
TO
85°C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NIT
T
EST
C
ONDITIONS
AMI Output Pulse Amplitude:
2.5
3.0
3.50
V
Transformer with 1:2 ratio and and
Internal Termination.
Output Pulse Width
338
350
362
ns
ANSI T1.102
Output Pulse Width Imbalance
-
-
20
-
ANSI T1.102
Output Pulse Amplitude Imbalance
-
-
+200
mV
ANSI T1.102
Jitter Added by the Transmitter Out-
put
-
0.025
0.05
UIpp
Broad Band with jitter free TCLK
applied to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
-
-
-
15
15
15
-
-
-
dB
dB
dB
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
77
F
IGURE
26. ITU G.703 P
ULSE
T
EMPLATE
T
ABLE
48: T
RANSMIT
P
ULSE
M
ASK
S
PECIFICATION
Test Load Impedance
75
Resistive (Coax)
120
Resistive (twisted Pair)
Nominal Peak Voltage of a Mark
2.37V
3.0V
Peak voltage of a Space (no Mark)
0 + 0.237V
0 + 0.3V
Nominal Pulse width
244ns
244ns
Ratio of Positive and Negative Pulses Imbalance
0.95 to 1.05
0.95 to 1.05
10%
10%
10%
10%
10%
10%
269 ns
(244 + 25)
194 ns
(244 50)
244 ns
219 ns
(244 25)
488 ns
(244 + 244)
0%
50%
20%
V = 100%
Nominal pulse
Note V corresponds to the nominal peak value.
20%
20%
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
78
F
IGURE
27. DSX-1 P
ULSE
T
EMPLATE
(
NORMALIZED
AMPLITUDE
)
T
ABLE
49: DSX1 I
NTERFACE
I
SOLATED
PULSE
MASK
AND
CORNER
POINTS
M
INIMUM
CURVE
M
AXIMUM
CURVE
T
IME
(UI)
N
ORMALIZED
AMPLITUDE
T
IME
(UI)
N
ORMALIZED
AMPLITUDE
-0.77
-.05V
-0.77
.05V
-0.23
-.05V
-0.39
.05V
-0.23
0.5V
-0.27
.8V
-0.15
0.95V
-0.27
1.15V
0.0
0.95V
-0.12
1.15V
0.15
0.9V
0.0
1.05V
0.23
0.5V
0.27
1.05V
0.23
-0.45V
0.35
-0.07V
0.46
-0.45V
0.93
0.05V
0.66
-0.2V
1.16
0.05V
0.93
-0.05V
1.16
-0.05V
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
79
T
ABLE
50: AC E
LECTRICAL
C
HARACTERISTICS
VDD=3.3V±5%, T
A
=25°C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
S
YMBOL
M
IN
.
T
YP
.
M
AX
.
U
NITS
E1 MCLK Clock Frequency
-
2.048
MHz
T1 MCLK Clock Frequency
-
1.544
MHz
MCLK Clock Duty Cycle
40
-
60
%
MCLK Clock Tolerance
-
±50
-
ppm
TCLK Duty Cycle
T
CDU
30
50
70
%
Transmit Data Setup Time
T
SU
50
-
-
ns
Transmit Data Hold Time
T
HO
30
-
-
ns
TCLK Rise Time(10%/90%)
TCLK
R
-
-
40
ns
TCLK Fall Time(90%/10%)
TCLK
F
-
-
40
ns
RCLK Duty Cycle
R
CDU
45
50
55
%
Receive Data Setup Time
R
SU
150
-
-
ns
Receive Data Hold Time
R
HO
150
-
-
ns
RCLK to Data Delay
RDY
-
-
40
ns
RCLK Rise Time(10% to 90%) with
25pF Loading.
RCLK
R
-
-
40
ns
RCLK Fall Time(90% to 10%) with
25pF Loading.
RCLK
F
40
ns
F
IGURE
28. T
RANSMIT
C
LOCK
AND
I
NPUT
D
ATA
T
IMING
TCLK
R
TCLK
F
TCLK
TPOS/TDATA
or
TNEG
T
SU
T
HO
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
80
MICROPROCESSOR INTERFACE I/O TIMING
I
NTEL
I
NTERFACE
T
IMING
- A
SYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in
Figure 30
and
Figure 32
is described in
Table 51
.
F
IGURE
29. R
ECEIVE
C
LOCK
AND
O
UTPUT
D
ATA
T
IMING
F
IGURE
30. I
NTEL
A
SYNCHRONOUS
P
ROGRAMMED
I/O I
NTERFACE
T
IMING
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
A D D R [6 :0 ]
D A T A [7 :0]
R D _D S
W R _R /W
R D Y _ D T A C K
V alid D ata for R ead ba ck
D ata A v aila ble to W rite In to th e LIU
R E A D O P E R A T IO N
W R IT E O P E R A T IO N
t
0
t
0
t
1
t
3
t
2
t
4
V a lid A ddres s
V alid A d dre s s
t
5
t
5
A LE _A S
C S
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
81
T
ABLE
51: A
SYNCHRONOUS
M
ODE
1 - I
NTEL
8051
AND
80188 I
NTERFACE
T
IMING
S
YMBOL
P
ARAMETER
M
IN
M
AX
U
NITS
t
0
Valid Address to CS Falling Edge
0
-
ns
t
1
CS Falling Edge to RD Assert
20
-
ns
t
2
RD Assert to RDY Assert
-
135
ns
NA
RD Pulse Width (t2)
135
-
ns
t
3
CS Falling Edge to WR Assert
20
-
ns
t
4
WR Assert to RDY Assert
-
135
ns
NA
WR Pulse Width (t2)
135
-
ns
t
5
CS Falling Edge to AS Falling Edge
0
-
ns
Reset pulse width - both Motorola and Intel Operations (see
Figure 32
)
t
9
Reset pulse width
30
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
82
M
OTOROLA
A
SYCHRONOUS
I
NTERFACE
T
IMING
The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS),
Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing
of a Motorola 68000 microprocessor family with up to 16.67 MHz clock frequency. The interface timing is
shown in
Figure 31
and
Figure 32
. The I/O specifications are shown in
Table 52
.
F
IGURE
31. M
OTOROLA
68K A
SYNCHRONOUS
P
ROGRAMMED
I/O I
NTERFACE
T
IMING
T
ABLE
52: A
SYNCHRONOUS
- M
OTOROLA
68K - I
NTERFACE
T
IMING
S
PECIFICATION
S
YMBOL
P
ARAMETER
M
IN
M
AX
U
NITS
t
0
Valid Address to CS Falling Edge
0
-
ns
t
1
CS Falling Edge to DS Assert
20
-
ns
t
2
DS Assert to DTACK Assert
-
135
ns
NA
DS Pulse Width (t2)
135
-
ns
t
3
CS Falling Edge to AS Falling Edge
0
-
ns
Reset pulse width - both Motorola and Intel Operations (see
Figure 32
)
t
9
Reset pulse width
30
F
IGURE
32. M
ICROPROCESSOR
I
NTERFACE
T
IMING
- R
ESET
P
ULSE
W
IDTH
C S
A D D R [6 :0 ]
D A T A [7 :0 ]
R D _ D S
W R _ R /W
R D Y _ D TA C K
V a lid D a ta fo r R e a d b a c k
D a ta A v a ila b le to W rite In to th e L IU
R E A D O P E R A T IO N
W R IT E O P E R A TIO N
t
0
t
0
t
1
t
2
V a lid A d d re ss
V a lid A d d re ss
t
3
t
3
t
1
t
2
A L E _ A S
Reset
t
9
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
83
PACKAGE DIMENSIONS
208 LEAD TQFP
(28 X 28 X 1.4mm)
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.055
0.063
1.40
1.60
A
1
0.002
0.006
0.05
0.15
A
2
0.053
0.057
1.35
1.45
B
0.007
0.011
0.17
0.27
C
0.004
0.008
0.09
0.20
D
1.173
1.189
29.80
30.20
D
1
1.098
1.106
27.90
28.10
e
0.0197 BSC
0.50 BSC
L
0.018
0.030
0.45
0.75
a
0
°
7
°
0
°
7
°
156
105
104
53
1
52
157
208
D
D
1
D
D
1
e
L
C
A
2
A
1
A
Seating
Plane
B
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
84
225 BALL PLASTIC BALL GRID ARRAY (BOTTOM VIEW)
(19.0 X 19.0 X 1.0mm)
1
2
4
3
7
8
6
5
17
16
14
15
1 2
13
11
10
9
18
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
D
D1
D
D1
A1
Featu re / Mark
D2
A
A1
A2
A3
e
b
(A1 corner feature is mfger option)
Seating Plane
SYMBO L
MIN
MAX
M IN
M AX
A
0.049
0.096
1.24
2.45
A1
0.016
0.024
0.40
0.60
A2
0.013
0.024
0.32
0.60
A3
0.020
0.048
0.52
1.22
D
0.740
0.756
18.80
19.20
D1
0.669 BSC
17.00 BSC
D2
0.665
0.669
16.90
17.00
b
0.020
0.028
0.50
0.70
e
0.039 BSC
1.00 BSC
INCHES
M ILLIM ETERS
Note: The control dimension is in millimeter.
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
85
ORDERING INFORMATION
REVISIONS
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT83L38IV
208 Pin TQFP(28 x 28 x 1.4 mm)
-40
°
C to +85
°
C
XRT83L38IB
225 Ball BGA
-40
°
C to +85
°
C
R
EVISION
#
D
ATE
D
ESCRIPTION
A1.0.0 thru
A1.0.5
Advanced versions.
P1.1.0
9/01
Preliminary release with modified register tables.
P1.1.1
Corrected description of RXTSEL pin 83. ...by setting the TERCNTL bit (bit 6) to...
P1.2.0
Added SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated
Microprocessor description table by register number. Moved absolute maximum and DC
electrical characteristics before AC electrical characteristics. Replaced TBD's in electrical
tables. Reformated table of contents.
P1.2.1
Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register
binary bits.
P1.2.2
Renamed FIFO pin to GAUGE, edited definition and edited definition of JASEL[1:0] to
reflect the FIFO size is selected by the jitter attenuator select.
P1.2.3
Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenu-
ator path and FIFO size.
P1.2.4
Corrected pin list, pin 114 was listed as GND and DMO_6. Pin 114 is DMO_6. Revised
JASEL1 and JASEL0 table in pin list to show JABW and FIFO size. Re-redefined bits D3,
D2 and D0 of register 1, in combination these bits set the jitter attenuator path and FIFO
size. Added Jitter attenuator tables in microprocessor register tables. Modified micropro-
cessor descriptions, timing diagrams and electrical characteristics.
P1.2.5
Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT,
replace IMASK bit to a "1" with GIE bit to a "0".
P1.2.6
New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers. Corrected
TXON_n pins to be internally pulled-down.
P1.2.7
5/02
Revised Microprocessor interface timing diagrams and data.
P1.2.8
6/02
Corrected microprocessor timing information and edited Redundancy section.
P1.2.9
7/02
Edited section on RLOS, TGND changed to AGND, RGND changed to ExVCM, T1 LOS
from 45dB to 36dB. Corrected references to transformer ratios of receiver from 2:1 to 1:1
and transmitter 1:2 internal and 1:2.45 external termination.
P1.3.0
8/02
Minor text editing.
P1.3.1
10/02
AGND Changed back to TGND, ExVCM changed back to RGND. Changed RXRES1 and
RXRES0, Required Fixed External Rx Resistor Values, to 4x previous values. Added 225
ball BGA package. Added description of arbitrary pulse and Gap Clock support.
P1.3.2
10/02
Minor edits to block diagram, changed issue date to January, corrected register 67 in table
18, corrected table 37.
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
86
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no
representation that the circuits are free of patent infringement. Charts and schedules contained here in are
only for illustration purposes and may vary depending upon a user's specific application. While the
information in this publication has been carefully checked; no responsibility, however, is assumed for
inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of
injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet March 2004.
P1.3.3
01/03
Swapped the function of µPTS1 and µPTS2. Replaced µProcessor timing diagrams and
timing information, (Figures 29 and 30 -- Tables 50 and 51).
P1.3.4
02/03
Removed EXT_VCM_[0-7] and made them No Connect pins. MCLKT1 changed to pin
K1, TGND_0 changed to pin D3 and D3 made NC. SR_DR moved to pin K4.
P1.3.5
05/03
Added RXON_n to control register 0, bit 5.
P1.3.6
10/03
Added new E1 arbitrary pulse feature. Added descritpions to the global registers.
1.0.0
06/04
Final Release. Fixed the typo RNEG1 Pin Number for the BGA Package to H2.
R
EVISION
#
D
ATE
D
ESCRIPTION
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
87
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