EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
·
(510) 668-7000
·
FAX (510) 668-7017
ST16C550
Rev. 4.30
PLCC Package
UART WITH 16-BYTE FIFO's
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
D5
D6
D7
RCLK
RX
N.C.
TX
CS0
CS1
-CS2
-BAUDOUT
RESET
-OP1
-DTR
-RTS
-OP2
N.C.
INT
-RXRDY
A0
A1
A2
D4
D3
D2
D1
D0
N.
C.
VC
C
-R
I
-C
D
-D
S
R
-C
T
S
XT
AL
1
XT
AL
2
-I
O
W
IOW
GN
D
N.
C.
-I
O
R
IOR
-
DDI
S
-T
XR
D
Y
-A
S
ST16C550CJ44
September 2003
GENERAL DESCRIPTION
The ST16C550 (550) is a universal asynchronous re-
ceiver and transmitter with 16 byte transmit and receive
FIFO. It operates at 2.97 to 5.5 volts. A programmable
baud rate generator can select transmit and receive
clock rates from 50 bps to 1.5 Mbps.
The ST16C550 is an improved version of the NS16C550
UART with higher operating speed and lower access
time. The ST16C550 on board status registers provides
the error conditions, type and status of the transfer
operation being performed. Included is complete MO-
DEM control capability, and a processor interrupt
system that may be software tailored to the user's
requirements. The ST16C550 provides internal loop-
back capability for on board diagnostic testing.
The ST16C550 is available in 40 pin PDIP, 44 pin PLCC,
and 48 pin TQFP packages. It is fabricated in an
advanced CMOS process to achieve low drain power
and high speed requirements.
FEATURES
·
Pin to pin and functionally compatible to the Industry
Standard 16C550
·
2.97 to 5.5 volt operation
·
24MHz clock operation at 5V
·
16MHz clock operation at 3.3V
·
16 byte transmit FIFO
·
16 byte receive FIFO with error flags
·
Full duplex operation
·
Transmit and receive control
·
Four selectable receive FIFO interrupt trigger levels
·
Standard modem interface
·
Compatible with ST16C450
·
Low operating current ( 1.2mA typ.)
ORDERING INFORMATION
Part number
Package
Operating temperature
Device Status
ST16C550CP40
40-Lead PDIP
0° C to + 70° C
Active. See the ST16C550CQ48 for new designs.
ST16C550CJ44
44-Lead PLCC
0° C to + 70° C
Active
ST16C550CQ48
48-Lead TQFP
0° C to + 70° C
Active
ST16C550IP40
40-Lead PDIP
-40° C to + 85° C
Active. See the ST16C550IQ48 for new designs.
ST16C550IJ44
44-Lead PLCC
-40° C to + 85° C
Active
ST16C550IQ48
48-Lead TQFP
-40° C to + 85° C
Active
ST16C550
2
Rev. 4.30
48 Pin TQFP Package
40 Pin DIP Package
Figure 1, PACKAGE DESCRIPTION, ST16C550
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
N.C.
D5
D6
D7
RCLK
N.C.
RX
TX
CS0
CS1
-CS2
-BAUDOUT
N.
C.
XT
A
L
1
XT
A
L
2
-I
OW
IO
W
GN
D
-I
OR
IO
R
N.
C.
-
D
DI
S
-
T
X
RDY
-A
S
N.C.
RESET
-OP1
-DTR
-RTS
-OP2
INT
-RXRDY
A0
A1
A2
N.C.
N.
C.
D4
D3
D2
D1
D0
VC
C
-R
I
-C
D
-D
S
R
-C
T
S
N.
C.
ST16C550CQ48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
RX
TX
CS0
CS1
-CS2
-BAUDOUT
XTAL1
XTAL2
-IOW
IOW
GND
VCC
-RI
-CD
-DSR
-CTS
RESET
-OP1
-DTR
-RTS
-OP2
INT
-RXRDY
A0
A1
A2
-AS
-TXRDY
-DDIS
IOR
-IOR
ST
16
C
5
50
C
P
4
0
ST16C550
3
Rev. 4.30
Figure 2, BLOCK DIAGRAM
D0-D7
-IOR,IOR
-IOW,IOW
RESET
A0-A2
-AS
CS0,CS1
-CS2
INT
-RXRDY
-TXRDY
-DTR,-RTS
-OP1,-OP2
-CTS
-RI
-CD
-DSR
TX
RX
Data bu
s
&
Contr
o
l L
o
gic
Reg
i
st
er
Se
le
c
t
L
ogic
Modem
Control
Logic
In
t
e
rr
u
p
t
Cont
rol
L
ogic
Transmit
FIFO
Registers
Transmit
Shift
Register
Receive
FIFO
Registers
Receive
Shift
Register
In
t
e
r C
o
n
n
ec
t
Bu
s Li
ne
s
&
Contr
o
l s
i
gnals
Clock
&
Baud Rate
Generator
XT
A
L
1
RC
L
K
XT
A
L
2
-
BAUDOU
T
-DDIS
ST16C550
4
Rev. 4.30
Symbol
Pin
Signal
Pin Description
40
44
48
type
SYMBOL DESCRIPTION
A0
28
31
28
I
Address-0 Select Bit Internal registers address selection.
A1
27
30
27
I
Address-1 Select Bit Internal registers address selection.
A2
26
29
26
I
Address-2 Select Bit Internal registers address selection.
IOR
22
25
20
I
Read data strobe. Its function is the same as -IOR (see -
IOR), except it is active high. Either an active -IOR or IOR
is required to transfer data from 16C550 to CPU during a
read operation. Connect to logic 0 when using -IOR.
CS0
12
14
9
I
Chip Select-0. Logical 1 on this pin provides the chip select-
0 function. Connect CS0 to logic 1 if using CS1 or -CS2.
CS1
13
15
10
I
Chip Select-1. Logical 1 on this pin provides the chip select-
1 function. Connect CS1 to logic 1 if using CS0 or -CS2.
-CS2
14
16
11
I
Chip Select -2. Logical 0 on this pin provides the chip select-
2 function. Connect to logic 0 if using CS0 or CS1.
IOW
19
21
17
I
Write data strobe. Its function is the same as -IOW (see -
IOW), but it acts as an active high input signal. Either -IOW
or IOW is required to transfer data from the CPU to
ST16C550 during a write operation. Connect to logic 0 when
using -IOW.
-AS
25
28
24
I
Address Strobe. A logic 1 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0.
D0-D7
1-8
2-9
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, tri-
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
20
22
18
Pwr
Signal and Power Ground.
ST16C550
5
Rev. 4.30
Symbol
Pin
Signal
Pin Description
40
44
48
type
SYMBOL DESCRIPTION
-IOR
21
24
19
I
Read data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the ST16C550 data bus to the CPU.
Connect to logic 1 when using IOR.
-IOW
18
20
16
I
Write data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register. Connect to logic 1 when using IOW.
INT
30
33
30
O
Interrupt Request (active high). Interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
-RXRDY
29
32
29
O
Receive Ready. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO
control register bit-3. When operating in the ST16C450
mode, only DMA mode "0" is allowed. Mode "0" supports
single transfer DMA in which a transfer is made between
CPU bus cycles. Mode "1" supports multi-transfer DMA in
which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode "0" -RXRDY
is low, when there is at least one character in the receiver
FIFO or receive holding register. In DMA mode "1", -RXRDY
is low, when the trigger level or the time-out has been
reached.
-TXRDY
24
27
23
O
Transmit Ready. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO
control register bit-3. When operating in the ST16C450
mode, only DMA mode "0" is allowed. Mode "0" supports
single transfer DMA in which a transfer is made between
CPU bus cycles. Mode "1" supports multi-transfer DMA in
which multiple transfers are made continuously until the
transmit FIFO has been filled.
-BAUDOUT
15
17
12
O
Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
PDF 
ZIP