The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product
for use in life-support devices and/or systems.
Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
1
EDS-103754 Rev D
Preliminary
The SLD2083CZ is a 10 Watt high performance
LDMOS transistor designed for operation to
2700MHz. It is an excellent solution for applica-
tions requiring high linearity and efficiency at a
low cost. The SLD2083CZ is typically used in
the design of driver stages for power amplifiers,
repeaters, and RFID applications. The power
transistor is fabricated using Sirenza's high per-
formance XeMOS II
TM
process.
RF Specifications
Parameter
Description: Test Conditions in Sirenza Evaluation
Board V
DS
= 28.0V, I
DQ
= 125mA, T
Flange
= 25șC
Unit
Min
Typ
Max
Frequency
Frequency of Operation
MHz
-
-
2700
Gain
10 Watt CW, 902MHz-928MHz
dB
17
18
-
Efficiency
Drain Efficiency at 10 Watt CW, 915MHz
%
40
47
-
IRL
Input Return Loss, 10 Watt Output Power, 915MHz
dB
-
-15
-10
Linearity
3
rd
Order IMD at 10 Watt PEP (Two Tone), 915MHz
dBc
-
-28
-26
1dB Compression (P
1dB
), 915MHz
Watt
10
11
-
ACPR=-55dB, IS-95
Watt
1.8
1.6
-
ACPR=-45dB, IS-95
Watt
3.2
3.6
-
Functional Schematic Diagram
SLD2083CZ
10 Watt Discrete LDMOS Device
Ceramic Package
Product Features
Applications
·
10 Watt Output P
1dB
·
Single Polarity Supply Voltage
·
High Gain: 18 dB Typical
·
High Efficiency
·
Advanced, XeMOS II LDMOS
·
Integrated ESD Protection, Class 1A
·
Base Station PA driver
·
Repeater
·
RFID
Product Description
Case Flange = Ground
ESD
Protection
Pb
RoHS Compliant
&
Package
Green
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
2
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
Pin Description
Pin #
Function
Description
1
Gate
Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to main-
tain constant bias current over the operating temperature range. Care must be taken to protect against video
transients that exceed the recommended maximum input power or voltage. .
2
Drain
Transistor RF output and drain bias voltage. Typical voltage is 28V.
Flange
Source, Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the
board for optimum thermal and RF performance. See mounting instructions for recommendation.
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (V
DS
)
35
V
Gate Voltage (V
GS
)
20
V
RF Input Power
+33
dBm
Load Impedance for Continuous Operation
Without Damage
10:1
VSWR
Output Device Channel Temperature
+200
șC
Lead Temperature During Solder Reflow
+270
șC
Operating Temperature Range
-20 to +90
șC
Storage Temperature Range
-40 to +100
șC
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation see
typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
DC Specifications
Parameter
Unit
Min
Typical
Max
g
m
Forward Transconductance @ 125mA I
DQ
mA / V
590
V
GS
Threshold
I
DS
=3mA
Volt
3.8
V
DS
Breakdown
1mA I
DS
current
Volt
65
C
iss
Input Capacitance (Gate to Source) V
GS
=0V, V
DS
=28V
pF
27.5
C
rss
Reverse Capacitance (Gate to Drain) V
GS
=0V, V
DS
=28V
pF
0.81
C
oss
Output Capacitance (Drain to Source) V
GS
=0V, V
DS
=28V
pF
14.65
R
DSon
Drain to Source Resistance, V
GS
=10V, V
DS
=250mV
0.6
Case Flange = Ground
ESD
Protection
Pin Diagram
Pin 1
Pin 2
Quality Specifications
Parameter
Unit
Min
Typical
Max
ESD Rating
Human Body Model
Volts
500
MTTF
85
o
C Leadframe, 200
o
C Channel
Hours
1.2 X 10
6
R
TH
Thermal Resistance (Junction to Case)
șC/W
4
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
3
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
Typical EVB Test Data
Gain, Efficiency vs. Output Power
Freq=915MHz, Temp=25
o
C, V
DS
=28V, I
DQ
=125mA
19.4
19.5
19.6
19.7
19.8
19.9
20
0
2
4
6
8
10
12
14
Output Power (W)
Gain (
d
B
)
0
10
20
30
40
50
60
Ef
f
i
cien
cy (
%
)
Gain
Efficiency
Gain vs. Frequency and Temperature
Pout=10W, V
DS
=28V, I
DQ
=125mA
17.5
18
18.5
19
19.5
20
900
905
910
915
920
925
930
Frequency (MHz)
G
a
in (dB
)
90 Deg C
25 Deg C
-20 Deg C
Two Tone IM3 vs. Output Power
Freq=915/916MHz, Temp=25
o
C, V
DS
=28V, I
DQ
=125mA
-55.0
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
0.0
2.0
4.0
6.0
Average Output Power (W)
IMD3
(dBc
)
902MHz
915MHz
928MHz
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
4
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
To download Gerber files, DXF drawings, a detailed BOM, and
assembly recommendations for the test board with fixture
contact Sirenza applications.
SLD2083CZ EVB Layout and BoM
Description
Part
Res, 10, 1/10W, 1%, 0805
R10
g
Polarized
J1
Inductor Coilcraft 1.6nH 0603
L1
Res, 0.0, 1/16W, 5%, 0603
R2, R4, R6, R7, R9, R11
Cap, 1000 pF, 100V, 10%, 0603
C7, C8
Cap, 0.01 uF, 100V, 5%, 0805
C10, C15
Cap, 0.5 pF, 250V, +/-.1pF, 0603
C11
Cap, 3.6 pF, 250V, +/-.1pF, 0603
C14
Cap, 12 pF, 250V, 1%, 0603
C2
Cap, 15 pF, 250V, 2%, 0603
C1
Cap, 68 pF, 250V, 5%, 0603
C3, C4, C5, C6
Res, 10 Ohm, 0402
R5, R15
CAP 0.22UF 50V CERAMIC X7R 1206
C13, C16
SLD2083CZ
Q1
Evaluation Board Bill of Materials
Impedance Information
(Typical)
Frequency
(MHz)
Input R
(Ohms)
Input X
(Ohms)
Output R
(Ohms)
Output X
(Ohms)
870
0.5
2.0
4.3
1.9
880
0.5
1.9
4.3
2.0
900
0.8
1.8
4.4
2.0
930
0.7
1.7
4.5
2.0
960
0.8
1.4
4.7
2.0
Impedances are circuit impedances as seen
from device at device lead.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
5
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
Package Outline Drawings
Recommended Landing Pads for the RF083 Package
All Dimensions are in inches
Part Number Ordering Information
Part Number
Devices Per Reel
Reel Size
SLD2083CZ
500
7''
TOP VIEW
SIDE VIEW
END VIEW
0.290
0.160
0.160
0.090
0.160
0.140
0.008
DETAIL A
0.200
0.100
0.050
DETAIL A
0.000±0.002
R0.015
Lead Coplanarity
Lead foot to backside
0.000 ± 0.002
Chamferred Lead
is FET Drain
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