Document Outline

• SED1374 TECHNICAL MANUAL
  • Customer Support Information
    • Comprehensive Support Tools
    • Evaluation / Demonstration Board
    • Chip Documentation
    • Software
    • Application Engineering Support
    • Table of Contents
  • SED1374 Embedded Memory Color LCD Controller
    • Description
    • FEATURES
      • Memory Interface
      • CPU Interface
      • Display Support
      • Clock Source
      • Display Modes
      • Power Down Modes
      • General Purpose IO Pins
      • Operating Voltage
      • Package
    • System Block Diagram
  • Hardware Functional Specification
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
      • 1.1 Scope
      • 1.2 Overview Description
    • 2 Features
      • 2.1 Integrated Frame Buffer
      • 2.2 CPU Interface
      • 2.3 Display Support
      • 2.4 Display Modes
      • 2.5 Clock Source
      • 2.6 Miscellaneous
      • 2.7 Package
    • 3 Typical System Implementation Diagrams
      • Figure 31: Typical System Diagram (SH-4 Bus)
      • Figure 32: Typical System Diagram (SH-3 Bus)
      • Figure 33: Typical System Diagram (M68K #1 Bus)
      • Figure 34: Typical System Diagram (M68K #2 Bus)
      • Figure 35: Typical System Diagram (Generic #1 Bus...
      • Figure 36: Typical System Diagram (Generic #2 Bus...
    • 4 Functional Block Diagram
      • Figure 41: System Block Diagram Showing Data Path...
      • 4.1 Functional Block Descriptions
        • 4.1.1 Host Interface
        • 4.1.2 Memory Controller
        • 4.1.3 Sequence Controller
        • 4.1.4 Look-Up Table
        • 4.1.5 LCD Interface
        • 4.1.6 Power Save
    • 5 Pins
      • 5.1 Pinout Diagram
        • Figure 51: Pinout Diagram
      • 5.2 Pin Description
        • Key:
        • 5.2.1 Host Interface
        • 5.2.2 LCD Interface
        • 5.2.3 Clock Input
        • 5.2.4 Miscellaneous
        • 5.2.5 Power Supply
      • 5.3 Summary of Configuration Options
        • Table 51: Summary of Power On/Reset Options
      • 5.4 Host Bus Interface Pin Mapping
        • Table 52: Host Bus Interface Pin Mapping
      • 5.5 LCD Interface Pin Mapping
        • Table 53: LCD Interface Pin Mapping
    • 6 D.C. Characteristics
      • Table 61: Absolute Maximum Ratings
      • Table 62: Recommended Operating Conditions
      • Table 63: Input Specifications
      • Table 64: Output Specifications
    • 7 A.C. Characteristics
      • 7.1 Bus Interface Timing
        • 7.1.1 SH-4 Interface Timing
          • Figure 71: SH-4 Timing
          • Table 71: SH-4 Timing
        • 7.1.2 SH-3 Interface Timing
          • Figure 72: SH-3 Bus Timing
          • Table 72: SH-3 Bus Timing
        • 7.1.3 Motorola M68K #1 Interface Timing
          • Figure 73: M68K #1 Bus Timing (MC68000)
          • Table 73: M68K #1 Bus Timing (MC68000)
        • 7.1.4 Motorola M68K #2 Interface Timing
          • Figure 74: M68K #2 Timing (MC68030)
          • Table 74: M68K #2 Timing (MC68030)
        • 7.1.5 Generic #1 Interface Timing
          • Figure 75: Generic #1 Timing
          • Table 75: Generic #1 Timing
        • 7.1.6 Generic #2 Interface Timing
          • Figure 76: Generic #2 Timing
          • Table 76: Generic #2 Timing
      • 7.2 Clock Input Requirements
        • Figure 77: Clock Input Requirements
        • Table 77: Clock Input Requirements
      • 7.3 Display Interface
        • 7.3.1 Power On/Reset Timing
          • Figure 78: LCD Panel Power On/Reset Timing
        • 7.3.2 Power Down/Up Timing
          • Figure 79: Power Down/Up Timing
          • Table 78: Power Down/Up Timing
        • 7.3.3 Single Monochrome 4-Bit Panel Timing
          • Figure 710: Single Monochrome 4-Bit Panel Timing
          • Figure 711: Single Monochrome 4-Bit Panel A.C. Ti...
        • 7.3.4 Single Monochrome 8-Bit Panel Timing
          • Figure 712: Single Monochrome 8-Bit Panel Timing
          • Figure 713: Single Monochrome 8-Bit Panel A.C. Ti...
        • 7.3.5 Single Color 4-Bit Panel Timing
          • Figure 714: Single Color 4-Bit Panel Timing
          • Figure 715: Single Color 4-Bit Panel A.C. Timing
        • 7.3.6 Single Color 8-Bit Panel Timing (Format 1)
          • Figure 716: Single Color 8-Bit Panel Timing (Form...
          • Figure 717: Single Color 8-Bit Panel A.C. Timing ...
        • 7.3.7 Single Color 8-Bit Panel Timing (Format 2)
          • Figure 718: Single Color 8-Bit Panel Timing (Form...
          • Figure 719: Single Color 8-Bit Panel A.C. Timing ...
        • 7.3.8 Dual Monochrome 8-Bit Panel Timing
          • Figure 720: Dual Monochrome 8-Bit Panel Timing
          • Figure 721: Dual Monochrome 8-Bit Panel A.C. Timi...
        • 7.3.9 Dual Color 8-Bit Panel Timing
          • Figure 722: Dual Color 8-Bit Panel Timing
          • Figure 723: Dual Color 8-Bit Panel A.C. Timing
        • 7.3.10 9/12-Bit TFT/MD-TFD Panel Timing
          • Figure 724: 12-Bit TFT/MD-TFD Panel Timing
          • Figure 725: TFT/MD-TFD A.C. Timing
    • 8 Registers
      • 8.1 Register Mapping
      • 8.2 Register Descriptions
        • Table 81: Panel Data Format
        • Table 82: Gray Shade/Color Mode Selection
        • Table 83: High Performance Selection
        • Table 84: Inverse Video Mode Select Options
        • Table 85: Hardware Power Save/GPIO0 Operation
        • Table 86: Software Power Save Mode Selection
        • Figure 81: Screen-Register Relationship, Split Sc...
        • Table 87: Look-Up Table Access
        • Table 88: Selection of SwivelView Mode
        • Table 89: Selection of PCLK and MCLK in SwivelVie...
    • 9 Frame Rate Calculation
    • 10 Display Data Formats
      • Figure 101: 1/2/4/8 Bit-Per-Pixel Display Data Me...
    • 11 Look-Up Table Architecture
      • Table 111: Look-Up Table Configurations
      • 11.1 Gray Shade Display Modes
        • 2-Level Gray Shade Mode
          • Figure 111: 2-Level Gray-Shade Mode Look-Up Table...
        • 4-Level Gray Shade Mode
          • Figure 112: 4-Level Gray-Shade Mode Look-Up Table...
        • 16-Level Gray Shade Mode
          • Figure 113: 16-Level Gray-Shade Mode Look-Up Tabl...
        • Look-Up Table Bypass Mode
          • Figure 114: Look-Up Table Bypass Mode Architectur...
      • 11.2 Color Display Modes
        • 2-Level Color Mode
          • Figure 115: 2-Level Color Look-Up Table Architect...
        • 4-Level Color Mode
          • Figure 116: 4-Level Color Mode Look-Up Table Arch...
        • 16-Level Color Mode
          • Figure 117: 16-Level Color Mode Look-Up Table Arc...
        • 256-Level Color Mode
          • Figure 118: 256-Level Color Mode Look-Up Table Ar...
    • 12 SwivelView’
      • 12.1 Default SwivelView Mode
        • Figure 121: Relationship Between The Screen Image...
        • 12.1.1 How to Set Up Default SwivelView Mode
      • 12.2 Alternate SwivelView Mode
        • Figure 122: Relationship Between The Screen Image...
        • 12.2.1 How to Set Up Alternate SwivelView Mode
      • 12.3 Comparison Between Default and Alternate Swiv...
        • Table 121: Default and Alternate SwivelView Mode ...
      • 12.4 SwivelView Mode Limitations
    • 13 Power Save Modes
      • Table 131: Power Save Mode Selection
      • 13.1 Software Power Save Mode
        • Table 132: Software Power Save Mode Summary
      • 13.2 Hardware Power Save Mode
        • Table 133: Hardware Power Save Mode Summary
      • 13.3 Power Save Mode Function Summary
        • Table 134: Power Save Mode Function Summary
      • 13.4 Panel Power Up/Down Sequence
        • Figure 131: Panel On/Off Sequence
      • 13.5 Turning Off BCLK Between Accesses
      • 13.6 Clock Requirements
        • Table 135: SED1374 Internal Clock Requirements
    • 14 Mechanical Data
      • Figure 141: Mechanical Drawing QFP14
  • Programming Notes and Examples
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Initialization
      • Table 21: SED1374 Initialization Sequence (Contin...
      • 2.1 Frame Rate Calculation
    • 3 Memory Models
      • 3.1 Display Buffer Location
        • 3.1.1 1 Bit-Per-Pixel (2 Colors/Gray Shades)
          • Figure 31: Pixel Storage for 1 Bpp (2 Colors/Gray...
        • 3.1.2 2 Bit-Per-Pixel (4 Colors/Gray Shades)
          • Figure 32: Pixel Storage for 2 Bpp (4 Colors/Gray...
        • 3.1.3 4 Bit-Per-Pixel (16 Colors/Gray Shades)
          • Figure 33: Pixel Storage for 4 Bpp (16 Colors/Gra...
        • 3.1.4 Eight Bit-Per-Pixel (256 Colors)
          • Figure 34: Pixel Storage for 8 Bpp (256 Colors) i...
    • 4 Look-Up Table (LUT)
      • 4.1 Look-Up Table Registers
        • Table 41: 2 Bpp Banking Scheme
        • Table 42: 4 Bpp Banking Scheme
        • Table 43: 8 Bpp Banking Scheme
      • 4.2 Look-Up Table (LUT) Organization
        • Table 44: Look-Up Table Configurations
        • Color Modes
          • Table 45: Recommended LUT Values for 1 Bpp Color ...
          • Table 46: LUT Values for 2 Bpp Color Mode
          • Table 47: Suggested LUT Values to Simulate VGA De...
          • Table 48: Suggested LUT Values to Simulate VGA De...
        • Gray Shade Modes
          • Table 49: Recommended LUT Values for 1 Bpp Gray S...
          • Table 410: Suggested Values for 2 Bpp Gray Shade
          • Table 411: Suggested LUT Values for 4 Bpp Gray Sh...
    • 5 Advanced Techniques
      • 5.1 Virtual Display
        • Figure 51: Viewport Inside a Virtual Display
        • 5.1.1 Registers
          • Figure 52: Memory Address Offset Register
        • 5.1.2 Examples
      • 5.2 Panning and Scrolling
        • 5.2.1 Registers
          • Figure 53: Screen 1 Start Address Registers
          • Table 51: Number of Pixels Panned Using Start Add...
        • 5.2.2 Examples
      • 5.3 Split Screen
        • Figure 54: 320x240 Single Panel For Split Screen
        • 5.3.1 Registers
          • Figure 55: Screen 1 Vertical Size
          • Figure 56: Screen 2 Start Address Registers
        • 5.3.2 Examples
    • 6 LCD Power Sequencing and Power Save Modes
      • 6.1 LCD Power Sequencing
      • 6.2 Registers
      • 6.3 LCD Enable/Disable
        • Power On/Enable Sequence
        • Power Off/Disable Sequence
    • 7 SwivelView’
      • 7.1 Introduction To SwivelView
      • 7.2 Default SwivelView Mode
        • Figure 71: Relationship Between The Screen Image ...
      • 7.3 Alternate SwivelView Mode
        • Figure 72: Relationship Between The Screen Image ...
      • 7.4 Registers
      • 7.5 Limitations
        • Table 71: Default and Alternate SwivelView Mode C...
      • 7.6 Examples
    • 8 Identifying the SED1374
    • 9 Hardware Abstraction Layer (HAL)
      • 9.1 Introduction
      • 9.2 API for 1374HAL
        • 9.2.1 Initialization
        • 9.2.2 Miscellaneous HAL Support
        • 9.2.3 Advanced HAL Functions
        • 9.2.4 Register / Memory Access
        • 9.2.5 Power Save
        • 9.2.6 Drawing
        • 9.2.7 LUT Manipulation
    • 10 Sample Code
      • 10.1 Introduction
        • 10.1.1 Sample code using the SED1374 HAL API
        • 10.1.2 Sample code without using the SED1374 HAL A...
        • 10.1.3 Header Files
  • SED1374 Register Summary
  • 1374CFG.EXE Configuration Program
    • Table of Contents
    • List of Figures
    • Introduction
    • Program Requirements
      • Installation
      • Usage
    • 1374CFG
      • Figure 1: 1374CFG Window
      • Panel Information
        • Figure 2: Panel Information
      • Miscellaneous Options
        • Figure 3: Miscellaneous Options
      • System
        • Figure 4: System Options
        • Figure 5: ERROR: Frame Rate
        • Figure 6: ERROR: Zero Frame Rate
      • LUT Control
        • Figure 7: LUT Control
      • Open
        • Figure 8: 1374CFG File Open Dialog
        • Figure 9: ERROR: Unable to read HAL
      • Save
        • Figure 10: 1374CFG Save As Dialog
        • Figure 11: ERROR: Unable to read HAL
      • Help
      • Exit
    • Comments
  • 1374SHOW Demonstration Program
    • 1374SHOW
      • SED1374 Supported Evaluation Platforms
      • Installation
      • Usage
      • Program Messages
  • 1374SPLT Display Utility
    • 1374SPLT
      • SED1374 Supported Evaluation Platforms
      • Installation
      • Usage
      • 1374SPLT Example
      • Program Messages
  • 1374VIRT Display Utility
    • 1374VIRT
      • SED1374 Supported Evaluation Platforms
      • Installation
      • Usage
      • 1374VIRT Example
      • Program Messages
  • 1374PLAY Diagnostic Utility
    • 1374PLAY
      • SED1374 Supported Evaluation Platforms
      • Installation
      • Usage
      • 1374PLAY Example
      • Scripting
      • Comments
      • Program Messages
  • 1374BMP Demonstration Program
    • 1374BMP
      • Installation
      • Usage
      • Comments
      • Program Messages
  • 1374PWR Power Save Utility
    • 1374PWR
      • SED1374 Supported Evaluation Platforms
      • Installation
      • Usage
      • Program Messages
  • Windows® CE Display Drivers
    • 1 WINDOWS® CE DISPLAY DRIVERS
      • 1.1 Program Requirements
      • 1.2 Example Driver Build
      • 1.3 Example Installation
      • 1.4 Comments
  • SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User ...
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
      • 1.1 Features
    • 2 Installation and Configuration
      • Table 21: Configuration DIP Switch Settings
      • Table 22: Host Bus Selection
      • Table 23: Jumper Settings
    • 3 LCD Interface Pin Mapping
      • Table 31: LCD Signal Connector (J5) Pinout
    • 4 CPU/Bus Interface Connector Pinouts
      • Table 41: CPU/BUS Connector (H1) Pinout
      • Table 42: CPU/BUS Connector (H2) Pinout
    • 5 Host Bus Interface Pin Mapping
      • Table 51: Host Bus Interface Pin Mapping
    • 6 Technical Description
      • 6.1 ISA Bus Support
        • 6.1.1 Display Adapter Card Support
        • 6.1.2 Expanded Memory Manager
      • 6.2 Non-ISA Bus Support
      • 6.3 Embedded Memory Support
      • 6.4 Decode Logic
      • 6.5 Clock Input Support
      • 6.6 LCD Panel Voltage Setting
      • 6.7 Monochrome LCD Panel Support
      • 6.8 Color Passive LCD Panel Support
      • 6.9 Color TFT/D-TFD LCD Panel Support
      • 6.10 Power Save Modes
      • 6.11 Adjustable LCD Panel Negative Power Supply
      • 6.12 Adjustable LCD Panel Positive Power Supply
      • 6.13 CPU/Bus Interface Header Strips
    • 7 Parts List
    • 8 Schematic Diagrams
      • Figure 81: SED1374B0C Schematic Diagram (1 of 4)
      • Figure 82: SED1374B0C Schematic Diagram (2 of 4)
      • Figure 83: SED1374B0C Schematic Diagram (3 of 4)
      • Figure 84: SED1374B0C Schematic Diagram (4 of 4)
  • Interfacing to the Toshiba MIPS TX3912 Processor
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
      • 1.1 General Description
    • 2 Direct Connection to the Toshiba TX3912
      • 2.1 General Description
        • Figure 21: SED1374 to TX3912 Direct Connection
      • 2.2 Memory Mapping and Aliasing
      • 2.3 SED1374 Configuration and Pin Mapping
        • Table 21: SED1374 Configuration for Direct Connec...
        • Table 22: SED1374 Generic #2 Interface Pin Mappin...
    • 3 System Design Using the ITE IT8368E PC Card Buff...
      • 3.1 Hardware Description
        • Figure 31: SED1374 to TX3912 Connection Using an ...
      • 3.2 IT8368E Configuration
      • 3.3 Memory Mapping and Aliasing
        • Table 31: TX3912 to Unbuffered PC Card Slots Syst...
        • Table 32: TX3912 to PC Card Slots Address Remappi...
      • 3.4 SED1374 Configuration
        • Table 33: SED1374 Configuration Using the IT8368E...
        • Table 34: SED1374 Generic #1 Interface Pin Mappin...
    • 4 Software
    • 5 Technical Support
      • 5.1 EPSON LCD Controllers (SED1374)
      • 5.2 Toshiba MIPS TX3912 Processor
      • 5.3 ITE IT8368E
  • SED1374 Power Consumption
    • 1 SED1374 Power Consumption
      • 1.1 Conditions
        • Table 11: SED1374 Total Power Consumption
    • 2 Summary
  • Interfacing to the Motorola MC68328 �Dragonball� M...
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Interfacing to the MC68328
      • 2.1 The MC68328 System Bus
      • 2.2 Chip-Select Module
    • 3 SED1374 Host Bus Interface
      • 3.1 Bus Interface Modes
        • Table 31: Host Bus Interface Pin Mapping
      • 3.2 Generic #1 Interface Mode
      • 3.3 MC68K #1 Interface Mode
    • 4 MC68328 To SED1374 Interface
      • 4.1 Hardware Description
        • 4.1.1 Using The MC68K #1 Host Bus Interface
          • Figure 41: Typical Implementation of MC68328 to S...
        • 4.1.2 Using The Generic #1 Host Bus Interface
          • Figure 42: Typical Implementation of MC68328 to S...
      • 4.2 SED1374 Hardware Configuration
        • Table 41: Summary of Power-On/Reset Options
        • Table 42: Host Bus Interface Selection
      • 4.3 MC68328 Chip Select Configuration
    • 5 Software
    • 6 References
      • 6.1 Documents
      • 6.2 Document Sources
    • 7 Technical Support
      • 7.1 EPSON LCD Controllers (SED1374)
      • 7.2 Motorola MC68328 Processor
  • Interfacing to the NEC VR4102’ Microprocessor
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Interfacing to the NEC VR4102
      • 2.1 The NEC VR4102 System Bus
        • 2.1.1 Overview
        • 2.1.2 LCD Memory Access Cycles
          • Figure 21: NEC VR4102 Read/Write Cycles
    • 3 SED1374 Host Bus Interface
      • 3.1 Bus Interface Modes
        • Table 31: Host Bus Interface Pin Mapping
      • 3.2 Generic #2 Interface Mode
    • 4 VR4102 to SED1374 Interface
      • 4.1 Hardware Description
        • Figure 41: Typical Implementation of VR4102 to SE...
      • 4.2 SED1374 Hardware Configuration
        • Table 41: Summary of Power-On/Reset Options
        • Table 42: Host Bus Selection
      • 4.3 NEC VR4102 Configuration
    • 5 Software
    • 6 References
      • 6.1 Documents
      • 6.2 Document Sources
    • 7 Technical Support
      • 7.1 Epson LCD Controllers (SED1374)
      • 7.2 NEC Electronics Inc.
  • Interfacing to the PC Card Bus
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Interfacing to the PC Card Bus
      • 2.1 The PC Card System Bus
        • 2.1.1 PC Card Overview
        • 2.1.2 Memory Access Cycles
          • Figure 21: PC Card Read Cycle
          • Figure 22: PC Card Write Cycle
    • 3 SED1374 Bus Interface
      • 3.1 Bus Interface Modes
        • Table 31: Host Bus Interface Pin Mapping
      • 3.2 Generic #1 Interface Mode
    • 4 PC Card to SED1374 Interface
      • 4.1 Hardware Connections
        • Figure 41: Typical Implementation of PC Card to S...
      • 4.2 SED1374 Hardware Configuration
        • Table 41: Summary of Power-On/Reset Options
        • Table 42: Host Bus Interface Selection
      • 4.3 PAL Equations
      • 4.4 Register/Memory Mapping
    • 5 Software
    • 6 References
      • 6.1 Documents
      • 6.2 Document Sources
    • 7 Technical Support
      • 7.1 EPSON LCD Controllers (SED1374)
      • 7.2 PC Card Standard
  • Interfacing to the Motorola MPC821 Microprocessor
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Interfacing to the MPC821
      • 2.1 The MPC8xx System Bus
      • 2.2 MPC821 Bus Overview
        • 2.2.1 Normal (Non-Burst) Bus Transactions
          • Figure 21: Power PC Memory Read Cycle
          • Figure 22: Power PC Memory Write Cycle
        • 2.2.2 Burst Cycles
      • 2.3 Memory Controller Module
        • 2.3.1 General-Purpose Chip Select Module (GPCM)
        • 2.3.2 User-Programmable Machine (UPM)
    • 3 SED1374 Host Bus Interface
      • 3.1 Host Bus Interface Modes
        • Table 31: Host Bus Interface Pin Mapping
      • 3.2 Generic #1 Host Bus Interface Mode
    • 4 MPC821 to SED1374 Interface
      • 4.1 Hardware Description
        • Figure 41: Typical Implementation of MPC821 to SE...
      • 4.2 Hardware Connections
        • Table 41: List of Connections from MPC821ADS to S...
      • 4.3 SED1374 Hardware Configuration
        • Table 42: Configuration Settings
        • Table 43: Host Bus Selection
      • 4.4 MPC821 Chip Select Configuration
      • 4.5 Test Software
    • 5 Software
    • 6 References
      • 6.1 Documents
      • 6.2 Document Sources
    • 7 Technical Support
      • 7.1 EPSON LCD/CRT Controllers (SED1374)
      • 7.2 Motorola MPC821 Processor
  • Interfacing to the Motorola MCF5307 "ColdFire" Mic...
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Interfacing to the MCF5307
      • 2.1 The MCF5307 System Bus
        • 2.1.1 Overview
        • 2.1.2 Normal (Non-Burst) Bus Transactions
          • Figure 21: MCF5307 Memory Read Cycle
          • Figure 22: MCF5307 Memory Write Cycle
        • 2.1.3 Burst Cycles
      • 2.2 Chip-Select Module
    • 3 SED1374 Bus Interface
      • 3.1 Bus Interface Modes
        • Table 31: Host Bus Interface Pin Mapping
      • 3.2 Generic #1 Interface Mode
    • 4 MCF5307 To SED1374 Interface
      • 4.1 Hardware Description
        • Figure 41: Typical Implementation of MCF5307 to S...
      • 4.2 SED1374 Hardware Configuration
        • Table 41: Summary of Power-On/Reset Options
        • Table 42: Host Bus Interface Selection
      • 4.3 MCF5307 Chip Select Configuration
    • 5 Software
    • 6 References
      • 6.1 Documents
      • 6.2 Document Sources
    • 7 Technical Support
      • 7.1 EPSON LCD Controllers (SED1374)
      • 7.2 Motorola MCF5307 Processor
  • Interfacing to the Philips MIPS PR31500/PR31700 Pr...
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
      • 1.1 General Description
    • 2 Direct Connection to the Philips PR31500/PR31700...
      • 2.1 General Description
        • Figure 21: SED1374 to PR31500/PR31700 Direct Conn...
      • 2.2 Memory Mapping and Aliasing
      • 2.3 SED1374 Configuration and Pin Mapping
        • Table 21: SED1374 Configuration for Direct Connec...
        • Table 22: SED1374 Generic #2 Interface Pin Mappin...
    • 3 System Design Using the ITE IT8368E PC Card Buff...
      • 3.1 Hardware Description
        • Figure 31: SED1374 to PR31500/PR31700 Connection ...
      • 3.2 IT8368E Configuration
      • 3.3 Memory Mapping and Aliasing
        • Table 31: PR31500/PR31700 to Unbuffered PC Card S...
        • Table 32: PR31500/PR31700 to PC Card Slots Addres...
      • 3.4 SED1374 Configuration
        • Table 33: SED1374 Configuration Using the IT8368E...
        • Table 34: SED1374 Generic #1 Interface Pin Mappin...
    • 4 Software
    • 5 Technical Support
      • 5.1 EPSON LCD Controllers (SED1374)
      • 5.2 Philips MIPS PR31500/PR31700 Processor
      • 5.3 ITE IT8368E
  • SDU1374/75-TMPR3912/22U CPU Module
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
      • 1.1 General Description
    • 2 SED1374/75 Bus Interface
      • 2.1 Bus Interface Modes
      • 2.2 Generic #2 Interface Mode
    • 3 TMPR3912/22U and SED1374/75 Interface
      • 3.1 Hardware Connections
        • Figure 31: SED1374 to TMPR3912/22U Interface
      • 3.2 Memory Mapping and Aliasing
      • 3.3 SED1374/75 Configuration and Pin Mapping
        • Table 31: SED1374/75 Configuration for Generic #2...
        • Table 32: SED1374/75 Generic #2 Interface Pin Map...
    • 4 CPU Module Description
      • 4.1 Clock Signals
        • 4.1.1 BUSCLK
        • 4.1.2 CLKI
      • 4.2 LCD Connectors
        • 4.2.1 50-pin LCD Module Connector, J3
        • 4.2.2 Standard Epson LCD Connector, J4
      • 4.3 LCD Controller
        • 4.3.1 SED1374 vs. SED1375
        • 4.3.2 LCDPWR Polarity
        • 4.3.3 SED1374\75 Chip Select
  • Interfacing to an 8-bit Processor
    • Table of Contents
    • List of Tables
    • List of Figures
    • 1 Introduction
    • 2 Interfacing to an 8-bit Processor
      • 2.1 The Generic 8-bit Processor System Bus
    • 3 SED1374 Bus Interface
      • 3.1 Host Bus Pin Connection
        • Table 31: Host Bus Interface Pin Mapping
      • 3.2 Generic #2 Interface Mode
    • 4 8-Bit Processor to SED1374 Interface
      • 4.1 Hardware Description
        • Figure 41: Typical Implementation of an 8-bit Pro...
      • 4.2 SED1374 Hardware Configuration
        • Table 41: Configuration Settings
        • Table 42: Host Bus Selection
      • 4.3 Register/Memory Mapping
    • 5 Software
    • 6 References
      • 6.1 Documents
      • 6.2 Document Sources
    • 7 Technical Support
      • 7.1 Epson LCD/CRT Controllers (SED1374)