1
* This specification are subject to be changed without notice.
EM73C63
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
8.11.2000
GENERAL DESCRIPTION
EM73C63 is an advanced single chip CMOS 4-bit micro-controller. It contains 32K-byte ROM, 500-nibble
RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel
function. EM73C63 is also equipped with 5 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection
ports), LCD display (40x16), built-in sound generator.
It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP
operation mode for optimized power saving.
FEATURES
· Operation voltage
: 2.4V to 5.5V.
· Clock source
: Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32KHz,
connect a external resistor) by mask option and high-frequency oscillator is RC
oscillator (connect a external resistor and a capacitor).
External clock and internal clock is available by mask option.
· Oscillation frequency : 480K, 1M, 2M and 4M Hz are both available for high frequency clock by mask option.
· Instruction set
: 107 powerful instructions.
· Instruction cycle time : Up to 2 µs for 4 MHz (high speed clock).
244 µs for 32768 Hz (low speed clock).
· ROM capacity
: 32768 X 8 bits.
· RAM capacity
: 500 X 4 bits.
· Input port
: 1 port (P0.0-P0.3), IDEL/STOP releasing function is available by mask option.(each
input pin has a pull-up and pull-down resistor available by mask option).
· Bidirection port
: 2 ports (P4, P8). P4.0 and SOUND are available by mask option. IDEL/STOP
releasing function for P8(0..3) is available by mask option.
· 12-bit timer/counter
: Two 12-bit timer/counters are programmable for timer, event counter and pulse width
measurement mode.
· Built-in time base counter : 22 stages.
· Subroutine nesting
: Up to 13 levels.
· Interrupt
: External . .. . . . 2 input interrupt sources.
Internal . . . . . . 2 Timer overflow interrupts.
1 Time base interrupt.
· LCD driver
: 40 X 16 dots, 1/16 duty, 1/5 bias with voltage multiplier.
· Sound effect
: Tone generator, random generator and volume control.
· Power saving function: SLOW, IDLE, STOP operation modes.
· Package type
: Chip form 84 pins, PLCC 84 pins.
2
* This specification are subject to be changed without notice.
8.11.2000
EM73C63
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
Symbol
Pin-type
Function
V
D D
Power supply (+)
V
SS
Power supply (-)
RESET
RESET-A
System reset input signal, low active
mask option :
none
pull-up
CLK
OSC-C
RC or external clock source connecting pin for high speed clock source.
LXIN
OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source.
LXOUT
OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source.
P0(0..3)/WAKEUP0..3
INPUT-B
4-bit input port with IDLE/STOP releasing function
mask option :
wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P4.0/SOUND
I/O-O
1-bit bidirection I/O port or inverse sound effect output
mask option :
SOUND enable, push-pull, high current PMOS
SOUND disable, open-drain
SOUND disable, push-pull, high current PMOS
SOUND disable, push-pull, low current PMOS
P4(1..3)
I/O-O
3-bit bidirection I/O port with high current source.
mask option :
open-drain
push-pull, high current PMOS
push-pull, low current PMOS
P8.0(INT1)/WAKEUPA I/O-L
2-bit bidirection I/O port with external interrupt sources input and IDLE
P8.2(INT0)/WAKEUPC
/STOP releasing function
mask option :
wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
P8.1(TRGB)/WAKEUPB I/O-L
2-bit bidirection I/O port with time/counter A,B external input and IDLE
FUNCTION BLOCK DIAGRAM
PIN DESCRIPTIONS
Interrupt
Control
Time
Base
Timer/Counter
(TA,TB)
System Control
Instruction Decoder
Instruction Register
ROM
PC
Data Bus
Reset
Control
Clock
Generator
Timing
Generator
Clock Mode
Control
Data pointer
ACC
ALU
Flag
Z
C
S
Stack pointer
Stack
RAM
HR
LR
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
P4.0/SOUND
P4.1
P4.2
P4.3
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.2(INT0)/WAKEUPC
P8.3(TRGA)/WAKEUPD
RESET
CLK
LXOUT
SOUND GEN.
LCD Driver
Voltage
multiplier
V1~V5
VA
VB
V
EE
COM0~COM15
SOUND
SEG0~SEG39
LXIN
3
* This specification are subject to be changed without notice.
EM73C63
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
8.11.2000
P8.3(TRGA)/WAKEUPD
/STOP releasing function
mask option :
wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
SOUND
Built-in sound effect output
VA, VB, VEE
LCD voltage multiplier connect pins
V1, V2, V3, V4, V5
LCD bias voltage connect pins
COM0~COM15
LCD common output pins
SEG0~SEG39
LCD segment output pins
TEST
Tie Vss as package type, no connecting as COB type.
FUNCTION
DESCRIPTIONS
PROGRAM ROM ( 32K X 8 bits )
32 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 5 kinds of interrupt service routine entry addresses .
3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh,0016h,001Eh,0026h,
002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,
0086h .
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and data region.
address Bank 0 :
Symbol
Pin-type
Function
Bank 6
Bank 7
.
.
.
SCALL, subroutine call entry address
Data table for
[LDAX],[LDAXI]
instruction
Subroutine call entry address
designated by [LCALL a]
instruction
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Reset start address
INT0; interrupt service routine entry address
TRGA
TRGB
TBI
INT1
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h
07FFh
0800h
0FFFh
1000h
1FFFh
Reserved
4
* This specification are subject to be changed without notice.
8.11.2000
EM73C63
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
User's program and fixed data are stored in the program ROM. User's program is executed using the PC value to fetch an
instruction code.
The 32Kx8 bits program ROM can be divided into 8 banks. There are 4Kx8 bits per bank.
The program ROM bank is selected by P3(2..0). The program counter is a 13-bit binary counter. The PC
and P3 are initialized to "0" during reset.
When P3(2..0)=000B, the bank0 and bank1 of program ROM will be selected. P3(2..0)=001B, the bank0 and
bank2 will be selected, and so on.
Address
P3=x000B P3=x001B
P3=x010B
P3=X011B
P3=X100B P3=X101B P3=X110B
0000h
:
:
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
0FFFh
1000h
:
:
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
1FFFh
PROGRAM EXAMPLE:
BANK 0
START:
:
:
:
LDIA
#00H
; set program ROM to bank1
OUTA P3
B
XA1
:
XA :
:
:
LDIA
#01H
; set program ROM to bank2
OUTA P3
B
XB1
:
XB :
:
:
LDIA
#02H
; set program ROM to bank3
OUTA P3
B
XC1
:
XC :
:
:
B
XD
XD :
:
:
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 1
XA1 :
:
:
B
XA
:
XA2 :
:
5
* This specification are subject to be changed without notice.
EM73C63
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
8.11.2000
B
XA2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 2
XB1 :
:
:
B
XB
:
XB2 :
:
B
XB2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 3
XC1 :
:
:
B
XC
:
XC2 :
:
B
XC2
Fixed data can be read out by table-look-up instruction. Table-look-up instruction requires the Data point (DP)
to indicate the ROM address in obtaining the ROM code data (Except bank0) :
LDAX
Acc
ROM[DP]
L
LDAXI
Acc
ROM[DP]
H
,DP+1
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM", "STADPH",
then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble data by instruction
"LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL
; [DP]
L
07h
STADPM
; [DP]
M
07h
STADPH
; [DP]
H
07h, Load DP=777h
:
OUT #00H, P3 ; Set in bank 1
LDL #00h;
LDH #03h;
LDAX
; ACC
6h
STAMI
; RAM[30]
6h
LDAXI
; ACC
5h
STAM
; RAM[31]
5h
;
ORG 1777h
DATA 56h;
DATA RAM ( 500-nibble )
A total 500 - nibble data RAM is available from address 000 to 1FFh
Data RAM includes the zero page region, stacks and data areas.
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