ChipFind - Datasheet

Part Number EM73A83

Download:  PDF   ZIP
1
* This specification are subject to be changed without notice.
EM73A83
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
10.31.2000
Prelim
inary
GENERAL DESCRIPTION
EM73A83 is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 500-nibble
RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel
function. EM73A83 also equipped with 6 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection
ports), LCD display (40x16), built-in sound generator and speech synthesizer.
It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP
operation mode for optimized power saving.
FEATURES
· Operation voltage
: 2.2V to 4.8V.
· Clock source
: Dual clock system. Low-frequency oscillator is 32 KHz Crystal oscillator or RC
oscillator by mask option and high-frequency oscillator is a built-in internal
oscillator (4.6 MHz).
· Instruction set
: 107 powerful instructions.
· Instruction cycle time
: 1.7µs for 4.6M Hz (high speed clock).
244µs for 32768 Hz (low speed clock).
· ROM capacity
: 16K x 8 bits.
· RAM capacity
: 500 x 4 bits.
· Input port
: 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option.
(each input pin has a pull-up and pull-down resistor available by mask option).
· Bidrection port
: 2 ports (P4, P8). IDLE/STOP release function for P8(0..3) is available by mask
option.
· Built-in watch-dog-timer counter : It is available by mask option.
· 12-bit timer/counter
: Two 12-bit timer/counters are programmable for timer, event counter and pulse
width measurement mode.
· Built-in time base counter : 22 stages.
· Subroutine nesting
: Up to 13 levels.
· Interrupt
: External interrupt . . . . . . 2 input interrupt sources.
Internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt.
1 speech interrupt.
· LCD driver
: 40x16 dots, 1/16 duty, 1/5 bias with voltage multiplier.
· Sound effect
: Tone generator and random generator.
· Speech synthesizer
: 160K speech data ROM (use as 160K nibbles data ROM).
· Power saving function
: SLOW, IDLE, STOP operation modes.
· Package type
: Chip form 85 pins.
2
* This specification are subject to be changed without notice.
10.31.2000
EM73A83
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
Symbol
Pin-type
Function
V
DD,
V
DD2
Power supply (+)
V
SS
Power supply (-)
RESET
RESET-A
System reset input signal, low active
mask option :
none
pull-up
CLK
OSC-G
Capacitor connecting pin for internal high frequency oscillator.
LXIN
OSC-B/OSC-H Crystal/Resistor connecting pin for low speed clock source.
LXOUT
OSC-B
Crystal connecting pin for low speed clock source.
P0(0..3)/WAKEUP0..3
INPUT-B
4-bit input port with IDLE/STOP releasing function
mask option :
wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P4(0..3)
I/O-O
4-bit bidirection I/O port with high current source.
mask option :
open-drain
push-pull, high current PMOS
push-pull, low current PMOS
P8.0(INT1)/WAKEUPA
I/O-L
2-bit bidirection I/O port with external interrupt sources input and IDLE
P8.2(INT0)/WAKEUPC
/STOP releasing function
mask option :
wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
P8.1(TRGB)/WAKEUPB I/O-L
2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD
/STOP releasing function
FUNCTION BLOCK DIAGRAM
PIN DESCRIPTIONS
Interrupt
Control
Time
Base
Timer/Counter
(TA,TB)
System Control
Instruction Decoder
Instruction Register
ROM
PC
Data Bus
Reset
Control
Clock
Generator
Timing
Generator
Clock Mode
Control
Data pointer
ACC
ALU
Flag
Z
C
S
Stack pointer
Stack
RAM
HR
LR
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
P4.0
P4.1
P4.2
P4.3
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.2(INT0)/WAKEUPC
P8.3(TRGA)/WAKEUPD
RESET
CLK
LXOUT
Speech
synthesizer
LCD Driver
V1~V5
VA,VB
COM0~COM15
BZ1
BZ2
SEG0~SEG39
LXIN
3
* This specification are subject to be changed without notice.
EM73A83
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
10.31.2000
Prelim
inary
Symbol
Pin-type
Function
mask option :
wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
BZ1, BZ2
Speech output pins
V1, V2, V3, V4, V5,
LCD bias pins
VA, VB
COM0~COM15
LCD common output pins
SEG0~SEG39
LCD segment output pins
TEST
Tie Vss as package type, no connecting as COB type.
.
.
.
SCALL, subroutine call entry address
Data table for
[LDAX],[LDAXI]
instruction
Subroutine call entry address
designated by [LCALL a]
instruction
Bank 1
Bank 2
Bank 3
Reset start address
INT0 ; interrupt service routine entry address
TRGA
TRGB
TBI
INT1
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h
07FFh
0800h
0FFFh
1000h
1FFFh
SPI
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 16K X 8 bits )
16 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,0086h.
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
address Bank 0 :
4
* This specification are subject to be changed without notice.
10.31.2000
EM73A83
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Prelim
inary
User's program and fixed data are stored in the program ROM. User's program is executed using the PC value
to fetch an instruction code.
The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank.
The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC
and P3 are initialized to "0" during reset.
When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and
bank2 will be selected.
Address
P3=xx00B
P3=xx01B
P3=xx10B
0000h
:
:
Bank0
Bank0
Bank0
0FFFh
1000h
:
:
Bank1
Bank2
Bank3
1FFFh
PROGRAM EXAMPLE :
BANK 0
START:
:
:
:
LDIA
#00H
; set program ROM to bank1
OUTA P3
B
XA1
:
XA :
:
:
LDIA
#01H
; set program ROM to bank2
OUTA P3
B
XB1
:
XB :
:
:
LDIA
#02H
; set program ROM to bank3
OUTA P3
B
XC1
:
XC :
:
:
B
XD
XD :
:
:
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 1
XA1 :
:
:
B
XA
:
XA2 :
:
5
* This specification are subject to be changed without notice.
EM73A83
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
10.31.2000
Prelim
inary
B
XA2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 2
XB1 :
:
:
B
XB
:
XB2 :
:
B
XB2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 3
XC1 :
:
:
B
XC
:
XC2 :
:
B
XC2
Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point
(DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) :
LDAX
Acc
ROM[DP]
L
LDAXI
Acc
ROM[DP]
H
,DP+1
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI"
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]
L
07h
STADPM ; [DP]
M
07h
STADPH
; [DP]
H
07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX
; ACC
6h
STAMI
; RAM[30]
6h
LDAXI
; ACC
5h
STAM
; RAM[31]
5h
;
ORG 1777h
DATA 56h;
DATA RAM ( 500-nibble )
A total 500 - nibble data RAM is available from address 000 to 1FFh
Data RAM includes the zero page region, stacks and data areas.