1
* This specification are subject to be changed without notice.
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
12.29.1999
GENERAL DESCRIPTION
EM73866 is an advanced single chip CMOS 4-bit micro-controller. It contains 8K-byte ROM, 500-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73866 also contains 6 interrupt sources, 2 input port, 7 bidirection ports, Max LCD display (32x4), built-in
watch-dog-timer and high speed Timer/Counter.
EM73866 has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.
FEATURES
Operation voltage
: 2.2V ~ 6V.
Clock source
: Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz,
connect an external resistor) by mask option and high-frequency oscillator is RC
(Connect an external resistor) or Crystall oscillator.
Instruction set
: 107 powerful instructions.
Instruction cycle time : Up to 2us for 4 MHz (high speed clock).
244 µs for 32768 Hz (low speed clock).
122 µs for 32768 Hz (low speed clock with frequency Double)
ROM capacity
: 8192 X 8 bits.
RAM capacity
: 500 X 4 bits.
Input port
: 2 ports (P0, P2), P0(0..3), P2 (0..3), IDLE/STOP releasing function are available
by mask option.
Bidirection port
: 7 ports (P1, P3, P4, P5, P6, P7, P8). P4.1 is shared with HTC external input.
IDLE/STOP releasing function are available by mask option for P8(0..3).
12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width
measurement.
Built-in watch-dog-timer : It is available by mask option.
Built-in time base counter : 22 stages.
Built-in high Speed Timer/Counter : Could be timer, melody out or pulse width measurement.
Subrountine nesting : Up to 13 levels.
Interrupt
: External . . . . . 2 input interrupt sources.
Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt.
1 high speed counter overflow interrupt.
LCD driver
: Max 32 X 4 dots, 1/4, 1/3, 1/2 static four kinds of duty selectable, 1/2 or 1/3 bias choice
and dynamic resistor available.
Power saving function :SLOW, IDLE, STOP operation mode.
Package type
: Chip form 76 pins.
APPLICATIONS
EM73866 is suitable for application in family applicance, consumer products, hand held games, calculator and
the toy controller.
2
* This specification are subject to be changed without notice.
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
12.29.1999
Symbol
Pin-type
Function
V
DD
Power supply (+)
V
SS
Power supply (-)
RESET
RESET-A
System reset input signal, low active
mask option : none
pull-up
XIN/RC
OSC
OSC-A/OSC-H1 Crystal/RC clock source connecting pin
XOUT
OSC-A
Crystal connecting pin
LXIN
OSC-B/OSC-H2 Crystal/RC connecting pin for low speed clock source
LXOUT
OSC-B
Crystal connecting pin for low speed clock source
P0(0..3)/WAKEUP(0..3)
INPUT-K
8-bit input pins with IDLE/STOP releasing function
P2(0..3)/WAKEUP(4..7)
mask option : wakeup enable, negative edge release, pull-up
wakeup enable, negative edge release, none
wakeup enable, positive edge release, pull-down
wakeup enable, positive edge release, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P1(0..1)
I/O-Z
2-bit bidirection I/O pins with high current function source
mask option 1: initial low
initial high
mask option 2: low current push-pull
normal current push-pull
high current push-pull
NMOS open-drain
PMOS open-drain
FUNCTION BLOCK DIAGRAM
PIN DESCRIPTIONS
Interrupt
Control
Time
Base
Timer/Counter
(TA,TB)
System Control
Instruction Decoder
Instruction Register
ROM
PC
Data Bus
Reset
Control
Clock
Generator
Timing
Generator
Sleep Mode
Control
Data pointer
ACC
ALU
Flag
Z
C
S
Stack pointer
Stack
RAM
HR
LR
I/O Control
RESET
XIN
XOUT
Clock
Generator
(slow)
LXOUT LXIN
LCD
V
RLC
COM0~COM3
SEG0~SEG29
V1
V2
V3
TEST
VSS
VDD
P1.0 - P1.1
P3.0 - P3.3
P6.0 - P6.1
W
AKEUP
A,C
/WAKEUPD
P0(0..3)/WAKEUP(0..3)
P2(0..3)/WAKEUP(4..7)
P4(0..3)
P5(0..3)
P7.0
/WAKEUP(P8..11)
/WAKEUP(P12..15)
P8(0,2)(INT1,0)/
3
* This specification are subject to be changed without notice.
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
12.29.1999
Symbol
Pin-type
Function
P3(0,1)/SEG(30,31)
I/O-O
2-bit bidirection I/O pins are shared with LCD segment pin
mask option : segment pin
low current push-pull
normal current push-pull
open-drain
P3(2,3), P6(0,1)
I/O-N
4-bit bidirection I/O pins
mask option : low current push-pull
normal current push-pull
open-drain
P4.0/SOUND/WAKEUP8 I/O-R1
1-bit bidirection I/O with inverse sound output and IDLE/STOP
releasing function.
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, high current push-pull
wakeup disable, open-drain
wakeup disable, SOUND
wakup enable, low current push-pull
wakeup enable, normal current push-pull
P4.1(TRGH)/WAKEUP9 I/O-R1
1-bit bidirection I/O with HTC output and IDLE/STOP releasing
function.
mask option : wakeup disble, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, high current push-pull
wakeup disable, NMOS open-drain
wakeup disable, PMOS open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
P4(2,3)/WAKEUP(10,11) I/O-R1
2-bit bidirection I/O pins with IDLE/STOP releasing function
mask option : wakeup disble, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, high current push-pull
wakeup disable, NMOS open-drain
wakeup disable, PMOS open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
P5(0..3)/WAKEUP(12..15) I/O-S
4-bit bidirection I/O pins with IDLE/STOP releasing function
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
P7.0/TRGA/WAKEUPD I/O-S
2-bit bidirection I/O pins with timer/counterA, B external intput and
P8.1/TRGB/WAKEUPB
IDLE/STOP releasing function
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
PIN DESCRIPTIONS
4
* This specification are subject to be changed without notice.
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
12.29.1999
PIN DESCRIPTIONS
Symbol
Pin-type
Function
P8.0(INT1)/WAKEUPA I/O-S
2-bit bidirection I/O pins with interrupt 0, 1 external intput and
P8.2(INT0)/WAKEUPC
IDLE/STOP releasing function
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
COM(0..3)
--
LCD common pins
SEG(0..29)
--
LCD segment pins
V1, V2, V3, V
RLC
--
LCD bias pins
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 8K X 8 bits )
8 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h.
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
5
* This specification are subject to be changed without notice.
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
12.29.1999
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]
L
07h
STADPM ; [DP]
M
07h
STADPH
; [DP]
H
07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX
; ACC
6h
STAMI
; RAM[30]
6h
LDAXI
; ACC
5h
STAM
; RAM[31]
5h
;
ORG 1777h
DATA 56h;
DATA RAM ( 500-nibble )
A total 500-nibble data RAM is available from address 000 to 1FFh. DATA RAM includes the zero page region,
stacks and data areas.
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI"
.
.
.
SCALL, subroutine call entry address
Data table for
[LDAX],[LDAXI]
instruction
Subroutine call entry address
designated by [LCALL a]
instruction
Reset start address
address
8192 x 8 bits
INT0 ; External interrupt service routine entry address
HTCI; High speed counter interrupt service routine entry address
TRGA; Timer/counterA interrupt serice routine entry address
TRGB; Timer/counterA interrupt serice routine entry address
TBI; Time base interrupt serice routine entry address
INT1; External interrupt serice routine entry address
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h
07FFh
0800h
0FFFh
1000h
1FFFh
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