1
* This specification are subject to be changed without notice.
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
1.5.2001
Prelim
inary
GENERAL DESCRIPTION
EM73461A is an advanced single chip CMOS 4-bit micro-controller. It contains 4K-byte ROM, 244-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73461A also contains 6 interrupt sources, 1 input port, 2 bidirection ports, LCD display (32x4), and one high
speed timer/counter with melody output.
EM73461A has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.
FEATURES
· Operation voltage
: 2.4V to 3.6V.
· Clock source
: Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz,
connect an external resistor) by mask option and high-frequency oscillator is RC
oscillator (connect an external resistor).
· Instruction set
: 109 powerful instructions.
· Instruction cycle time : Up to 2us for 4 MHz (high speed clock).
122 µs or 244µs by frequency double mask option for 32768 Hz (low speed clock).
· ROM capacity
: 4096 X 8 bits.
· RAM capacity
: 244 X 4 bits.
· Input port
: 1 port (P0). P0(0..3) and IDLE releasing function are available by mask option.
· Bidirection port
: 2 ports (P4, P8). P4.0 and SOUND is available by mask option. P4.1 is shared with
HTC external input. P8(0..3) and IDLE releasing function are available by mask
option.
· 12-bit timer/counter
: Two 12-bit timer/counters are programmable for timer, event counter and pulse width
measurement.
· High speed timer/counter : One 8-bit high speed timer/counters is programmable for auto load timer, melody
output and pulse width measurement.
· Built-in time base counter : 22 stages.
· Subroutine nesting
: Up to 13 levels.
· Interrupt
: External . . . . . 2 input interrupt sources.
Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt.
1 high speed timer overflow interrupt.
· LCD driver
: 32 X 4 dots, 1/4,1/3,1/2 static six kinds of duty selectable, 1/2 bias, 1/3 bias.
· Power saving function : SLOW, IDLE, STOP operation mode.
· Package type
: Chip form
61 pins.
APPLICATIONS
EM73461A is suitable for application in family applicance, consumer products, hand held games and the toy
controller.
2
* This specification are subject to be changed without notice.
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
1.5.2001
Prelim
inary
FUNCTION BLOCK DIAGRAM
Symbol
Pin-type
Function
V
D D
Power supply (+)
V
SS
Power supply (-)
RESET
RESET-A
System reset input signal, low active
mask option :
none
pull-up
CLK
OSC-I
RC clock source connecting pin
LXIN
OSC-B/OSC-H1 Crystal/RC connecting pin for low speed clock source
LXOUT
OSC-B
Crystal connecting pin for low speed clock source
P0(0..3)/WAKEUP0..3
INPUT-K
4-bit input port with IDLE releasing function
mask option :
wakeup enable, negative edge release, pull-up
wakeup enable, negative edge release, none
wakeup enable, positive edge release, pull-down
wakeup enable, positive edge release, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P4.0/SOUND
I/O-R
1-bit bidirection I/O port or inverse sound effect output
mask option :
SOUND enable, high current push-pull
SOUND disable, open-drain
PIN DESCRIPTIONS
Interrupt
Control
Time
Base
Timer/Counter
(TA,TB)
System Control
Instruction Decoder
Instruction Register
ROM
PC
Data Bus
Reset
Control
Clock
Generator
Timing
Generator
Sleep Mode
Control
Data pointer
ACC
ALU
Flag
Z
C
S
G
Stack pointer
Stack
ROM
HR
LR
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
P4.0/SOUND
P4.1TRGH
P4.2
P4.3
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.2(INT0)/WAKEUPC
P8.3(TRGA)/WAKEUPD
RESET
CLK
Clock
Generator
(slow)
LXOUT LXIN
HTC
DP
SP
LCD
VA
VB
V1
V2
V3
COM0~COM3
SOUND
SEG0~SEG31
3
* This specification are subject to be changed without notice.
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
1.5.2001
Prelim
inary
Symbol
Pin-type
Function
SOUND disable, low current push-pull
SOUND disable, normal current push-pull
SOUND disable, high current push-pull
P4.1/TRGH
I/O-Q
1-bit bidirection I/O port with HTC external input
mask option :
NMOS open-drain
PMOS open-drain
low current push-pull
normal current push-pull
high current push-pull
P4(2,3)
I/O-Q
2-bit bidirection I/O port with high current source
mask option :
NMOS open-drain
PMOS open-drain
low current push-pull
normal current push-pull
high current push-pull
P8.0(INT1)/WAKEUPA, I/O-S
2-bit bidirection I/O port with external interrupt source input and IDLE
P8.2(INT0)/WAKEUPC
releasing function
mask option :
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
wakeup disable, open-drain
wakeup disable, low current push-pull
wakeup disable, normal current push-pull
P8.1(TRGB)/WAKEUPB I/O-S
2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD
releasing function
mask option :
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
wakeup disable, open-drain
wakeup disable, low current push-pull
wakeup disable, normal current push-pull
SOUND
Melody output
VA,VB, V1, V2, V3
Connect the capacitors for LCD bias voltage
COM0~COM3
LCD common output pins
SEG0~SEG31
LCD segment output pins
TEST
Tie Vss as package type, no connecting as COB type.
PIN DESCRIPTIONS
FUNCTION DESCRIPTIONS
PROGRAM ROM (4K X 8 bits)
4 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of program ROM can be divided into 5 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h.
4. Address 000h - 7FFh : LCALL subroutine entry address.
5. Address 000h - FFFh : Except used as above function, the other region can be used as user's program region.
4
* This specification are subject to be changed without notice.
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
1.5.2001
Prelim
inary
address 4096 x 8 bits
000h
Reset start address
002h
INT0; External interrupt service routine entry address
004h
HTCI; High speed timer interrupt service entry address
006h
TRGA; Timer/counterA interrupt service routine entry address
008h
TRGB; Timer/counter B interrupt service routine entry address
00Ah
TBI; Time base interrupt service routine entry address
00Ch
INT1; External interrupt service routine entry address
00Eh
086h
FFFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by two ways.
(1) Table-look-up instruction :
Table -look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the
ROM code data.
LDAX
Acc
ROM[DP]
L
LDAXI
Acc
ROM[DP]
H
,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code
.
.
.
.
.
.
SCALL, subroutine call entry address
data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can
get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL
; DP3-0
07h
STADPM
; DP5-4
07h
STADPH
; DP8-6
07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX
; ACC
6h
STAMI
; RAM[30]
6h
LDAXI
; ACC
5h
STAM
; RAM[31]
5h
;
ORG 777h
DATA 56h;
:
DATA RAM ( 244-nibble )
There is total 244 - nibble data RAM from address 00 to F3h
Data RAM includes 3 parts: zero page region, stacks and data area.
5
* This specification are subject to be changed without notice.
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
1.5.2001
Prelim
inary
LCD display RAM:
RAM address from 20h ~ 3Fh are the LCD display RAM area, the RAM data of this region can't be operated
by instruction LDHL xx and EXHL.
ZERO-PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03]
07h
CLR 0Eh,2 ; RAM[0Eh]
2
0
STACK:
There are 13-level (maximum) stack for user using for subroutine (including interrupt and CALL). User can
assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example:
LDAM ; Acc
RAM[HL]
STAM ; RAM[HL]
Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
level 0
level 4
level 8
level C
level 1
level 5
level 9
level 2
level 6
level A
level 3
level17
level B
B0h ~ BFh
C0h ~ CFh
D0h ~ DFh
E0h ~ EFh
F0h ~ F3h
Address
00h~0Fh
10h~1Fh
20h~2Fh
30h~3Fh
40h~4Fh
:
zero page
LCD display RAM
Increment
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