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Part Number EM73201

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1
* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
7.20.1999
GENERAL DESCRIPTION
EM73201 is an advanced single chip CMOS 4-bit micro-controller. It contains 2K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, one 12-bit timer/counter for the kernel function.
EM73201 also contains 5 interrupt sources, 4 I/O ports (including 1 input port, 1 output port for LED driving,
2 bidirection I/O ports) built-in watch-dog-time counter and one high frequency clock output for modulating
infrared signal.
Except low-power consumption and high speed, EM73201 also have a sleep and hold mode operation for the
power saving function.
EM73201 is suitable for application in family appliance, consumer products and toy controller.
FEATURES
Operation voltage
: 2.4V to 6.0V (clock frequency: 32 KHz to 5 MHz)
Clock source
: Single clock system for RC , Crystal and external clock source, available by
mask option.
Instruction set
: 109 powerful instructions.
Instruction cycle time
: Up to 2µs for 4.19MHz .
ROM capacity
: 2048 x 8 bits.
RAM capacity
: 52 x 4 bits.
Input port
: 1 port (P0).
Output port
: 1 port (P1).
Bidirection I/O port
: 2 ports (P7,P8).
12-bit timer/counter
: One 12-bit timer/counter is programmable for timer, even counter and pulse
width measurement mode.
Built-in time base counter : 22 stages.
Subroutine nesting
: Up to 13 levels.
Interrupt
: External interrupt . . . . . . 2 input interrupt sources.
Internal interrupt . . . . . . 1 timer overflow interrupt,
1 time base interrupt.
The built-in watch-dog-timer counter is available by mask option.
Low voltage reset is available by mask option.
High frequency clockout: Programmable high frequency clock output for modulating infrared signal.
Power saving function
: Sleep mode and Hold mode.
Package type
: EM73201H
Chip form 22 pins.
EM73201AP
DIP
18 pins.
EM73201BK
SKINNY 22 pins.
EM73201CP
DIP
16 pins.
APPLICATIONS
EM73201 is suitable for application in family appliance, consumer products and the toy controller.
2
* This specification are subject to be changed without notice.
7.20.1999
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P8.3
P7.0
P7.1
P7.2
P7.3
P1.0
P1.1
P1.2
V
SS
V
DD
P8.2
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
EM73201AP
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
P8.0
P8.3
P7.0
P7.1
P7.2
P7.3
P1.0
P1.1
P1.2
P1.3
V
SS
V
DD
P8.2
RESET
P8.1
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
EM73201BK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
P7.0
P7.2
P7.3
P1.0
P1.1
P1.2
V
SS
RESET
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
EM73201CP
EM73201AP must enable low voltage reset
Interrupt
Control
Time
Base
12 bits
timer
counter
System Control
Instruction Decoder
Instruction Register
ROM
PC
Data Bus
Reset
Control
WDT
Clock
Generator
Timing
Generator
Sleep Mode
Control
Data pointer
ACC
ALU
Flag
Z
C
S
G
Stack pointer
Stack
ROM
HR
LR
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
P1.0/CLKOUT
P1.1
P1.2
P1.3
P7.0
P7.1
P7.2
P7.3
P8.0/INT1
P8.1
P8.2/INT0
P8.3/TRGA
RESET
XIN/CLK XOUT/NC
Infrared Control
3
* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
7.20.1999
V
DD
Power supply (+)
Vss
Power supply (-)
RESET
RESET-A
System reset input signal, low active
mask option:
none
pull-up
XIN/CLK
OSC-A/OSC-C Crystal/RC or external clock source connecting pin
XOUT/NC
OSC-A
Crystal connecting pin or NC for RC osc. type
P(0..3)/WAKEUP0..3
INPUT-C
4-bit input port with Sleep/Hold releaseing func tion
mask option :
none
pull-up
pull-down
P1.0/CLKOUT
OUTPUT-B
1-bit high current output pin for LED driving or clock output for
infrared signal
mask option :
open-drain, normal sink
open-drain, high sink
normal source, normal sink
normal source, high sink
P1(1..3)
OUTPUT-A
3-bit high current output pin for LED driving
mask option :
open-drain, normal sink
open-drain, high sink
normal source, normal sink
normal source, high sink
P7(0..3)
I/O-U
4-bit bidirection I/O port
mask option :
open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
P8.0/INT1,P8.2/INT0
I/O-W
2-bit bidirection I/O pins with external interrupt sources input
mask option :
open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
P8.3/TRGA
I/O-V
1-bit bidirection I/O pin with timer/counter A external input
mask option :
open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
P8.1
I/O-W
1-bit bidirection I/O pin
mask option :
open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
PIN DESCRIPTIONS
Symbol
Pin- Type
Function
4
* This specification are subject to be changed without notice.
7.20.1999
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 2K X 8 bits )
2 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of program ROM can be divided into 5 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch: 4 kinds of interrupt service rountine entry addresses .
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h ,07Eh, 086h .
4. Address 000h - 7FFh : LCALL subroutine entry address
5. Address 7E0h - 7FFh : The data region for 5-to-8 bits data conversion table .
6. Address 000h - 7FFh : Except used as above function, the other region can be used as user's program region.
address 2048 x 8 bits
000h
Reset start address
002h
INT0; External interrupt service routine entry address
004h
006h
TRGA, Timer/counterA interrupt service routine entry address
008h
00Ah
TBI; Time base interrupt service routine entry address
00Ch
INT1; External interrupt service routine entry address
00Eh
086h
7FFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by two ways.
(1) Table-look-up instruction:
Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get
the ROM code data.
LDAX
Acc
ROM[DP]
L
LDAXI
Acc
ROM[DP]
H
,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM
code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH",
then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by
instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]
L
07h
STADPM ; [DP]
M
07h
STADPH
; [DP]
H
07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX
; ACC
6h
.
.
.
.
.
.
SCALL, subroutine call entry address
5
* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
7.20.1999
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE:
To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03]
07h
CLR 0Eh,2 ; RAM[0Eh]
2
0
STACK:
There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example:
LDAM ; Acc
RAM[HL]
STAM ; RAM[HL]
Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
STAMI
; RAM[30]
6h
LDAXI
; ACC
5h
STAM
; RAM[31]
5h
:
ORG 777h
DATA 56h;
:
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
20h - 2Fh
30h - 33h
Level 0
Level 4
Level 8
Level 12
Level 1
Level 5
Level 9
Level 2
Level 6
Level 10
Level 3
Level 7
Level 11
Increment
00h - 0Fh
10h - 1Fh
Stack
Zero-page