* This specification are subject to be changed without notice.

EM19101

8-BIT 5 MSPS A/D CONVERTER (CMOS)

4.23.1997

GENERAL DESCRIPTION

EM19101 is a 8-bit CMOS A/D converter for scanner use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 7 MSPS.

FEATURES

· 7MSPS maximum conversion speed
· Build-in sampling and hold circuit
· Internal self-bias reference voltage
· 45 mW very low power dissipation at 5MSPS
· +5V single power supply
· Available in 24 pin SOP
· Series

EM19101M for 300 mil SOP
EM19101S for 209 mil SOP

APPLICATION

Scanner and a wide range of fields where high speed A/D conversion is required in the digital communication.

PIN ASSIGNMENT

EM19101

8-BIT 5 MSPS A/D CONVERTER (CMOS)

Lower data

latches

Upper data

latches

Lower encoder

(4bit)

Upper encoder

(4bit)

Lower

Comparators with

S/ H (4bit)

Upper

Comparators with

S/ H (4bit)

Reference voltage

1 0

1 2

1 1

1 5

1 3

1 4

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

Clock generator

/ O E

DVS S

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

DV DD

CL K

DV DD

AV DD

V RT S

V RT

AV DD

VI N

AVSS

V RBS

V R B

AVSS

DV S S

FUNCTIONAL BLOCK DIAGRAM

1
2
3
4
5
6
7
8
9

10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

DVSS

D0
D1
D2
D3
D4
D5
D6
D7

DVDD

CLK

DVSS
VRB
VRBS
AVSS
AVSS
VIN
AVDD
VRT
VRTS
AVDD
AVDD
DVDD

EM19101

* This specification are subject to be changed without notice.

EM19101

8-BIT 5 MSPS A/D CONVERTER (CMOS)

4.23.1997

TIMING DIAGRAM

Output enable

DVSS

Digital ground

Data output bit 0 (LSB)

Data output bit 1

Data output bit 2

Data output bit 3

Data output bit 4

Data output bit 5

Data output bit 6

Data output bit 7 (MSB)

DVDD

Digital power supply

CLK

Clock input

DVDD

Digital power supply

AVDD

Analog power supply

AVDD

Analog power supply

VRTS

Top internal reference voltage

VRT

Top reference voltaget

AVDD

Analog power supply

VIN

Analog input voltage

AVSS

Analog ground

AVSS

Analog ground

VRBS

Bottom internal reference voltage

VRB

Bottom reference voltage

DVSS

Digital ground

Symbol

Function

PIN DESCRIPTIONS

N-3

N-2

N+1

N+2

N+3

N+4

N-1

N+1

N+2

C l o ck

An alog input

D at a o u t pu t

Exte rnal
C lo c k

Tra n s f er

* This specification are subject to be changed without notice.

EM19101

8-BIT 5 MSPS A/D CONVERTER (CMOS)

4.23.1997

Step

Analog Input (V)

Digital Output Code

Conditions

0.607815

00000000

VRB=0.6V

0.607815~0.6156250

00000001

VRT=2.6V

0.6156250~0.6234375

00000010

1LSB=7.8125mV

....

124

1.6000000~1.6078125

10000000

125

1.6078125~1.6156250

10000001

....

254

2.5843750~2.5921875

11111110

255

2.5921875~

11111111

OUTPUT CODING

=5MPS,V

=5V,V

=0.5V,V

=2.5V,Ta=25

C External clock duty=40 to 60%)

Parameter

Sym.

Conditions

Min. Typ. Max.

Unit

Maximum Conversion Speed

Vin=0.6V to 2.6V fin=1kHz ramp

MSPS

Supply current

=5MSPS NTSC ramp wave input

Reference pin current

REF

5.7

8.0

9.1

Analog input bandwidth

MHz

Analog input capacitance

=1.5V+0.07Vrms

Reference resistance

REF

220

250

350

Internal bias

Short V

and V

RBS

0.55

0.6

0.65

-V

Short V

and V

RTS

1.9

2.0

2.1

Offset Voltage

-10

-35

-60

Digital input voltage

4.0

1.0

Digital input current

=max.

=0V

ABSOLUTE MAXIMUM RATINGS

=25

Items

Sym.

Rating

Unit

Supply voltage

Operating temperature

OPR

-20 to +65

Input voltage

to V

Ref, Input voltage

to V

Recommended Poerating Conditions

Items

Sym.

Rating

Unit

Supply voltage

,AV

4.75 TO 5.25

,DV

|DGND-AGND|

0 to 100

Reference input voltage

0 and above

and below

- V

1.0 to 3.0

Analog input voltage

to V

* This specification are subject to be changed without notice.

EM19101

8-BIT 5 MSPS A/D CONVERTER (CMOS)

4.23.1997

Parameter

Sym.

Conditions

Min. Typ. Max. Unit

Digital output current

OE=V

-0.5V

-1.1

=min.

=0.4V

3.7

Digital output current

OZH

OE=V

=0V

Output data delay

Integral nonlinearity

=5MSPS V

=0.6V to 2.6V

0.5

1.3

LSB

Differential nonlinearity

=5MSPS V

=0.6V to 2.6V

0.3

0.5

LSB

Differential gain error

NTSC 40 IRE mod ramp,
F

=14.3MSPS

1.0

Differential phase error

0.5

Aperture jitter

Sampling delay

Application Note

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog V

pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the

respective GND's.

Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100

in series between the amplifier output and A/D input.

Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits

Reference input

Voltage between V

to V

is compatible with the dynamic range of the analog input. Bypassing V

and

pins to GND, by means of a capacitor about 0.1

F, stable characteristics are obtained. By shorting V

and V

RTS

, V

and VRBS, the self bias function that generates V

=2.6V and V

=0.6V, is activated.

Timing

Analog input is sampled with the falling edge of external clock and output as digital data with a delay of 2.5
clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 25ns.

OE pin

By connecting OE to GND output mode is obtained. By connecting to V

high impedance is obtained.

Part Number EM19101