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Elpida Memory, Inc. 2003
MOS INTEGRATED CIRCUIT
µ
µ
µ
µ
PD45128163-I
128M-bit Synchronous DRAM
4-bank, LVTTL
WTR (Wide Temperature Range)
DATA SHEET
Document No. E0346N10 (Ver.1.0)
Date Published February 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Description
The
µ
PD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as
2,097,152
×
16
×
4 (word
×
bit
×
bank).
The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).
This product is packaged in 54-pin TSOP (II).
Features
·
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
·
Pulsed interface
·
Possible to assert random column address in every cycle
·
Quad internal banks controlled by BA0(A13) and BA1(A12)
·
Byte control by LDQM and UDQM
·
Programmable Wrap sequence (Sequential / Interleave)
·
Programmable burst length (1, 2, 4, 8 and full page)
·
Programmable /CAS latency (2 and 3)
·
Ambient temperature (T
A
):
-
40 to + 85
°
C
·
Automatic precharge and controlled precharge
·
CBR (Auto) refresh and self refresh
·
×
16 organization
·
Single 3.3 V
±
0.3 V power supply
·
LVTTL compatible inputs and outputs
·
4,096 refresh cycles / 64 ms
·
Burst termination by Burst stop command and Precharge command
Data Sheet E0346N10 (Ver. 1.0)
4
µ
µ
µ
µ
PD45128163-I
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
2M words
×
×
×
×
16 bits
×
×
×
×
4 banks
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
LDQM
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
V
CC
Vss
DQ15
VssQ
DQ14
DQ13
VccQ
DQ12
DQ11
VssQ
DQ10
DQ9
VccQ
DQ8
Vss
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A0 to A11
Note
: Address inputs
BA0(A13), BA1(A12) : Bank select
DQ0 to DQ15
: Data inputs / outputs
CLK
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE
: Write enable
LDQM
: Lower DQ mask enable
UDQM
: Upper DQ mask enable
V
CC
: Supply voltage
V
SS
: Ground
V
CC
Q
: Supply voltage for DQ
V
SS
Q
: Ground for DQ
NC
: No connection
Note A0 to A11 : Row address inputs
A0 to A8 : Column address inputs
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