Document No. E0269N10 (Ver. 1.0)
Date Published April 2002 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2002

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

PRELIMINARY DATA SHEET

128MB 32-bit Direct Rambus DRAM RIMM

Module

MC-4R128FKK6K (32M words

×
×
×
×

16 bits

×
×
×
×

2 channels)

Description

The 32-bit Direct Rambus RIMM module is a general-
purpose high-performance lines of memory modules
suitable for use in a broad range of applications
including computer memory, personal computers,
workstations, and other applications where high
bandwidth and latency are required.

The 32-bit RIMM module consists of 288Mb Direct
Rambus DRAM (Direct RDRAM) devices. These are
extremely high-speed CMOS DRAMs organized as
16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits the use of conventional
system and board design technologies. The 32-bit
RIMM modules support 800MHz transfer rate per pin,
resulting in total module bandwidth of 3.2GB/s.

The 32-bit RIMM module provides two independent 16
bit memory channels to facilitate compact system
design. The "Thru" Channel enters and exits the
module to support a connection to or from a controller,
memory slot, or termination. The "Term" Channel is
terminated on the module and supports a connection
from a controller or another memory slot.

The RDRAM

architecture enables the highest

sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
RDRAM device multi-bank architecture supports up to
four simultaneous transactions per device.

Features

128MB Direct RDRAM storage and 128 banks total
on module

2 independent Direct RDRAM channels, 1 pass
through and 1 terminated on 32-bit RIMM module

High speed 800MHz Direct RDRAM devices

232 edge connector pads with 1mm pad spacing

Module PCB size: 133.35mm

39.925mm

1.27mm

Gold plated edge connector pads contacts

Serial Presence Detect (SPD) support

Operates from a 2.5V (

5%) supply

Low power and power down self refresh modes

Separate Row and Column buses for higher
efficiency

MC-4R128FKK6K

Preliminary Data Sheet E0269N10 (Ver. 1.0)

Ordering Information

Part number

Organization

I/O Freq.
(MHz)

RAS access
time (ns)

Package

Mounted devices

MC-4R128FKK6K-840

32M x 16 x 2

800

232 edge connector pads
RIMM with heat spreader
Edge connector: Gold plated

4 pieces of

PD488588FF

FBGA (

BGA

) package

Module Pad Names

Pad Signal name

Pad

Signal name

Pad

Signal name

GND

A59

GND

B59

GND

SCK_THRU_L

CMD_THRU_L

A60

VTERM

B60

VTERM

GND

A61

VTERM

B61

VTERM

DQA8_THRU_L

DQA7_THRU_L

A62

GND

B62

GND

A63

DQA3_THRU_R

B63

DQA4_THRU_R

DQA6_THRU_L

DQA5_THRU_L

A64

GND

B64

GND

A65

DQA5_THRU_R

B65

DQA6_THRU_R

DQA4_THRU_L

DQA3_THRU_L

A66

GND

B66

GND

A67

DQA7_THRU_R

B67

DQA8_THRU_R

A10 DQA2_THRU_L

B10 DQA1_THRU_L

A68

GND

B68

GND

A11 GND

B11 GND

A69

VDD

B69

VDD

A12 DQA0_THRU_L

B12 CTMN_THRU_L

A70

GND

B70

GND

A13 GND

B13 GND

A71

SCK_THRU_R

B71

CTMN_TERM_L

A14 CFM_THRU_L

B14 CTM_THRU_L

A72

GND

B72

GND

A15 GND

B15 GND

A73

CMD_THRU_R

B73

CTM_TERM_L

A16 CFMN_THRU_L

B16 ROW2_THRU_L

A74

GND

B74

GND

A17 GND

B17 GND

A75

VREF

B75

VCMOS

A18 ROW1_THRU_L

B18 ROW0_THRU_L

A76

VDD

B76

VDD

A19 GND

B19 GND

A77

SVDD

B77

SWP

A20 COL4_THRU_L

B20 COL3_THRU_L

A78

VDD

B78

VDD

A21 GND

B21 GND

A79

SCL

B79

SDA

A22 COL2_THRU_L

B22 COL1_THRU_L

A80

VDD

B80

VDD

A23 GND

B23 GND

A81

SA0

B81

SA1

A24 COL0_THRU_L

B24 DQB0_THRU_L

A82

VDD

B82

VDD

A25 GND

B25 GND

A83

SA2

B83

SIN_TERM

A26 DQB1_THRU_L

B26 DQB2_THRU_L

A84

GND

B84

GND

A27 GND

B27 GND

A85

DQB8_TERM

B85

DQB7_TERM

A28 DQB3_THRU_L

B28 DQB4_THRU_L

A86

GND

B86

GND

A29 GND

B29 GND

A87

DQB6_TERM

B87

DQB5_TERM

A30 DQB5_THRU_L

B30 DQB6_THRU_L

A88

GND

B88

GND

A31 GND

B31 GND

A89

DQB4_TERM

B89

DQB3_TERM

A32 DQB7_THRU_L

B32 DQB8_THRU_L

A90

GND

B90

GND

A33 GND

B33 GND

A91

DQB2_TERM

B91

DQB1_TERM

A34 SOUT_THRU

B34 SIN_THRU

A92

GND

B92

GND

A35 GND

B35 GND

A93

DQB0_TERM

B93

COL0_TERM

A36 DQB8_THRU_R

B36 DQB7_THRU_R

A94

GND

B94

GND

MC-4R128FKK6K

Preliminary Data Sheet E0269N10 (Ver. 1.0)

Pad Signal name

Pad

Signal name

Pad

Signal name

A37 GND

B37 GND

A95

COL1_TERM

B95

COL2_TERM

A38 DQB6_THRU_R

B38 DQB5_THRU_R

A96

GND

B96

GND

A39 GND

B39 GND

A97

COL3_TERM

B97

COL4_TERM

A40 DQB4_THRU_R

B40 DQB3_THRU_R

A98

GND

B98

GND

A41 GND

B41 GND

A99

ROW0_TERM

B99

ROW1_TERM

A42 DQB2_THRU_R

B42 DQB1_THRU_R

A100

GND

B100

GND

A43 GND

B43 GND

A101

ROW2_TERM

B101

CFMN_TERM

A44 DQB0_THRU_R

B44 COL0_THRU_R

A102

GND

B102

GND

A45 GND

B45 GND

A103

CTM_TERM_R

B103

CFM_TERM

A46 COL1_THRU_R

B46 COL2_THRU_R

A104

GND

B104

GND

A47 GND

B47 GND

A105

CTMN_TERM_R

B105

DQA0_TERM

A48 COL3_THRU_R

B48 COL4_THRU_R

A106

GND

B106

GND

A49 GND

B49 GND

A107

DQA1_TERM

B107

DQA2_TERM

A50 ROW0_THRU_R

B50 ROW1_THRU_R

A108

GND

B108

GND

A51 GND

B51 GND

A109

DQA3_TERM

B109

DQA4_TERM

A52 ROW2_THRU_R

B52 CFMN_THRU_R

A110

GND

B110

GND

A53 GND

B53 GND

A111

DQA5_TERM

B111

DQA6_TERM

A54 CTM_THRU_R

B54 CFM_THRU_R

A112

GND

B112

GND

A55 GND

B55 GND

A113

DQA7_TERM

B113

DQA8_TERM

A56 CTMN_THRU_R

B56 DQA0_THRU_R

A114

GND

B114

GND

A57 GND

B57 GND

A115

CMD_TERM

B115

SCK_TERM

A58 DQA1_THRU_R

B58 DQA2_THRU_R

A116

GND

B116

GND

MC-4R128FKK6K

Preliminary Data Sheet E0269N10 (Ver. 1.0)

Module Connector Pad Description

Signal

Module
connector pads

I/O

Type

Description

CFM_THRU_L

A14

RSL

Clock From Master. Connects to left RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.

CFM_THRU_R

B54

RSL

Clock From Master. Connects to right RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.

CFMN_THRU_L

A16

RSL

Clock From Master. Connects to left RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.

CFMN_THRU_R

B52

RSL

Clock From Master. Connects to right RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.

CMD_THRU_L

VCMOS

Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to left RDRAM device on "Thru" Channel.

CMD_THRU_R

A73

VCMOS

Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to right RDRAM device on "Thru" Channel.

COL4_THRU_L..
COL0_THRU_L

A20, B20, A22, B22,
A24

RSL

"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to left
RDRAM device on "Thru" Channel.

COL4_THRU_R..
COL0_THRU_R

B48, A48, B46, A46,
B44

RSL

"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Thru" Channel.

CTM_THRU_L

B14

RSL

Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.

CTM_THRU_R

A54

RSL

Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.

CTMN_THRU_L

B12

RSL

Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.

CTMN_THRU_R

A56

RSL

Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.

DQA8_THRU_L..
DQA0_THRU_L

A4, B4, A6, B6, A8,
B8, A10, B10, A12

I/O

RSL

"Thru" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on "Thru" Channel. Connects to left RDRAM device on "Thru"
Channel. DQA8_THRU_L is non-functional on modules.

DQA8_THRU_R..
DQA0_THRU_R

B67, A67, B65, A65,
B63, A63, B58, A58,
B56

I/O

RSL

"Thru" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on "Thru" Channel. Connects to right RDRAM device on
"Thru" Channel. DQA8_THRU_R is non-functional on
modules.

DQB8_THRU_L..
DQB0_THRU_L

B32, A32, B30, A30,
B28, A28, B26, A26,
B24

I/O

RSL

"Thru" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on "Thru" Channel. Connects to left RDRAM device on "Thru"
Channel. DQB8_THRU_L is non-functional on modules.

DQB8_THRU_R..
DQB0_THRU_R

A36, B36, A38, B38,
A40, B40, A42, B42,
A44

I/O

RSL

"Thru" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on "Thru" Channel. Connects to right RDRAM device on
"Thru" Channel. DQB8_THRU_R is non-functional on
modules.

ROW2_THRU_L..
ROW0_THRU_L

B16, A18, B18

RSL

Row bus. 3-bit bus containing control and address information
for row accesses. Connects to left RDRAM device on "Thru"
Channel.

MC-4R128FKK6K

Preliminary Data Sheet E0269N10 (Ver. 1.0)

Signal

Module
connector pads

I/O

Type

Description

ROW2_THRU_R..
ROW0_THRU_R

A52, B50, A50

RSL

Row bus. 3-bit bus containing control and address information
for row accesses. Connects to right RDRAM device on "Thru"
Channel.

SCK_THRU_L

VCMOS

Serial Clock input. Clock source used to read from and write
to "Thru" Channel RDRAM control registers. Connects to left
RDRAM device on "Thru" Channel.

SCK_THRU_R

A71

VCMOS

Serial Clock input. Clock source used to read from and write
to "Thru" Channel RDRAM control registers. Connects to right
RDRAM device on "Thru" Channel.

SIN_THRU

B34

I/O

VCMOS

"Thru" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO0 of right RDRAM device on
"Thru" Channel.

SOUT_THRU

A34

I/O

VCMOS

"Thru" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO1 of left RDRAM device on
"Thru" Channel.

CFM_TERM

B103

RSL

Clock from master. Connects to right RDRAM device on
"Term" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.

CFMN_TERM

B101

RSL

Clock from master. Connects to right RDRAM device on
"Term" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.

CMD_TERM

A115

VCMOS

Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to right RDRAM device on "Term" Channel.

COL4_TERM..
COL0_TERM

B97, A97, B95, A95,
B93

RSL

"Term" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Term" Channel.

CTM_TERM_L

B73

RSL

Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.

CTM_TERM_R

A103

RSL

Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.

CTMN_TERM_L

B71

RSL

Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.

CTMN_TERM_R

A105

RSL

Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.

DQA8_TERM..
DQA0_TERM

B113, A113, B111,
A111, B109, A109,
B107, A107, B105

I/O

RSL

"Term" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on "Term" Channel. Connects to right RDRAM device on
"Term" Channel. DQA8_TERM is non-functional on modules.

DQB8_TERM..
DQB0_TERM

A85, B85, A87, B87,
A89, B89, A91, B91,
A93

I/O

RSL

"Term" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on "Term" Channel. Connects to right RDRAM device on
"Term" Channel. DQB8_TERM is non-functional on modules.

ROW2_TERM..
ROW0_TERM

A101, B99, A99

RSL

"Term" Channel Row bus. 3-bit bus containing control and
address information for row accesses. Connects to right
RDRAM device on "Term" Channel.

SCK_TERM

B115

VCMOS

Serial Clock input. Clock source used to read from and write
to "Term" Channel RDRAM control registers. Connects to
right RDRAM device on "Term" Channel.

SIN_TERM

B83

I/O

VCMOS

"Term" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO0 of left RDRAM device on
"Term" Channel.

VTERM

A60, B60, A61, B61

"Term" Channel Termination voltage.

Part Number MC-4R128FKK6K

Document Outline