MA31750

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The Dynex Semiconductor MA31750 is a single-chip

microprocessor that implements the full MIL-STD-1750A
instruction set architecture, or Option 2 of Draft MIL-STD-
1750B. The processor executes all mandatory instructions and
many optional features are also included. Interrupts, fault
handling, memory expansion, Console, timers A and B, and
their related optional instructions are also supported in full
accordance with MIL-STD-1750.

The MA31750 offers a considerable performance increase

over the existing MAS281. This is achieved by using a 32-bit
internal bus structure with a 24 x 24 bit multiplier and 32-bit
ALU. Other performance-enhancing features include a 32-bit
shift network, a multi-port register file and a dedicated address
calculation unit.

The MA31750 has on-chip parity generation and checking

to enhance system integrity. A comprehensive built-in self-test
has also been incorporated, allowing processor functionality to
be verified at any time.

Console operation is supported through a parallel interface

using command/data registers in l/O space. Several discrete
output signals are produced to minimise external logic.

Control signals are also provided to allow inclusion of the

MA31750 into a multiprocessor or DMA system.

The processor can directly access 64KWords of memory in

full accordance with MIL-STD-1750A. This increases to
1MWord when used with the optional MA31751 memory
management unit (MMU). 1750B mode allows the system to
be expanded to 8MWord with the MMU.

IO control

DOUT

file

Address

generator

Sequencer

Microcode ROM

ALU

Qshift

Multiplier

Shift network

Interrupt

controller

Flags

Bus
Control

Parity

Bus
arb.

Address

Data

CLK

ebf

Microcode control
words to other blocks

Y bus

R bus

S bus

Ints

Faults

uAddr

rap

mov

abort

uData

aluv

INTAKN
BUSFAULTN

Figure 1: Architecture

MA31750

High Performance MIL-STD-1750 Microprocessor

Replaces July 1999 version, DS3748-7.0

DS3748-8.0 January 2000

MA31750

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1. ARCHITECTURE

The Dynex Semiconducor MA31750 Microprocessor is a

high performance implementation of the MIL-STD-1750A
(Notice 1) Instruction Set Architecture. Figure 1 depicts the
architectural details of the chip. Two key features of this
architecture which contribute to the overall high performance
of the MA31750 are a 32-bit shift network and a 24-bit parallel
multiplier. These sub-systems allow the MA31750 to perform
multi-bit shifts, multiplications,divisions and normalisations in a
fraction of the clock cycles required on machines not having
such resources. This is especially true of floating-point
operations, in which the MA31750 excels. Such operations
constitute a large proportion of the Digital Avionics Instruction
Set (DAIS) mix and generally a high percentage of many signal
processing algorithms, therefore having a significant impact on
system performance.

Key features include:

1) A three-bus (R, S, and Y) datapath consisting of an

arithmetic/logic unit (ALU), three-port register file, shift
network, parallel multiplier and flags block;

2) Four instruction fetch registers C0,C1, IA, and IB;
3) Two operand transfer registers DI, and DO;
4) Two address registers IC and A;
5) A state sequencer;
6) Micro-instruction decode logic.

The relationship between these functional blocks is shown

in Figure 1.

2. ADDITIONAL FEATURES

The MA31750 may be operated in one of two basic user

selectable modes. 1750A mode follows the requirements of
MIL-STD-1750A (Notice 1) and implements all of the
mandatory features of this standard. In addition, many of the
optional features such as interval timers A and B, a watchdog
timer and parity checking are included. 1750B mode, when
selected, allows the user access to a range of new instructions
and features as described in the Draft MIL-STD-1750B, Option
2. These include a range of unsigned arithmetic operations
and expanded addressing support instructions.

2.1. MIL-STD-1750 OPTIONAL FEATURES

In addition to implementing all of the required features of

MIL-STD-1750A and the Draft standard MIL-STD-1750B, the
MA31750 also incorporates a number of optional features.
Interval timers A and B as well as a trigger-go counter are
provided. Most specified XIO commands are decoded directly
on the chip and an additional set of commands, associated
with MMU and BPU operations, are also decoded on chip.

2.2. BUS ARBITRATION

The MA31750 has a number of extra control lines to allow

its use in a system utilising multiple processors. A bus request
and grant system coupled with external arbitration logic allows
common data and address buses to be used between devices.
A lock request pin is also provided to allow the processor to
maintain control of the buses when modifying areas of shared
memory.

2.3. MEMORY BLOCK PROTECTION

The basic MMU function allows write or execute protection

to be applied on 4KWord block boundaries. This may be
further resolved to 1kWord blocks by the inclusion of a Block
Protect Unit (BPU). The MA31751 can act as both an MMU
and a BPU in 1750A mode, operating with the full compliment
of 1MWord of memory. It will also support expansion to
8MWord in accordance with Draft MIL-STD-1750B.

MA31750

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3. MODES OF OPERATION

MA31750 operating modes include: (1) initialisation, (2)

instruction execution, (3) interrupt servicing, (4) fault servicing,
(5) timer operations and (6) console operation.

3.1. INITIALISATION

The MA31750 executes a microcoded initialisation routine

in response to a hardware reset or power-up. Figure 3 shows
a cycle-by-cycle breakdown of this routine. The operations
performed are dependent on the system configuration read by
the processor during startup. Figure 2 summarises the
resulting initialisation state.

The last action performed by the initialisation routine is to

load the instruction pipeline. Instruction fetches start at
memory location zero with AS = 0, PS = 0 and PB = 0 and will
be from the Start-Up ROM (SUR) if implemented. Whether
BIT passes or not, the processor will begin instruction
execution at this point. The system start-up code may include
a routine to enable and unmask interrupts in order to detect
and respond to a BIT failure if required.

Addr

Operation

PIC initialised

A<-- 0x8410

Read external configuration register from 8410H
(CONFWN asserted low)

If BPU, N<-- 128 else N<-- 0

Decrement N; branch to 21 if N >= 0

Write internal configuration register

If no MMU, br to 7

N <-- 256

Decrement N

*17

Write MMU Instruction Page Register N

*18

Write MMU Operand Page Register N; branch to 16 if
N > 0

A <-- 0400H

N <-- 16

PBSR <-- N

*1D

Write Memory control register to MMU with PB = N

Decrement N; branch if N >= 0 to 1B

A <-- 0

IC <-- A

Br to BIT if required

Br if no SUR to 00D

Re-init PIC

Zero SW

Br to 011 if BIT passed (or not run)

34
35
36

Set FT bit 13

Init DMAE, SUREN, NPU

12
*3F8

Fetch first word from 0

*3F9

Fetch second word from 1
First instruction first cycle

* Indicates an external cycle

Figure 3: Initialization Sequence

Figure 2: Initialization State

M A 3 1 7 5 0
Instruction Counter

Zero

Status Word

Zero

Fault Register Zero

Zero

Fault Mask Register (1750B)

All ones

Pending Interrupt Register

Zero

Interrupt Mask Register

Zero

General Registers

Undefined

Interrupts

Disabled

Timers A and B

Zeroed and started

Timer Reset Registers (1750B)

Zero

Trigger-Go Counter

Reset and started

TGON Line

High

Start-Up ROM

Enabled

DMA

Disabled

MMU
Page Registers AL/W/E fields

Zero

Page Register PPA field

Logical to physical

B P U
Memory Protect RAM

Zero (disabled)

Global Memory Protect

Enabled

MA31750

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3.1.1. CONFIGURATION REGISTER

The system configuration register allows the MA31750 to

function with a variety of different system designs.
Implemented features such as a BPU should be indicated as
present by setting bits in an externally-implemented 16-bit
latch - see figure 4 for bit assignments. The latch must be
placed in IO space at the address defined by XIO RCW (8410)
shown in the table of XIO commands, Figure 20c. The
processor decodes this command internally and produces a
discrete output signal CONFWN which may be used as the
external register Output Enable control.

3.1.2. BUILT-IN TEST (BIT)

BIT consists of ten subroutines, as outlined in Figure 6. If

all ten subroutines execute successfully, or no BIT is selected
in the configuration word, a BIT pass is flagged (seen
externally as NPU raised high by the initialization routine). If
any part of BIT fails, a corresponding bit identifying the failed
subroutine is set in General Register R0, Fault Bit 13 is set in
the Fault register (FT) and NPU is left in the low state. Figure 6
defines the coding of BIT results in R0. In the event of such a
failure, the resulting processor reset state will be dependent on
where in BIT the error occurred and may not be the same as
that shown in figure 2. A BIT failure indication in FT will set the
level 1 interrupt request bit of the Pending Interrupt (Pl)
register. Since initialisation disables and masks interrupts, this
interrupt request will not be asserted. Any external interrupts or
faults occurring during BIT will be cleared before program
execution begins and will not be serviced.

The processor maintains an internal configuration register

which is updated from the external register during initialisation
and during the execution of a NOP/BPT (No-op/Breakpoint)
instruction. The internal configuration register is used to
control the CPU. Note that although the external register can
be read using XIO RCW, this does not affect the internal
configuration. Note: if the interrupt level/edge trigger select bit
- (bit 4) is changed in the internal register during normal
operation of the device, one or more spurious interrupts may
occur.

When in 1750B mode, the processor needs to know how

many Page Banks are implemented in the external system so
that Status Word changes can be protected properly. MIL-
STD-1750B allows the options 0,1,2,4,8 or 16. The actual
selection should be coded into the three configuration register
bits MMU0, MMU1 and MMU2 as shown in figure 5.

In 1750A mode, setting any of the MMU select bits

indicates the presence of an MMU, the actual code is
unimportant in this mode.

BPU selects bits 2:0 should be set to indicate how much

BPU-protected memory exists on the system. If no BPU is
present, all three bits should be zero.

Bit

Function

MMU Select 0

BPU Select 0

1 = Console operation enabled

MMU Select 1

Interrupt sensitivity (1 = level, 0 = edge)

MMU Select 2

Parity sense (1 = odd, 0 = even)

1= BIT on power-up

1 = Start-Up ROM present

1 = DMA device present

1=1750A mode, 0=1750B mode

1=Instruction set expansion enabled

BPU Select 1

BPU Select 2

14-15

Reserved for future expansion

Figure 4: Configuration Word Bits

Selected bit

Function

M M U 2

M M U 1

M M U 0

No MMU in system

1 Page Bank (PB0)

2 Page Banks (PB0-1)

4 Page Banks (PB0-3)

8 Page Banks (PB0-7)

16 Page Banks (PB0-15)

Note: In 1750A mode, setting any or all of the MMU

select bits indicates the presence of an MMU.

Figure 5: MMU Selection Bits

Test Coverage

M a c h i n e

C y c l e s

Bit set

on fail

Temporary Registers (T0-T11)

General Registers (R0-R15)

Flags Block

Sequencer Operation and ROM
checksum

5632

Divide routine Quotient Shift
Network

Multiplier and ALU

Barrel shift Network

Interrupts and fault handling and
detection

Address generator block

Instruction pipeline

Note:

BIT pass is indicated by all zeros
in FT bits 13,14, and 15

Figure 6: Built-In Test Coverage

MA31750

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3.2. INSTRUCTION EXECUTION

Once initialisation has been completed, the processor will

begin instruction execution. Instruction execution is
characterised by a variety of operations, each is one machine
cycle in duration (two or more system CLK periods).
Depending on the instruction being executed at the time, these
operations include: (1) internal CPU cycles, (2) instruction
fetches, (3) operand transfers, and (4) input/output transfers.

Instruction execution may be interrupted at the end of any
individual machine cycle by an interrupt or Console request.
Internal cycles are always two CLK periods long, whilst the
other cycle types are a minimum of two CLK periods -
extendable by inserting waitstates. In all cycles except internal
cycles, RDN, WRN, DSN and AS strobes are produced to
control the transfer and latching of data and address around
the system.

Cycle Type

RD/WRN

O/IN

M/ION

Description

Internal Cycle

Used to perform all CPU data manipulation operations where bus
activity is not required.

Instruction
Fetch

Used to keep the instruction pipeline full with instructions and/or their
postwords. At least one instruction is always ready for execution when
the preceding instruction is completed. During jump and branch
instruction execution the pipeline is refilled by two consecutive
instruction fetches starting at the new instruction location. It is also
refilled as part of interrupt request processing.

Operand Read
Operand Write

H
L

H
H

Used to read in data from the external system and to write results to the
system.

IO Read
IO Write

H
L

H
H

L
L

Input/Output transfers utilize the MIL-STD-1750 XIO and VIO
instructions. RD/WN defines the direction of the transfer. IO transfers
may be divided into three groups; those commands which are
implemented internally by the CPU, those commands which are
implemented by external system hardware and those commands
defined as illegal by MIL-STD-1750A and B.

Figure 7: External Cycle Types

3.3. IO OPERATION

The MA31750 supports a 64KWord addressing space

dedicated to IO control and communication in accordance with
MIL-STD-1750. The control line MION is asserted low when
accessing IO space (see figure 7 above for other strobe
states). One of the two commands XIO or VIO is used to
specify both data for the transfer and the port address (referred
to as an XIO Command in 1750). The CPU contains logic
which decodes all internally supported XIO commands and
generates the control signals necessary to carry out the
commanded action. In addition, the validity of a command not
implemented internally is verified. Figure 20c identifies the XIO
commands which are internally supported by the MA31750.

3.4. INTERRUPT AND FAULT HANDLING

3.4.1. STATUS WORD (SW)

Figure 8 depicts the status register format. This 16-bit word

is divided into four, 4-bit sections. Three of these sections [AS,
PS and, (1750B mode) PB] are control bits for implementing
expanded memory with an external MMU. The fourth section,
CS, is used to hold the carry, positive, zero and negative
condition flags set by the result of the previous arithmetic
operation.

R (PB)

3 4

7 8

11 12

Field

Bits

Description

1
2
3

CONDITION STATUS
C- Carry from an addition or no
borrow from a subtraction.
P- Result > 0
Z- Result = 0
N- Result < 0

R
PB

4-7

RESERVED (=0) in 1750A mode
Page Bank Select in 1750B mode

8-11

PROCESSOR STATE:
(a)- Memory access to key code
(b)- Priviledged instruction enable

12-15

ADDRESS STATE:
Page register sets for expanded
memory addressing.

Figure 8: Status Word Format

Part Number MA31750