MA28139

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The OBT ASIC will interface any user to the ESA On Board

Data Handling bus. Developed under ESA Contract, it
conforms to ESA OBDH, Digital Bus Interface and Internal
User Bus Standards.

The OBT has 2 separate functions. The first is a 5 channel

modem which, on the bus side, provides the digital waveforms
necessary to operate the Litton Bus drivers, and receives the
outputs of the Litton bus detectors. On the user side, it
provides an input / output at Digital Bus Interface level. The
second function, internally coupled to the first, provides a
multiplexing / demultiplexing function of the DBI signals down
to Internal User Bus levels and vectored 16 bit serial register
read and write commands (see section 7.2 of ESA standard
TTC-B-01). In effect, the second function of the OBT provides
the core of an RTU.

The Interrogation and Response bus data streams of the

two functions may be either coupled together (in RT mode) or
isolated (in CT mode). The device may hence be used as a
modem only, an RTU kernel only or as a combined modem
and RTU kernel. In RT mode, the Interrogation bus data
stream can be observed and the Response bus data from
associated devices, such as an MA28138 Remote Bus
Interface, can be combined with that from the RTU kernel
before being used by the modem circuits to modulate the
Response bus. Bi-directional access to the Block Transfer bus
is provided in either mode.

When used to interface a central terminal to the OBDH bus,

the OBT should be continuously clocked in order to output
timing to all users on the I-bus as dummy interrogations from
the CT. Commands and telemetry are normally sent on the I
and BT busses whilst responses and telemetry normally return
on the R and BT busses.

Figure 1: Block Diagram

CONTROL

LOGIC

RTU

KERNEL

CONTROL

PINS

CLK DETECTOR,

WATCHDOG

DIGITAL
BUS
INTERFACE

INTERNAL
USER
BUS

CONFIGURATION PINS

OBDH BUS

I R BT

I Rx

R Rx

I (CTU)
R (RTU)

BT Rx

FEATURES

Radiation Hard

Low Power Consumption

Single CMOS-SOS ASIC Implementation

Latch-up Free

High SEU Immunity

Fully Compliant with ESA OBDH, IUB, DBI and RBI
Specification

Contains OBDH Bus Modem and RTU Kernel

Supports Bi-directional Data Transfer on Response and
Block Transfer Bus

MA28139

OBDH Bus Terminal

Replaces June 1999 version, DS3592-5.0

DS3592-6.0 January 2000

MA28139

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APPLICATION

PAYLOAD INTERFACES

The OBT converts the OBDH bus to an Internal User Bus,

and a Digital Bus Interface. The OBT can connect OBDH to
existing ESA standard payload interfaces such as the MSS
PIU (payload interface unit), ICU (intelligent control unit), SBC

Figure 3: Payload Interface

Figure 2: Application

DBI

IUB

PIU

PAYLOAD

BT-Bus

R-Bus

I-Bus

RBI

MA28138

MEMORY

I/O

PAYLOAD

DMA

AD-BUS

SBC

OBDH

ANALOGUE

HYBRID

DISCRETE

CIRCUIT

OBDH

BUS

TERMINAL

MA28139

(single board MIL-STD-1750 computer) or FTC (fault tolerant
computer).

The OBT and analogue components/transformers can be

integrated in the PIU, ICU, SBC, etc.

CENTRAL TERMINAL

Bus Controller

OBT

DMUX

MPX

DMUX

ADC

RBI

RAM

µP

I/O

RBI

RAM

µP

I/O

IUB

DBU

DBI

ODBH BUS

DBI

Commands

Timing

Digital

Data

Analogue

Data

Address

REMOTE TERMINAL

INTELLIGENT TERMINAL

DBI

UP TO A TOTAL OF 62 TERMINALS

MA28139

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FUNCTIONAL DESCRIPTION

In RT mode, power up resets the OBT and causes it to

deselect both busses. Two watchdog counters monitor the
Nominal l-bus and the Redundant l-bus. If either bus becomes
active, that bus will be selected. If the selected bus stops, the
OBT watchdog times out and resets both the OBT and the
user. If both busses become active, the Nominal bus will be
selected in preference to the Redundant one. A change in bus
selection will always result in the OBT and the user being
reset. Responses from the user are always returned on the
selected bus. Setting `SIMUL' high causes both BATs to drive
both the Nominal and the Redundant busses irrespective of
the current bus selection. The time-out period may be set to
any desired number of bits by varying the `LOSC' frequency.
The OBT derives all timing from, and is synchronous with, the
selected l-bus. The OBT demodulates the l-bus to the DBI and
decodes commands to the IUB.

The CTpRTn mode pin causes the modem circuits and the

RTU Kernel to be either cascade or isolated. If CTpRTn is low
(RT mode), the RIRSYNC, CLK, DATA and VAL signals are
routed to the RTU Kernel and the associated pins act as

outputs; responses from the RTU Kernel are ORed with those
from the external RRTDATA and RRTEN inputs and can be
independently monitored on the DATARRT and ENRRT pins.
In this mode any reset caused by the Clock Detector
watchdogs is also combined with the power up reset input.

If CTpRTn is high (CT mode), the modem and RTU Kernel

functions are isolated to permit the device to be used as either
a modem within the CTU or an RTU Kernel interfacing to an
external modem where the RIRSYNC, CLK, DATA and VAL
pins act as inputs. The right-hand multiplexer bank is switched
to the upper position so that the CT drives the OBDH via the
CIT and CBT (if used) pins and receives responses/telemetry
via the CRR and CBR (if used) pins. Note: in CT mode, BAT1
must be connected to the l-busses.

In RT mode, the CITSEL, MOD, CLK, SYNC and INV pins

are disabled and the clocks are supplied by the l-bus BAR in
response to the selected bus. In CT mode, the Clock Detector
is functional and drives the TlMEOUTn pin but is unable to
cause internal reset on time-out; in this mode the CT must
supply all clocks and select the operational bus.

The changes depending upon selection of RT mode or CT mode with the CTpRTn pin are defined in the table below:

Functional Signal

CT Mode Source

RT Mode Source

(CTpRTn = `1')

(CTpRTn = `0')

BAT1, 2 modulation clock

CITMOD input pin

Recovered R2F

BAT1, 2 data clock

CITCLK input pin

Recovered RIRCLK

BAT1 data input

RRTDATA input pin

RRTDATA OR DATARRT (RTU Kernel)

BAT1 tx enable

`1'

RRTEN OR DATAEN (RTU Kernel)

BAT1 sync code tx enable

CITSYNC input pin

`0'

BAT1 bit invalidate tx enable

CITINV input Pin

`0'

BAT1, 2 bus selection

CITSEL and SIMUL input pins

Detected active bus and SIMUL input pin

BAT2 data input

RBTDATA input Pin

RBTDATA input pin

BAT2 tx enable

RBTEN input pin

BAT1, 2, BAR1, 2, 3 reset

MRSTn input pin

TlMEOUTn AND MRSTn input pin

RIRSYNC, CLK, DATA,

outputs

inputs

VAL pin direction

BAT/BAR and RTU Kernel

separated

coupled

coupling

MA28139

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Figure 4: Architecture

MODEM Modulation Waveforms are compliant with ESA document THB/Apo/KZ/1386/av. Waveforms indicating the

operation of BAT1, 2 and BAR1, 2, 3 in both the CT and RT modes are shown in Figures 5 to 8.

Note: Switches in lower position - RT mode

Switches in upper position - CT mode

BUS

TIME

OUT

SIMUL

MODE RESET

IUB

SYNC, CLK, DATA, VAL RIR

SEL

MOD

CLK

SYNC

INV

DATA

CLK, DATA, VAL

INIT

DATA
EN

CLK, DATA, VAL

INIT

RBR/
CBR

RBT/CBT

RRR/CRR

CIT

RRT

DBI

BAR1

I-BUS RX

BAT1

BAR2

R-BUS RX

BAT2

BT-BUS TX

BAR3

BT-BUS RX

MA28139 OBT

CLK

OBDH

CLOCK

DETECTOR

WATCHDOG

NOMINAL

BUS #1

REDUNDANT
BUS #2

I R BT

NIDS1/2n,
RIDS1/2n

RR1-4,
NRE, RRE

NRDS1/2n
RRDS1/2n

BR1-4,
NBE, RBE

NBDS1/2n,
RBDS1/2n

R-BUS TX

(RT MODE)

I-BUS TX

(CT MODE)

TA0-5 TAV

DATARRT

ENRRT

RTU

KERNEL

BUS 1/2
ACTIVE

LOSC

OPEN

Part Number MA28139