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092000

FEATURES

Li-Ion safety circuit
-

Overvoltage protection

Overcurrent/short circuit protection

Undervoltage protection

Available in two configurations:
-

Internal 25 m

sense resistor

External user-selectable sense resistor

Current measurement
-

12-bit bi-directional measurement

Internal sense resistor configuration:
0.625 mA LSB and ą1.8A dynamic range

External sense resistor configuration:
15.625

V LSB and ą64 mV dynamic range

Current accumulation
-

Internal sense resistor: 0.25 mAhr LSB

External sense resistor: 6.25

Vhr LSB

Voltage measurement with 4.88 mV resolution

Temperature measurement using integrated
sensor with 0.125

C resolution

System power management and control feature
support

32 bytes of lockable EEPROM

16 bytes of general purpose SRAM

Dallas 1-Wire

interface with unique 64-bit

device address

Low power consumption:
-

Active current: 80

A max

Sleep current:

A max

PIN ASSIGNMENT

PIN DESCRIPTION

- Charge control output

- Discharge control output

DQ - Data input/output
PIO - Programmable I/O pin
PLS - Battery pack positive terminal input

- Power switch sense input

VIN - Voltage sense input
VDD- Power supply input (2.5V-5.5V)
VSS - Device ground
SNS - Sense resistor connection
IS1 - Current sense input
IS2 - Current sense input
NC - Not connected
SNS Probe Do not connect
VSS Probe Do not connect

DS2760

High Precision Li-Ion Battery Monitor

www.dalsemi.com

PRELIMINARY

DC NC NC NC PIO

DQ IS2 IS1 PS

NC NC

DS2760

Flip-Chip Packaging

VIN

VDD

PIO

VSS

IS1

DS2760

16-Pin TSSOP Package

IS2

SNS

2
3

SNS

PLS

PLS CC VIN VDD

SNS

Probe

VSS

Probe

SNS

VSS

DS2760

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ORDERING INFORMATION

DS2760E

TSSOP, External Sense
Res., 4.35V V

DS2760EA

TSSOP, External Sense
Res., 4.275V V

DS2760T

DS2760E on Tape & Reel

DS2760TA

DS2760EA on Tape &
Reel

DS2760E-025

TSSOP, 25 m

Sense

Res., 4.35V V

DS2760EA-025

TSSOP, 25 m

Sense

Res., 4.275V V

DS2760T-025

DS2760E-025 in Tape &
Reel

DS2760TA-025

DS2760EA-025 in Tape
& Reel

DS2760X

Flipchip, Ext. Sense Res.,
T&R, 4.35V V

DS2760XA

Flipchip, Ext. Sense Res.,
T&R, 4.275V V

DS2760X-025

Flipchip, 25 m

Sense

Res., T&R, 4.35V V

DS2760XA-025

Flipchip, 25 m

Sense

Res., T&R, 4.275V V

DESCRIPTION

The DS2760 High Precision Li-Ion Battery Monitor is a data acquisition, information storage, and safety
protection device tailored for cost-sensitive battery pack applications. This low-power device integrates
precise temperature, voltage, and current measurement, nonvolatile data storage, and Li-Ion protection
into the small footprint of either a TSSOP package or flip-chip. The DS2760 is a key component in
applications including remaining capacity estimation, safety monitoring, and battery-specific data storage.

Via its 1-Wire interface, the DS2760 gives the host system read/write access to status and control
registers, instrumentation registers, and general purpose data storage. Each device has a factory-
programmed 64-bit net address which allows it to be individually addressed by the host system,
supporting multi-battery operation.

The DS2760 is capable of performing temperature, voltage and current measurement to a resolution
sufficient to support process monitoring applications such as battery charge control, remaining capacity
estimation, and safety monitoring. Temperature is measured using an on-chip sensor, eliminating the need
for a separate thermistor. Bi-directional current measurement and accumulation are accomplished using
either an internal 25 m

sense resistor or an external device. The DS2760 also features a programmable

I/O pin that allows the host system to sense and control other electronics in the pack, including switches,
vibration motors, speakers and LEDs.

Three types of memory are provided on the DS2760 for battery information storage: EEPROM, lockable
EEPROM and SRAM. EEPROM memory saves important battery data in true nonvolatile memory that
is unaffected by severe battery depletion, accidental shorts or ESD events. Lockable EEPROM becomes
ROM when locked to provide additional security for unchanging battery data. SRAM provides
inexpensive storage for temporary data.

DS2760

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DETAILED PIN DESCRIPTION Table 1

SYMBOL

DESCRIPTION

Charge Protection Control Output. Controls an external p-channel high-side charge
protection FET.

Discharge Protection Control Output. Controls an external p-channel high-side
discharge protection FET.

Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the
DATA terminal of the battery pack. Pin has an internal 1

A pull-down for sensing

disconnection.

PIO

Programmable I/O Pin. Used to control and monitor user-defined external circuitry.
Open drain to VSS.

PLS

Battery Pack Positive Terminal Input. The device monitors the state of the battery
pack's positive terminal through this pin in order to detect events such as the attachment
of a charger or the removal of a short circuit.

Power Switch Sense Input. The device wakes up from Sleep Mode when it senses the
closure of a switch to VSS on this pin. Pin has an internal 1

A pull-up.

VIN

Voltage Sense Input. The voltage of the Li-Ion cell is monitored via this input pin.

VDD

Power Supply Input. Connect to the positive terminal of the Li-Ion cell through a
decoupling network.

VSS

Device Ground. Connect directly to the negative terminal of the Li-Ion cell. For the
external sense resistor configuration, connect the sense resistor between VSS and SNS.

SNS

Sense Resistor Connection. Connect to the negative terminal of the battery pack. In the
internal sense resistor configuration, the sense resistor is connected between VSS and
SNS.

IS1

Current Sense Input. This pin is internally connected to VSS through a 4.7 k

resistor.

Connect a 0.1

F capacitor between IS1 and IS2 to complete a low-pass input filter.

IS2

Current Sense Input. This pin is internally connected to SNS through a 4.7 k

resistor.

DS2760

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POWER MODES

The DS2760 has two power modes: Active and Sleep. While in Active Mode, the DS2760 continually
measures current, voltage and temperature to provide data to the host system and to support current
accumulation and Li-ion safety monitoring. In Sleep Mode, the DS2760 ceases these activities. The
DS2760 enters Sleep Mode when either of the following conditions occurs:

the PMOD bit in the Status Register has been set to 1 and the DQ line is low for
longer than 2 seconds (pack disconnection)

the voltage on VIN drops below undervoltage threshold V

for t

UVD

(cell depletion)

the pack is disabled through the issuance of a SWAP command (SWEN bit =1)

The DS2760 returns to Active Mode when any of the following occurs:

the PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled
high (pack connection)

the

pin is pulled low (power switch)

the voltage on PLS becomes greater than the voltage on VIN (charger connection) with the
SWEN bit set to 0

the pack is enabled through the issuance of a SWAP command (SWEN bit =1)

The DS2760 defaults to Active Mode when power is first applied.

LI-ION PROTECTION CIRCUITRY

During Active Mode, the DS2760 constantly monitors cell voltage and current to protect the battery from
overcharge (overvoltage), overdischarge (undervoltage) and excessive charge and discharge currents
(overcurrent, short circuit). Conditions and DS2760 responses are described in the sections below and
summarized in Table 2 and Figure 3.

LI-ION PROTECTION CONDITIONS AND DS2760 RESPONSES Table 2

Activation

Condition
Name

Threshold

Delay

Response

Release

Threshold

Overvoltage

> V

OVD

high

< V

Undervoltage

< V

UVD

high,

Sleep Mode

PLS

> VDD

(charger connected)

Overcurrent, Charge

> V

(1)

OCD

high

PLS

< VDD - V

(2)

Overcurrent, Discharge

< -V

(1)

OCD

high

PLS

> VDD - V

(3)

Short Circuit

SNS

> V

SCD

high

PLS

> VDD - V

(3)

= V

IS1

IS2

. Logic high = V

PLS

for

and VDD for

All voltages are with respect to VSS. I

SNS

references current delivered from pin SNS.

(1)

for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of
current: I

SNS

> I

for charge direction and I

SNS

< -I

for discharge direction

(2) with test current I

TST

current flowing from PLS to VSS (pull-down on PLS)

(3) with test current I

TST

current flowing from VDD to PLS (pull-up on PLS)

Overvoltage. If the voltage of the cell exceeds overvoltage threshold V

for a period longer than

overvoltage delay t

OVD

, the DS2760 shuts off the external charge FET and sets the OV flag in the

Protection Register. When the cell voltage falls below charge enable threshold V

, the DS2760 turns the

charge FET back on (unless another protection condition prevents it). Discharging remains enabled
during overvoltage.

DS2760

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Undervoltage. If the voltage of the cell drops below undervoltage threshold V

for a period longer than

undervoltage delay t

UVD

, the DS2760 shuts off the charge and discharge FETs, sets the UV flag in the

Protection Register, and enters Sleep Mode.

Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (V

= V

IS1

IS2

) is the filtered voltage drop across the current sense resistor. If V

exceeds overcurrent threshold

for a period longer than overcurrent delay t

OCD

, the DS2760 shuts off both external FETs and sets the

COC flag in the Protection Register. The charge current path is not re-established until the voltage on the
PLS pin drops below VDD V

. The DS2760 provides a test current of value I

TST

from PLS to VSS to

pull PLS down when the offending charge current source has been removed.

Overcurrent, Discharge Direction. If V

is less than -V

for a period longer than t

OCD

, the DS2760

shuts off the external discharge FET and sets the DOC flag in the Protection Register. The discharge
current path is not re-established until the voltage on PLS rises above VDD - V

. The DS2760 provides

a test current of value I

TST

from VDD to PLS to pull PLS up when the offending low-impedance load has

been removed.

Short Circuit. If the voltage on the SNS pin with respect to VSS exceeds short circuit threshold V

for

a period longer than short circuit delay t

SCD

, the DS2760 shuts off the external discharge FET and sets the

DOC flag in the Protection Register. The discharge current path is not re-established until the voltage on
PLS rises above VDD - V

. The DS2760 provides a test current of value I

TST

from VDD to PLS to pull

PLS up when the short circuit has been removed.

LITHIUM-ION PROTECTION CIRCUITRY EXAMPLE WAVEFORMS Figure 3

(1) To allow the device to react quickly to short circuits, detection is actually done on the SNS pin rather

than on the filtered IS1 and IS2 pins. The actual short circuit detect condition is V

SNS

> V

Sleep

Mode

CELL

charge

discharge

-V

SCD

OCD

UVD

OVD

PLS

VDD

active

VSS

inactive

OVD

(1)

DS2760

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Summary. All of the protection conditions described above are OR'ed together to affect the

and

outputs.

= (Undervoltage) or (Overcurrent, EITHER Direction) or (Short Circuit) or

(Protection Register bit DE = 0) or (Sleep Mode)

= (Overvoltage) or (Overcurrent, Charge Direction) or (Protection Register bit CE = 0) or

(Sleep Mode)

CURRENT MEASUREMENT

In the Active Mode of operation, the DS2760 continually measures the current flow into and out of the
battery by measuring the voltage drop across a current sense resistor. The DS2760 is available in two
configurations: (1) internal 25 m

current sense resistor, and (2) external user-selectable sense resistor. In

either configuration, the DS2760 considers the voltage difference between pins IS1 and IS2 (V

= V

IS1

IS2

) to be the filtered voltage drop across the sense resistor. A positive V

value indicates current is

flowing into the battery (charging), while a negative V

value indicates current is flowing out of the

battery (discharging). Note than when an external sense resistor is used, one end of the resistor must be
wired directly to VSS (the negative terminal of the cell) for proper operation of the current measurement
circuitry.

is measured with a signed resolution of 12-bits. Measurements are placed in the Current Register in

two's-complement format. Currents outside the range of the register are reported at the limit of the range.
The format of the Current Register is shown in Figure 4.

For the internal sense resistor configuration, the DS2760 maintains the Current Register in units of Amps,
with a resolution of 0.625 mA and full scale range of no less than

1.8A (see Note 7 on I

spec for more

details). The DS2760 automatically compensates for internal sense resistor process variations and
temperature effects when reporting current.

For the external sense resistor configuration, the DS2760 writes the measured V

voltage to the Current

V and a full scale range of

64 mV.

CURRENT REGISTER FORMAT  Figure 4

MSB--Address 0E

LSB--Address 0F

MSb

LSb

MSb

LSb

Units: 0.625 mA for internal sense resistor

15.625

V for external sense resistor

CURRENT ACCUMULATOR

The Current Accumulator facilitates remaining capacity estimation by tracking the net current flow into
and out of the battery. Current flow into the battery increments the Current Accumulator while current
flow out of the battery decrements it. Data is maintained in the Current Accumulator in two's-
complement format. The format of the Current Accumulator is shown in Figure 5.

DS2760

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When the internal sense resistor is used, the DS2760 maintains the Current Accumulator in units of Amp-
hours, with a resolution of 0.25 mAhrs and full scale range of

8.2 Ahrs. When using an external sense

resistor, the DS2760 maintains the Current Accumulator in units of Volt-hours, with a resolution of
6.25

Vhrs and a full scale range of

205 mVhrs.

The Current Accumulator is a read/write register that can be altered by the host system as needed.

CURRENT ACCUMULATOR FORMAT  Figure 5

MSB--Address 10

LSB--Address 11

MSb

LSb

MSb

LSb

Units: 0.25 mAhrs for internal sense resistor

6.25

Vhrs for external sense resistor

CURRENT OFFSET COMPENSATION

CURRENT MEASUREMENT and the CURRENT ACCUMULATION are both internally compensated
for offset on a continual basis minimizing error resulting from variations in device temperature and
voltage. Additionally a constant bias may be utilized to alter any other sources of offset. This bias resides
in EEPROM address 33h in two's-complement format and is subtracted from each current measurement.

CURRENT OFFSET BIAS  Figure 6

Address 33

MSb

LSb

Units: 0.625 mA for internal sense resistor

15.625

V for external sense resistor

VOLTAGE MEASUREMENT

The DS2760 continually measures the voltage between pins VIN and VSS over a range of 0 to 5-volts.
The resulting data is placed in the Voltage Register in two's-complement format with a resolution of
4.88 mV. Voltages above the maximum register value are reported as the maximum value. The Voltage
Register format is shown in Figure 7.

VOLTAGE REGISTER FORMAT  Figure 7

MSB--Address 0C

LSB--Address 0D

MSb

LSb

MSb

LSb

Units: 4.88 mV

DS2760

10 of 25

TEMPERATURE MEASUREMENT

The DS2760 uses an integrated temperature sensor to continually measure battery temperature.
Temperature measurements are placed in the Temperature Register in two's-complement format with a
resolution of 0.125°C over a range of

127°C. The Temperature Register format is shown in Figure 8.

TEMPERATURE REGISTER FORMAT  Figure 8

MSB--Address 18

LSB--Address 19

MSb

LSb

MSb

LSb

Units: 0.125

PROGRAMMABLE I/O

To use the PIO pin as an output, write the desired output value to the PIO bit in the Special Feature
Register. Writing a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to VSS. Writing a
1 to the PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To
sense the value on the PIO pin, read the PIO bit. The DS2760 turns off the PIO output driver when in
enters Sleep Mode or when DQ is low for more than 2 seconds, regardless of the state of the PMOD bit.

POWER SWITCH INPUT

The DS2760 provides a power control function that uses the discharge protection FET to gate battery
power to the system. The

pin, internally pulled to VDD through a 1

A current source, is

continuously monitored for a low-impedance connection to VSS. If the DS2760 is in Sleep Mode, the
detection of a low on

causes the device to transition into Active Mode, turning on the discharge FET.

If the DS2760 is already in Active Mode, activity on

has no effect other than the mirroring of its logic

level in the

bit in the Special Feature Register.

MEMORY

The DS2760 has a 256-byte linear address space with registers for instrumentation, status and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general-purpose except addresses 30h, 31h, and 33h,
which should be written with the default values for the Protection Register, Status Register, and Current
Offset Register, respectively. When the MSB of any 2 byte register is read, both the MSB and LSB are
latched and held for the duration of the Read Data command to prevent updates during the read and
ensure synchronization between the two register bytes. For consistent results, always read the MSB and
the LSB of a two-byte register during the same Read Data command sequence.

EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the Write Data
command updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The
Copy Data command copies the contents of shadow RAM to EEPROM in an unlocked block of
EEPROM but has no effect on locked blocks. The Recall Data command copies the contents of a block of
EEPROM to shadow RAM regardless of whether the block is locked or not.

DS2760

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MEMORY MAP  Table 3

Address (Hex)

Description

Read/Write

Protection Register

R/W

Status Register

02-06

Reserved

EEPROM Register

R/W

Special Feature Register

R/W

09-0B

Reserved

Voltage Register MSB

Voltage Register LSB

Current Register MSB

Current Register LSB

Accumulated Current Register MSB

R/W

Accumulated Current Register LSB

R/W

12-17

Reserved

Temperature Register MSB

Temperature Register LSB

1A-1F

Reserved

20-2F

EEPROM, block 0

R/W*

30-3F

EEPROM, block 1

R/W*

40-7F

Reserved

80-8F

SRAM

R/W

90-FF

Reserved

Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.

PROTECTION REGISTER

The Protection Register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, COC and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The default
values of the CE and DE bits of the Protection Register are stored in lockable EEPROM in the
corresponding bits in address 30h. A Recall Data command for EEPROM block 1 recalls the default
values into CE and DE. The format of the Protection Register is shown in Figure 9. The function of each
bit is described in detail in the following paragraphs.

PROTECTION REGISTER FORMAT Figure 9

Address 00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

COC

DOC

OV  Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage
condition. This bit must be reset by the host system.

UV Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
undervoltage condition. This bit must be reset by the host system.

DS2760

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COC Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
charge-direction overcurrent condition. This bit must be reset by the host system.

DOC Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
discharge-direction overcurrent condition. This bit must be reset by the host system.

CC CC

Pin Mirror. This read-only bit mirrors the state of the CC

output pin.

DC DC Pin Mirror. This read-only bit mirrors the state of the DC

output pin.

CE Charge Enable. Writing a 0 to this bit disables charging ( CC

output high, external charge FET off)

regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2760 automatically sets this bit to 1 when it transitions
from Sleep Mode to Active Mode.

DE Discharge Enable. Writing a 0 to this bit disables discharging ( DC output high, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2760 automatically sets this bit to 1 when
it transitions from Sleep Mode to Active Mode.

STATUS REGISTER

The default values for the Status Register bits are stored in lockable EEPROM in the corresponding bits
of address 31h. A Recall Data command for EEPROM block 1 recalls the default values into the Status
Register bits. The format of the Status Register is shown in Figure 10. The function of each bit is
described in detail in the following paragraphs.

STATUS REGISTER FORMAT  Figure 10

Address 01

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PMOD

RNAOP

SWEN

PMOD Sleep Mode Enable. A value of 1 in this bit enables the DS2760 to enter Sleep Mode when the
DQ line goes low for greater than 2 seconds and leave Sleep Mode when the DQ line goes high. A value
of 0 disables DQ-related transitions into and out of Sleep Mode. This bit is read-only. The desired
default value should be set in bit 5 of address 31h.

RNAOP Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address
command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should
be set in bit 4 of address 31h.

SWEN - SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP
command. If set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of
address 31h. This bit is read-only.

X Reserved bits.

DS2760

13 of 25

EEPROM REGISTER

The format of the EEPROM Register is shown in Figure 11. The function of each bit is described in
detail in the following paragraphs.

EEPROM REGISTER FORMAT Figure 11

Address 07

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EEC

LOCK

BL1

BL0

EEC EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data command is in
progress. While this bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that
data may be written to unlocked EEPROM blocks.

LOCK EEPROM Lock Enable. When this bit is 0, the Lock command is ignored. Writing a 1 to this
bit enables the Lock command. After the Lock command is executed, the LOCK bit is reset to 0.

BL1  EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM Block 1
(addresses 30-3F) is locked (read-only) while a 0 indicates Block 1 is unlocked (read/write).

BL0  EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM Block 0
(addresses 20-2F) is locked (read-only) while a 0 indicates Block 0 is unlocked (read/write).

X Reserved bits.

SPECIAL FEATURE REGISTER

The format of the Special Feature Register is shown in Figure 12. The function of each bit is described in
detail in the following paragraphs.

SPECIAL FEATURE REGISTER FORMAT Figure 12

Address 08

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PIO

MSTR

PS PS Pin Mirror. This read-only bit mirrors the state of the PS pin.

PIO  PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.

MSTR - SWAP Master status bit. This bit indicates whether a device has been selected through the
SWAP command. Selection of this device through the SWAP command and the appropriate Net Address
will result in setting this bit, indicating that this device is the master. A 0 signifies that this device is not
the master.

X Reserved bits.

DS2760

14 of 25

1-WIRE BUS SYSTEM

The 1-Wire bus is a system which has a single bus master and one or more slaves. A multi-drop bus is a
1-Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the
DS2760 is a slave device. The bus master is typically a microprocessor in the host system. The
discussion of this bus system consists of four topics: 64-Bit Net Address, Hardware Configuration,
Transaction Sequence, and 1-Wire Signaling.

64-BIT NET ADDRESS

Each DS2760 has a unique, factory-programmed 1-Wire net address which is 64 bits in length. The first
8 bits are the 1-Wire family code (30h for DS2760). The next 48 bits are a unique serial number. The
last 8 bits are a CRC of the first 56 bits (see Figure 13). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2760 to communicate via the 1-Wire protocol detailed in the
1-Wire Bus System section of this datasheet.

1-WIRE NET ADDRESS FORMAT  Figure 13

8-bit CRC

48-bit Serial Number

8-Bit Family
Code (30h)

MSb

LSb

CRC GENERATION

The DS2760 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure
error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of
the address and compare it to the CRC from the DS2760. The host system is responsible for verifying the
CRC value and taking action as a result. The DS2760 does not compare CRC values and does not
prevent a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC
can result in a communication channel with a very high level of integrity.

The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as
shown in Figure 10, or it can be generated in software. Additional information about the Dallas 1-Wire
Cyclic Redundancy Check is available in Application Note 27 entitled "Understanding and Using Cyclic
Redundancy Checks with Dallas Semiconductor Touch Memory Products".

In the circuit in Figure 14, the shift register bits are initialized to 0. Then, starting with the least
significant bit of the family code, one bit at a time is shifted in. After the 8

bit of the family code has

been entered, then the serial number is entered. After the 48

bit of the serial number has been entered,

the shift register contains the CRC value.

DS2760

15 of 25

1-WIRE CRC GENERATION BLOCK DIAGRAM  Figure 14

HARDWARE CONFIGURATION

Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2760 used an open-drain output driver as part of
the bi-directional interface circuitry shown in Figure 15. If a bi-directional pin is not available on the bus
master, separate output and input pins can be tied together.

The 1-Wire bus must have a pull-up resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5 k

. The idle state for the 1-Wire bus is high. If, for any

reason, a bus transaction must be suspended, the bus MUST be left in the idle state in order to properly
resume the transaction later. If the bus is left low for more than 120

s, slave devices on the bus begin to

interpret the low period as a Reset Pulse, effectively terminating the transaction.

1-WIRE BUS INTERFACE CIRCUITRY  Figure 15

TRANSACTION SEQUENCE

The protocol for accessing the DS2760 via the 1-Wire port is as follows:

Initialization

Net Address Command

Function Command

Transaction/Data

The sections that follow describe each of these steps in detail.

Typ.

100 OHM
MOSFET

Rx = Receive
Tx = Transmit

+5V

4.7K

BUS MASTER

DS2760 1-WIRE PORT

MSb

XOR

LSb

XOR

input

DS2760

16 of 25

All transactions of the 1-Wire bus begin with an initialization sequence consisting of a Reset Pulse
transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2760
and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on
the bus and ready to operate. For more details, see the 1-Wire Signaling section.

NET ADDRESS COMMANDS

Once the bus master has detected the presence of one or more slaves, it can issue one of the Net Address
Commands described in the following paragraphs. The name of each ROM Command is followed by the
8-bit opcode for that command in square brackets. Figure 16 presents a transaction flowchart of the Net
Address Commands.

Read Net Address [33h or 39h]. This command allows the bus master to read the DS2760's 1-Wire net
address. This command can only be used if there is a single slave on the bus. If more than one slave is
present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a
wired-AND result). The RNAOP bit in the Status Register selects the opcode for this command, with
RNAOP=0 indicating 33h and RNAOP=1 indicating 39h.

Match Net Address [55h]. This command allows the bus master to specifically address one DS2760 on
the 1-Wire bus. Only the addressed DS2760 responds to any subsequent Function Command. All other
slave devices ignore the Function Command and wait for a reset pulse. This command can be used with
one or more slave devices on the bus.

Skip Net Address [CCh]. This command saves time when there is only one DS2760 on the bus by
allowing the bus master to issue a Function Command without specifying the address of the slave. If
more than one slave device is present on the bus, a subsequent Function Command can cause a data
collision when all slaves transmit data at the same time.

Search Net Address [F0h]. This command allows the bus master to use a process of elimination to
identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the
repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple three-step routine on each bit location of the net
address. After one complete pass through all 64 bits, the bus master knows the address of one device.
The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the
Book of DS19xx iButtonTM Standards for a comprehensive discussion of a net address search, including
an actual example.

SWAP [AAh]. SWAP is a Net Address level command specifically intended to aid in distributed
multiplexing applications and is described specifically with regards to power control using the 27xx series
of products. The term power control refers to the ability of the DS2760 to control the flow of power into
or out the battery pack using control pins DC

and CC . The SWAP command is issued followed by the

Net Address. The effect is to cause the addressed device to enable power to or from the system while
simultaneously (break-before-make) deselecting and powering down (SLEEP) all other packs. This
switching sequence is controlled by a timing pulse issued on the DQ line following the Net Address. The
falling edge of the pulse is used to disable power with the rising edge enabling power flow by the selected
device. The DS2760 will recognize a SWAP command, device address and, timing pulse if and only if
the SWEN bit is set.

DS2760

17 of 25

FUNCTION COMMANDS

After successfully completing one of the Net Address Commands, the bus master can access the features
of the DS2760 with any of the Function Commands described in the following paragraphs. The name of
each function is followed by the 8-bit opcode for that command in square brackets.

Read Data [69h, XX]. This command reads data from the DS2760 starting at memory address XX. The
LSb of the data in address XX is available to be read immediately after the MSb of the address has been
entered. Because the address is automatically incremented after the MSb of each byte is received, the
LSb of the data at address XX+1 is available to be read immediately after the MSb of the data at address
XX. If the bus master continues to read beyond address FFh, the DS2760 outputs logic 1 until a Reset
Pulse occurs. Addresses labeled "Reserved" in the Memory Map contain undefined data. The Read Data
command may be terminated by the bus master with a Reset Pulse at any bit boundary.

Write Data [6Ch, XX]. This command writes data to the DS2760 starting at memory address XX. The
LSb of the data to be stored at address XX can be written immediately after the MSb of address has been
entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb
to be stored at address XX+1 can be written immediately after the MSb to be stored at address XX. If the
bus master continues to write beyond address FFh, the DS2760 ignores the data. Writes to read-only
addresses, reserved addresses and locked EEPROM blocks are ignored. Incomplete bytes are not written.
Writes to unlocked EEPROM blocks are to shadow RAM rather than EEPROM. See the Memory section
for more details.

Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 16-byte
EEPROM block containing address XX. Copy Data commands that address locked blocks are ignored.
While the Copy Data command is executing, the EEC bit in the EEPROM Register is set to 1 and writes
to EEPROM addresses are ignored. Reads and writes to non-EEPROM addresses can still occur while
the copy is in progress. The Copy Data command takes t

EEC

time to execute, starting on the next falling

edge after the address is transmitted.

Recall Data [B8h, XX]. This command recalls the contents of the 16-byte EEPROM block containing
address XX to shadow RAM.

Lock [6Ah, XX]. This command locks (write-protects) the 16-byte block of EEPROM memory
containing memory address XX. The LOCK bit in the EEPROM Register must be set to l before the
Lock command is executed. If the LOCK bit is 0, the Lock command has no effect. The Lock command
is permanent; a locked block can never be written again.

DS2760

19 of 25

NET ADDRESS COMMAND FLOW CHART  Figure 16

MASTER Tx

RESET PULSE

DS2760 Tx

PRESENCE PULSE

MASTER Tx

NET ADDRESS

COMMAND

55h

MATCH

33h / 39h

READ

F0h

CCh

SKIP

DS2760 Tx

FAMILY CODE

1 BYTE

DS2760 Tx

SERIAL NUMBER

6 BYTES

DS2760 Tx

CRC

1 BYTE

MASTER Tx

BIT 0

MATCH ?

MASTER Tx

BIT 1

DS2760 Tx BIT 0

MASTER Tx BIT 0

BIT 0

MATCH ?

DS2760 Tx BIT 1

MASTER Tx BIT 1

BIT 1

MATCH ?

BIT 1

MATCH ?

MASTER Tx

FUNCTION

COMMAND

MASTER Tx

BIT 63

DS2760 Tx BIT 63

MASTER Tx BIT 63

BIT 63

MATCH ?

MASTER Tx

FUNCTION

COMMAND

YES

AAh

SWAP

YES

MASTER Tx

BIT 0

MATCH ?

MASTER Tx

BIT 1

MATCH ?

MASTER Tx

BIT 63

MATCH ?

YES

DS2760 to Sleep

Mode

FALLING EDGE

OF DQ

DS2760 to Active

Mode

RISING EDGE

OF DQ

DS2760

20 of 25

I/O SIGNALING

The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2760 are: the initialization sequence (Reset Pulse followed by Presence Pulse), Write 0, Write 1, and
Read Data. All of these types of signaling except the Presence Pulse are initiated by the bus master.

The initialization sequence required to begin any communication with the DS2760 is shown in Figure 17.
A Presence Pulse following a Reset Pulse indicates the DS2760 is read to accept a Net Address
Command. The bus master transmits (Tx) a Reset Pulse for t

RSTL

. The bus master then releases the line

and goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pull-up resistor. After
detecting the rising edge on the DQ pin, the DS2760 waits for t

PDH

and then transmits the Presence Pulse

for t

PDL

1-WIRE INITIALIZATION SEQUENCE  Figure 17

WRITE TIME SLOTS

A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to
a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must
be t

SLOT

(60 to 120

s) in duration with a 1

s minimum recovery time, t

REC

, between cycles. The

DS2760 samples the 1-Wire bus line between 15 and 60

s after the line falls. If the line is high when

sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 18). For the bus
master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15

s after the start of the write time slot. For the host to generate a Write 0 time

slot, the bus line must be pulled low and held low for the duration of the write time slot.

READ TIME SLOTS

A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to a
logic low level. The bus master must keep the bus line low for at least 1

s and then release it to allow

the DS2760 to present valid data. The bus master can then sample the data t

RDV

(15

s) from the start of

the read time slot. By the end of the read time slot, the DS2760 releases the bus line and allows it to be
pulled high by the external pull-up resistor. All read time slots must be t

SLOT

(60 to 120

s) in duration

with a 1

s minimum recovery time, t

REC

, between cycles. See Figure 18 for more information.

RSTL

PDL

RSTH

PDH

PACK+

PACK

LINE TYPE LEGEND:

Bus master active low

DS2760 active low

Resistor pullup

Both bus master and
DS2760 active low

DS2760

22 of 25

ABSOLUTE MAXIMUM RATINGS*

Voltage on PLS and CC pin, Relative to VSS

-0.3V to +18V

Voltage on PIO pin, Relative to VSS

-0.3V to +12V

Voltage on any other pin, Relative to VSS

-0.3V to +6V

Continuous Internal Sense Resistor Current

2.5A

Pulsed Internal Sense Resistor Current

50A for <100 ľs/sec, <1000 pulses

Operating Temperature

-40°C to +85°C

Storage Temperature

-55°C to +125°C

Soldering Temperature

See J-STD-020A Specification

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC
OPERATING CONDITIONS

(-20

C to 70

C, 2.5V

VDD

5.5V)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

NOTES

Supply Voltage

VDD

2.5

5.5

Data Pin

-0.3

5.5

DC ELECTRICAL CHARACTERISTICS

(-20

C to 70

C; 2.5V

VDD

5.5V)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

NOTES

Active Current

ACTIVE

DQ=VDD,

norm. operation

Sleep Mode Current

SLEEP

DQ=0V,

no activity,

floating

Input Logic High:
DQ, PIO

1.5

Input Logic High:

-0.2V

Input Logic Low:
DQ, PIO

0.4

Input Logic Low:

0.2

Output Logic High:

=-0.1 mA

PLS

-0.4V

Output Logic High:

=-0.1 mA

VDD-0.4V

Output Logic Low:

=0.1 mA

0.4

Output Logic Low:
DQ, PIO

=4 mA

0.4

Input Resistance: DQ

500

Input Resistance: VIN

Internal Current Sense
Resistor

SNS

Internal Current Sense
Resistor TC

SNS

4000

ppm/

Internal Kelvin Sense
Resistance

IS1 to VSS
IS2 to SNS

4.7

DQ Low to Sleep time

SLEEP

sec

DS2760

23 of 25

ELECTRICAL CHARACTERISTICS:
PROTECTION CIRCUITRY

(-20

C to 70

C; 2.5V

VDD

5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Overvoltage Detect

4.300
4.225

4.350
4.275

4.400
4.325

1,2

Charge Enable

4.05

4.15

4.25

Undervoltage Detect

2.5

2.6

2.7

Overcurrent Detect

1.8

1.9

2.0

Overcurrent Detect

47.5

1,4

Short Circuit Detect

100

150

200

Overvoltage Delay

OVD

0.8

1.2

sec

Undervoltage Delay

UVD

100

110

Overcurrent Delay

OCD

Short Circuit Delay

SCD

100

120

Test Threshold

0.5

1.0

1.5

Test Current

TST

DS2760

24 of 25

ELECTRICAL CHARACTERISTICS:
TEMPERATURE, VOLTAGE, CURRENT

(-20

C to 70

C; 2.5V

VDD

5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Temperature Resolution

LSB

0.125

Temperature Full Scale
Magnitude

127

Temperature Error

ERR

Voltage Resolution

LSB

4.88

Voltage Full Scale
Magnitude

Voltage Offset Error

OERR

LSB

Voltage Gain Error

GERR

reading

Current Resolution

LSB

0.625

15.625

3
4

Current Full Scale
Magnitude

1.8

2.56

3, 4

Current Offset Error

OERR

LSB

Current Gain Error

GERR

reading

Accumulated Current
Resolution

0.25
6.25

mAhr

ľVhr

3
4

Current Sampling
Frequency

SAMP

1456

Internal Timebase Accuracy

ERR

ELECTRICAL CHARACTERISTICS:
COPY TO EEPROM

(-20

C to 70

C; 2.5V

VDD

5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Copy to EEPROM Time

EEC

EEPROM Copy Endurance

EEC

25000

cycles

DS2760

25 of 25

ELECTRICAL CHARACTERISTICS:
1-WIRE INTERFACE

(-20

C to 70

C; 2.5V

VDD

5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Time Slot

SLOT

120

Recovery Time

REC

Write 0 Low Time

LOW0

120

Write 1 Low Time

LOW1

Read Data Valid

RDV

Reset Time High

RSTH

480

Reset Time Low

RSTL

480

960

Presence Detect High

PDH

Presence Detect Low

PDL

240

SWAP timing pulse width

SWL

0.2

480

SWAP timing pulse
falling edge to DC release

SWOFF

SWAP timing pulse rising
edge to DC engage

SWON

DQ Capacitance

NOTES

All voltages are referenced to VSS.

See "Ordering Information" section of datasheet to determine corresponding part number for each
V

value.

Internal current sense resistor configuration.

External current sense resistor configuration.

Self heating due to output pin loading and sense resistor power dissipation can alter the reading from
ambient conditions.

Voltage offset measurement is with respect to V

at 25°C.

Although the Current Register is large enough to report values higher than 1.8A, internal
compensation for sense resistor process variation and temperature effects can reduce the maximum
reportable current to as low as 1.8A.

Requires in-system calibration by user.

This spec excludes the effects of temperature on the sense resistor. The DS2760 compensates for the
internal sense resistor's temperature coefficient of 4000 ppm/

C to an accuracy of

500 ppm/

C. The

DS2760 does not attempt to compensate for the characteristics of an external sense resistor. Error
terms arising from the use of an external sense resistor should be taken into account when calculating
total current measurement error.

10.

Typical value for t

ERR

is at 3.6V and 25

11.

4 year data retention at 70

12.

Typical load capacitance on DC

and CC is 100 pF.

Part Number DS2760