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072401

FEATURES

§ Integrates NV SRAM, real-time clock,

crystal, power-fail control circuit and lithium
energy source

§ Clock registers are accessed identically to the

static RAM. These registers are resident in
the eight top RAM locations

§ Totally nonvolatile with over 10 years of

operation in the absence of power

§ BCD coded year, month, date, day, hours,

minutes, and seconds with leap year
compensation valid up to 2100

§ Power-fail write protection allows for ±10%

power supply tolerance

§ DS1647 only (DIP Module)

- Standard JEDEC byte-wide 128k x 8

RAM pinout

§ DS1647P only (PowerCap

Module Board)

- Surface mountable package for direct

connection to PowerCap containing
battery and crystal

- Replaceable battery (PowerCap)

- Power-fail output

Pin-for-pin compatible with other
densities of DS164XP Timekeeping
RAM

ORDERING INFORMATION

DS1647

32-pin DIP module

*DS1647P

34-pin PowerCap Module
Board

*DS9034PCX

PowerCap (Required; must
be ordered separately)

PIN ASSIGNMENT

DS1647/DS1647P

Nonvolatile Timekeeping RAM

www.maxim-ic.com

A15

A16

PFO

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

A17

A14

A13

A12

A11

A10

A18

X1 GND V

BAT

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

1
2
3
4
5
6
7
8
9
10
11
12

32-Pin Encapsulated Package

A14

A5
A4
A3
A2
A1
A0

DQ1

DQ0

A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7

DQ5

DQ6

30
29
28
27
26
25
24
23
22
21

A16

A12

A18

DQ2

GND

15
16

18
17

DQ4
DQ3

DS1647/DS1647P

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PIN DESCRIPTION

A0-A18

- Address Input

- Chip Enable

- Output Enable

- Write Enable

+5V

GND -

Ground

DQ0-DQ7 -

Data

Input/Output

- No Connection

PFO

- Power-fail Output
(DS1647P only)

X1, X2

- Crystal Connection

BAT

- Battery Connection

DESCRIPTION

The DS1647 is a 512k x 8 nonvolatile static RAM with a full-function real-time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 512k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real-time clock function. The real-
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1647
also contains its own power-fail circuitry, which deselects the device when the V

supply is in an out-of-

tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low V

as errant access and update cycles are avoided.

PACKAGES

The DS1647 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1647P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

CLOCK OPERATIONS - READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1647 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that clock accuracy is not
affected by the access of data. All of the DS1647 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.

DS1647/DS1647P

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BLOCK DIAGRAM DS1647 Figure 1

TRUTH TABLE DS1647 Table 1

MODE

POWER

DESELECT

HIGH-Z

STANDBY

DESELECT

HIGH-Z

STANDBY

WRITE

DATA IN

ACTIVE

READ

DATA OUT

ACTIVE

± 10%

READ

HIGH-Z

ACTIVE

<4.5V >V

BAT

DESELECT

HIGH-Z

CMOS STANDBY

BAT

DESELECT

HIGH-Z

DATA RETENTION

MODE

SETTING THE CLOCK

The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts
updates to the DS1647 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The

OSC

bit is the MSB for the second's registers. Setting it

to a 1 stops the oscillator.

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the second's register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e.,

low,

low, and address for seconds register remain valid and stable).

DS1647/DS1647P

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CLOCK ACCURACY (DIP MODULE)

The DS1647 is guaranteed to keep time accuracy to within

±1 minute per month at 25°C. The RTC is

calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1647 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within

±1.53 minutes per month (35 ppm) at 25°C. Clock

accuracy is also effected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application
note 58.

1646 REGISTER MAP - BANK1 Table 2

DATA

ADDRESS

FUNCTION

7FFFF

YEAR

00-99

7FFFE

MONTH

01-12

7FFFD

DATE

01-31

7FFFC

DAY

01-07

7FFFB

HOUR

00-23

7FFFA

MINUTES

00-59

7FFF9

OSC

SECONDS

00-59

7FFF8

CONTROL

OSC

= STOP BIT

R = READ BIT

FT = FREQUENCY TEST

W = WRITE BIT

X = UNUSED

NOTE:

All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits.

DS1647/DS1647P

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RETRIEVING DATA FROM RAM OR CLOCK

The DS1647 is in the read mode whenever

(write enable) is high;

(chip enable) is low. The

device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid

data will be available at the DQ pins within t

after the last address input is stable, providing that the

and

access times and states are satisfied. If

access times are not met, valid data will be

available at the latter of chip-enable access (t

CEA

) or at output enable access time (t

OEA

). The state of the

data input/output pins (DQ) is controlled by

and

. If the outputs are activated before t

, the data

lines are driven to an intermediate state until t

. If the address inputs are changed while

and

remain valid, output data will remain valid for output data hold time (t

) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1647 is in the write mode whenever

and

are in their active state. The start of a write is

referenced to the latter occurring high to low transition of

and

. The addresses must be held valid

throughout the cycle.

must return inactive for a minimum of t

prior to the initiation of

another read or write cycle. Data in must be valid t

prior to the end of write and remain valid for t

afterward. In a typical application, the

signal will be high during a write cycle. However,

can be

active provided that care is taken with the data bus to avoid bus contention. If

is low prior to

transitioning low the data bus can become active with read data defined by the address inputs. A low

transition on

will then disable the outputs t

WEZ

after

goes active.

DATA RETENTION MODE

When V

is within nominal limits (V

> 4.5 volts) the DS1647 can be accessed as described above with

read or write cycles. However, when V

is below the power-fail point V

(point at which write

protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished

internally by inhibiting access via the

signal. At this time the power-fail output signal (

PFO

) will be

driven active low and will remain active until V

returns to nominal levels. When V

falls below the

level of the internal battery supply, power input is switched from the V

pin to the internal battery and

clock activity, RAM, and clock data are maintained from the battery until V

is returned to nominal

level.

Part Number DS1647