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080299

FEATURES

Real time clock keeps track of hundredths of
seconds, seconds, minutes, hours, days, date
of the month, months, and years

8K x 8 NV SRAM directly replaces volatile
static RAM or EEPROM

Embedded lithium energy cell maintains
calendar operation and retains RAM data

Watch function is transparent to RAM
operation

Month and year determine the number of days
in each month; valid up to 2100

Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time

Standard 28pin JEDEC pinout

Full ą10% operating range

Operating temperature range 0°C to 70°C

Accuracy is better than ą1 minute/month @
25°C

Over 10 years of data retention in the absence
of power

Available in 120, 150 and 200 ns access time

ORDERING INFORMATION

DS1243YXXX

120 120 ns access
150 150 ns access

DS1243Y

200 ns access

PIN ASSIGNMENT

PIN DESCRIPTION

Address Inputs

Chip Enable

GND

Ground

Data In/Data Out

Power (+5V)

Write Enable

Output Enable

No Connect

RST

Reset

DESCRIPTION

The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192
words by 8 bits) with a builtin real time clock. The DS1243Y has a selfcontained lithium energy source
and control circuitry which constantly monitors V

for an outoftolerance condition. When such a

condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent corrupted data in both the memory and real time clock.

DS1243Y

64K NV SRAM with Phantom Clock

www.dalsemi.com

28-Pin Encapsulated Package

720-Mil Extended

A3
A2
A1
A0

DQ0
DQ1

GND

DQ2

WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5

DQ3

DQ4

1
2
3
4
5
6
7
8
9
10
11
12

28
27
26
25
24
23
22
21
20
19
18
17

A12

RST

DS1243Y

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The Phantom Clock provides timekeeping information including hundredths of seconds, seconds,
minutes, hours, day, date, month, and year information. The date at the end of the month is automatically
adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock
operates in either 24hour or 12hour format with an AM/PM indicator.

RAM READ MODE

The DS1243Y executes a read cycle whenever

(Write Enable) is inactive (high) and

(Chip

Enable) is active (low). The unique address specified by the 13 address inputs (A0A12) defines which of
the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers
within t

ACC

(Access Time) after the last address input signal is stable, providing that

and

(Output

Enable) access times and states are also satisfied. If

and

access times are not satisfied, then data

access must be measured from the later occurring signal (

) and the limiting parameter is either

for

or t

for

rather than address access.

RAM WRITE MODE

The DS1243Y is in the write mode whenever the

and

signals are in the active (low) state after

address inputs are stable. The latter occurring falling edge of

will determine the start of the

write cycle. The write cycle is terminated by the earlier rising edge of

. All address inputs must

be kept valid throughout the write cycle.

must return to the high state for a minimum recovery time

) before another cycle can be initiated. The

control signal should be kept inactive (high) during

write cycles to avoid bus contention. However, if the output bus has been enabled (

and

active)

then

will disable the outputs in t

ODW

from its falling edge.

DATA RETENTION MODE

The DS1243Y provides full functional capability for V

greater than V

and write protects by 4.25

volts. Data is maintained in the absence of V

without any additional support circuitry. The nonvolatile

static RAM constantly monitors V

. Should the supply voltage decay, the RAM automatically write

protects itself. All inputs to the RAM become "don't care" and all outputs are high impedance. As V

falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During powerup, when V

rises above approximately 3.0 volts, the power

switching circuit connects external V

to the RAM and disconnects the lithium energy source. Normal

RAM operation can resume after V

exceeds 4.5 volts.

FRESHNESS SEAL

Each DS1243Y is shipped from Dallas Semiconductor with its lithium energy source disconnected,
insuring full energy capacity. When V

is first applied at a level greater than V

, the lithium energy

source is enabled for battery backup operation.

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.

DS1243Y

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Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable (

), Output Enable (

), and Write Enable (

). Initially, a read cycle to any memory

location using the

and

control of the Phantom Clock starts the pattern recognition sequence by

moving a pointer to the first bit of the 64bit comparison register. Next, 64 consecutive write cycles are
executed using the

and

control of the SmartWatch. These 64 write cycles are used only to gain

access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable.
However, the write cycles generated to gain access to the Phantom Clock are also writing data to a
location in the mated RAM. The preferred way to manage this requirement is to set aside just one address
location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared
to bit 0 of the 64bit comparison register. If a match is found, the pointer increments to the next location
of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not
advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern
recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the
Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64
cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of
the

pin or the

pin. Cycles to other locations outside the memory block can be interleaved with

cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom

Clock.

PHANTOM CLOCK
REGISTER INFORMATION

The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.

Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.

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PHANTOM CLOCK REGISTER DEFINITION Figure 2

AMPM/12/24 MODE

Bit 7 of the hours register is defined as the 12 or 24hour mode select bit. When high, the 12hour mode
is selected. In the 12hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24hour mode,
bit 5 is the second 10hour bit (2023 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the

RESET

and oscillator functions. Bit 4 controls the

RESET

(pin 1). When the

RESET

bit is set to logic 1, the

RESET

input pin is ignored. When the

RESET

bit is set to logic 0, a low input on the

RESET

pin will cause the Phantom Clock to abort data transfer

without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.

DS1243Y

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

0.3V to +7.0V

Operating Temperature

C to 70

Storage Temperature

C to +70

Soldering Temperature

260

C for 10 seconds (See Note 13)

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0

C to 70

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Power Supply Voltage

4.5

5.0

5.5

Input Logic 1

2.2

+0.3

Input Logic 0

-0.3

0.8

DC ELECTRICAL CHARACTERISTICS (0

C to 70

C; V

= 5V

10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Leakage Current

-1.0

+1.0

I/O Leakage Current

-1.0

+1.0

Output Current @ 2.4V

-1.0

Output Current @ 0.4V

2.0

Standby Current

= 2.2

CCS1

5.0

Standby Current

= V

0.5V

CCS2

3.0

5.0

Operating Current t

CYC

= 200ns

CC01

Write Protection Voltage

4.25

4.5

DC TEST CONDITIONS

Outputs are open; all voltages are referenced to ground.

CAPACITANCE (t

= 25

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

Input/Output Capacitance

I/O

DS1243Y

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MEMORY AC ELECTRICAL
CHARACTERISTICS (0

C to 70

C; V

= 5.0V

10%)

DS1243Y-120 DS1243Y-150

DS1243Y

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX UNITS

NOTES

Read Cycle Time

120

150

200

Access Time

ACC

120

150

200

to Output Valid

100

to Output Valid

120

150

200

Output Active

COE

Output High Z from
Deselection

100

Output Hold from
Address Change

Write Cycle Time

120

150

200

Write Pulse Width

100

150

Address Setup Time

Write Recovery
Time

Output High Z from

ODW

Output Active from

OEW

Data Setup Time

Data Hold Time
from

AC TEST CONDITIONS

Output Load:

50 pF + 1TTL Gate

Input Pulse Levels:

03V

Timing Measurement Reference Levels
Input:

1.5V

Output:

1.5V

Input Pulse Rise and Fall Times:

5 ns

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PHANTOM CLOCK AC ELECTRICAL
CHARACTERISTICS (0°C to 70°C; V

= 4.5 to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Read Cycle Time

120

Access Time

100

Access Time

100

to Output Low Z

COE

to Output Low Z

OEE

to Output High Z

ODO

Read Recovery

Write Cycle Time

120

Write Pulse Width

100

Write Recovery

Data Setup Time

Data Hold Time

Pulse Width

100

RESET

Pulse Width

RST

200

High to Power-Fail

POWER-DOWN/POWER-UP TIMING

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

at V

before Power-Down

Slew from 4.5V to 0V (

at V

)

300

Slew from 0V to 4.5V (

at V

)

at V

after Power-Up

REC

= 25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Expected Data Retention Time

years

WARNING:

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.

DS1243Y

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NOTES:

is high for a read cycle.

= V

or V

. If

= V

during write cycle, the output buffers remain in a high impedance state.

is specified as the logical AND of

and

. t

is measured from the latter of

going low to the earlier of

going high.

, t

are measured from the earlier of

going high.

These parameters are sampled with a 50 pF load and are not 100% tested.

If the

low transition occurs simultaneously with or later than the

low transition in Write

Cycle 1, the output buffers remain in a high impedance state during this period.

If the

high transition occurs prior to or simultaneously with the

high transition, the output

buffers remain in a high impedance state during this period.

is low or the

low transition occurs prior to or simultaneously with the

low transition,

the output buffers remain in a high impedance state during this period.

The expected t

is defined as cumulative time in the absence of V

with the clock oscillator

running.

10.

is a function of the latter occurring edge of

11.

and t

are a function of the first occurring edge of

12.

RST (Pin1) has an internal pullup resistor.

13.

RealTime Clock Modules can be successfully processed through conventional wavesoldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.

Part Number DS1243Y