DS1232LP/LPS
Low Power MicroMonitor Chip
DS1232LP/LPS
062698 1/7
FEATURES
·
Super low-power version of DS1232
·
50
m
A quiescent current
·
Halts and restarts an outofcontrol microprocessor
·
Automatically restarts microprocessor after power
failure
·
Monitors pushbutton for external override
·
Accurate 5% or 10% microprocessor power supply
monitoring
·
8pin DIP, 8pin SOIC or space saving
µ
SOP pack-
age available
·
Optional 16pin SOIC package available
·
Industrial temperature 40
°
C to +85
°
C available, des-
ignated N
PIN ASSIGNMENT
1
2
3
4
8
7
6
5
V
CC
ST
RST
RST
PBRST
TD
TOL
GND
DS1232LP 8Pin DIP
(300 Mil)
See Mech. Drawings
Section
DS1232LPS 16Pin SOIC
(300 Mil)
See Mech. Drawings
Section
1
2
3
4
5
6
7
8
TD
TOL
GND
PBRST
VCC
ST
RST
RST
DS1232LPS2 8Pin
SOIC
(150 Mil)
See Mech. Drawings
Section
NC
PBRST
NC
TD
NC
TOL
NC
GND
NC
VCC
NC
ST
NC
RST
NC
RST
1
11
12
13
14
2
3
4
5
6
7
8
9
10
15
16
DS1232LP
µ
(118 MIL
µ
SOP)
See Mech. Drawings
Section
V
CC
ST
RST
RST
8
7
6
5
1
2
3
4
PBRST
TD
TOL
GND
PIN DESCRIPTION
PBRST
Pushbutton Reset Input
TD
Time Delay Set
TOL
Selects 5% or 10% V
CC
Detect
GND
Ground
RST
Reset Output (Active High)
RST
Reset Output (Active Low, open drain)
ST
Strobe Input
V
CC
+5 Volt Power
DESCRIPTION
The DS1232LP/LPS Low Power MicroMonitor Chip
monitors three vital conditions for a microprocessor:
power supply, software execution, and external over-
ride. First, a precision temperaturecompensated refer-
ence and comparator circuit monitors the status of V
CC
.
When an outoftolerance condition occurs, an internal
power fail signal is generated which forces reset to the
active state. When V
CC
returns to an in-tolerance condi-
tion, the reset signals are kept in the active state for a
minimum of 250 ms to allow the power supply and pro-
cessor to stabilize.
The second function the DS1232LP/LPS performs is
pushbutton reset control. The DS1232LP/LPS de-
bounces the pushbutton input and guarantees an active
reset pulse width of 250 ms minimum. The third function
is a watchdog timer. The DS1232LP/LPS has an inter-
nal timer that forces the reset signals to the active state if
DS1232LP/LPS
062698 2/7
the strobe input is not driven low prior to timeout. The
watchdog timer function can be set to operate on time-
out settings of approximately 150 ms, 600 ms, and 1.2
seconds.
OPERATION POWER MONITOR
The DS1232LP/LPS detects outoftolerance power
supply conditions and warns a processorbased sys-
tem of impending power failure. When V
CC
falls below a
preset level as defined by TOL, the V
CC
comparator out-
puts the signals RST and RST. When TOL is connected
to ground, the RST and RST signals become active as
V
CC
falls below 4.75 volts. When TOL is connected to
V
CC
, the RST and RST signals become active as V
CC
falls below 4.5 volts. The RST and RST are excellent
control signals for a microprocessor, as processing is
stopped at the last possible moments of valid V
CC
. On
powerup, RST and RST are kept active for a minimum
of 250 ms to allow the power supply and processor to
stabilize.
OPERATION PUSHBUTTON RESET
The DS1232LP/LPS provides an input pin for direct con-
nection to a pushbutton (Figure 1). The pushbutton re-
set input requires an active low signal. Internally, this in-
put is debounced and timed such that RST and RST
signals of at least 250 ms minimum are generated. The
250 ms delay starts as the pushbutton reset input is re-
leased from low level.
OPERATION WATCHDOG TIMER
The watchdog timer function forces RST and RST sig-
nals to the active state when the ST input is not stimu-
lated for a predetermined time period. The time period is
set by the TD input to be typically 150 ms with TD con-
nected to ground, 600 ms with TD left unconnected, and
1.2 seconds with TD connected to V
CC
. The watchdog
timer starts timing out from the set time period as soon
as RST and RST are inactive. If a hightolow transition
occurs on the ST input pin prior to timeout, the watch-
dog timer is reset and begins to timeout again. If the
watchdog timer is allowed to time-out, then the RST and
RST signals are driven to the active state for 250 ms
minimum. The ST input can be derived from micropro-
cessor address signals, data signals, and/or control sig-
nals. When the microprocessor is functioning normally,
these signals would, as a matter of routine, cause the
watchdog to be reset prior to timeout. To guarantee
that the watchdog timer does not timeout, a highto
low transition must occur at or less than the minimum
shown in Table 1. A typical circuit example is shown in
Figure 2.
MICROMONITOR BLOCK DIAGRAM
TOL
T.C. REFERENCE
+
LEVEL SENSE
VOLTAGE
DIGITAL
DIGITAL
RST
TD
TIMEOUT
RST
ST
PBRST
V
CC
V
CC
TOLERANCE
BIAS
AND
DEBOUNCE
SENSE
COMPARATOR
DELAY
SAMPLER
DS1232LP/LPS
062698 3/7
PUSHBUTTON RESET Figure 1
TD
TOL
GND
RST
ALE
RST
8051
RST
ST
PBRST
V
CC
+5 V
DC
+5 V
DC
m
P
DS1232
LP/LPS
WATCHDOG TIMER Figure 2
TD
TOL
GND
RST
Z80
ADDRESS
DECODER
10K
RST
ST
PBRST
MREQ
RST
V
CC
+5 V
DC
DS1232
LP/LPS
BUS
DS1232LP/LPS
062698 4/7
TIMING DIAGRAM: PUSHBUTTON RESET Figure 3
RST
PBRST
RST
V
IH
t
RST
V
IL
t
PDLY
t
PB
V
OH
V
OL
TIMING DIAGRAM: STROBE INPUT Figure 4
RST
INDETERMINATE
STROBE
INVALID
STROBE
MIN.
MAX.
VALID
STROBE
ST
t
TD
WATCHDOG TIMEOUTS Table 1
TIMEOUT
TD
MIN
TYP
MAX
GND
62.5 ms
150 ms
250 ms
Float
250 ms
600 ms
1000 ms
V
CC
500 ms
1200 ms
2000 ms
DS1232LP/LPS
062698 5/7
TIMING DIAGRAM: POWER DOWN Figure 5
t
F
4.75V
V
CCTP
4.25V
t
RPD
V
CC
V
OH
V
OL
RST
RST
TIMING DIAGRAM: POWER UP Figure 6
4.25V
4.75V
V
CCTP
t
R
t
RPU
V
CC
V
OH
V
OL
RST
RST
DS1232LP/LPS
062698 6/7
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Pin Relative to Ground
0.5V to +7.0V
Voltage on I/O Relative to Ground
0.5V to V
CC
+ 0.5V
Operating Temperature
0
°
C to 70
°
C
Operating Temperature (Industrial Version)
40
°
C to +85
°
C
Storage Temperature
55
°
C to +125
°
C
Soldering Temperature
260
°
C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0
°
C to 70
°
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
V
CC
4.5
5.0
5.5
V
1
ST and PBRST Input High Level
V
IH
2.0
V
CC
+0.3
V
1
ST and PBRST Input Low Level
V
IL
0.3
+0.8
V
1
DC ELECTRICAL CHARACTERISTICS
(0
°
C to 70
°
C; V
CC
= 4.5 to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage
I
IL
1.0
+1.0
µ
A
3
Output Current @ 2.4V
I
OH
8
10
mA
5
Output Current @ 0.4V
I
OL
10
mA
Low Level @ RST
V
OL
0.4
V
1
Output Voltage @ 500 uA
V
OH
V
CC
0.5V
V
CC
0.1V
V
1, 7
Operating Current (CMOS)
I
CC1
50
µ
A
2
Operating Current (TTL)
I
CC2
200
500
µ
A
8
V
CC
Trip Point (TOL = GND)
V
CCTP
4.50
4.62
4.74
V
1
V
CC
Trip Point (TOL = V
CC
)
V
CCTP
4.25
4.37
4.49
V
1
CAPACITANCE
(t
A
= 25
°
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
IN
5
pF
Output Capacitance
C
OUT
7
pF
DS1232LP/LPS
062698 7/7
AC ELECTRICAL CHARACTERISTICS
(0
°
C to 70
°
C; V
CC
= 5V + 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
PBRST = V
IL
t
PB
20
ms
RESET Active Time
t
RST
250
610
1000
ms
ST Pulse Width
t
ST
20
ns
6, 9
V
CC
Fail Detect to RST and RST
t
RPD
50
175
µ
s
V
CC
Slew Rate 4.75V to 4.25V
t
F
300
µ
s
V
CC
Detect to RST and RST
Inactive
t
RPU
250
610
1000
ms
4
V
CC
Slew Rate 4.25V to 4.75V
t
R
0
ns
PBRST Stable Low to RST and
RST
t
PDLY
20
ms
NOTES:
1. All voltages referenced to ground.
2. Measured with outputs open and ST and PBRST within 0.5V of supply rails.
3. PBRST is internally pulled up to V
CC
with an internal impedance of 40K typical.
4. t
R
= 5
µ
s.
5. RST is an open drain output.
6. Must not exceed t
TD
minimum. See Table 1.
7. RST remains within 0.5V of V
CC
on powerdown until V
CC
drops below 2.0V. RST remains within 0.5V of
GND on powerdown until V
CC
drops below 2.0V.
8. Measured with outputs open and ST and PBRST at TTL levels.
9. Watchdog can not be disabled. It must be strobed to avoid resets.
MARKING INFORMATION:
8pin DIP "DS1232L"
16pin SOIC "DS1232L"
8pin SOIC "DS1232L"
8pin
µ
SOP "1232"
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