Spread Spectrum Frequency Timing Generator

W42C31-03

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

September 28, 1999, rev. **

Features

ˇ Maximized EMI suppression using Cypress's Spread

Spectrum technology

ˇ Generates a spread spectrum copy of the provided

input

ˇ Integrated loop filter components
ˇ Operates with a 5V supply
ˇ Low power CMOS design
ˇ Available in 8-pin SOIC (Small Outline Integrated

Circuit)

Overview

The W42C31-03 incorporates the latest advances in PLL
spread spectrum frequency synthesizer techniques. By fre-
quency modulating the output with a low-frequency carrier,
EMI is greatly reduced. Use of this technology allows systems
to pass increasingly difficult EMI testing without resorting to
costly shielding or redesign.

In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.

Table 1. Frequency Spread Selection

W42C31-03

Oscillator

Input

Frequency

(MHz)

XTAL Input

Frequency

(MHz)

Output

Frequency

(MHz)

FS1

FS0

10 to 20

ą1.875%

10 to 20

ą1.0%

20 to 33

20 to 25

ą1.875%

20 to 33

20 to 25

2.0%

Simplified Block Diagram

Pin Configuration

SOIC

Spread Spectrum

W42C31-03

(EMI suppressed)

5.0V

Oscillator or Reference

Spread Spectrum

W42C31-03

(EMI suppressed)

5.0V

XTAL

Input

Output

-
0

GND

FS0

OE#

FS1

VDD

CLKOUT

W42C31-03

Functional Description

The W42C31-03 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. An
on-chip crystal driver causes the crystal to oscillate at its fun-
damental. The resulting reference signal is divided by Q and
fed to the phase detector. A signal from the VCO is divided by
P and fed back to the phase detector also. The PLL will force
the frequency of the VCO output signal to change until the
divided output signal and the divided reference signal match
at the phase detector input. The output frequency is then equal
to the ratio of P/Q times the reference frequency. The unique
feature of the Spread Spectrum Clock Generator is that a mod-
ulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed, the modula-
tion percentage may be varied.

Using frequency select bits (FS1:0 pins), various spreading
percentages can be chosen (see Table 1).

A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ą0.5% and ą2.5% are most
common.

The W42C31 features the ability to select from various spread
spectrum characteristics. Selections specific to the
W42C31-03 are shown in Table 1. Other spreading character-
istics are available (see separate data sheets) or can be cre-
ated with a custom mask.

Pin Definitions

Pin Name

Pin No.

Pin

Type

Pin Description

CLKOUT

Output Modulated Frequency: Frequency modulated copy of the unmodulated input
clock

Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It may either be connected to an external crystal, or to an external reference
clock.

Crystal Connection: If using an external reference, this pin must be left unconnected.

OE#

Output Enable (Active LOW): This pin three-states the output when HIGH. It has an
internal pull-down resistor.

FS0

Frequency Selection Bit 0: This pin selects the frequency spreading characteristics.
Refer to Table 1. This pin has a pull-up resistor.

FS1

Frequency Selection Bit 1: This pin selects the frequency range. Refer to Table 1.
This pin has a pull-up resistor.

VDD

Power Connection: Connected to 5V power supply.

GND

Ground Connection: This should be connected to the common ground plane.

Figure 1. System Block Diagram

XTAL

Freq.

Phase

Modulating

VCO

Post

CLKOUT

Detector

Charge

Pump

Waveform

Dividers

Divider

Feedback

Divider

PLL

GND

VDD

Crystal load
capacitors
as needed

W42C31-03

Spread Spectrum Frequency Timing
Generation

The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.

Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.

Modulating Waveform

The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.

Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
f

Center

MOD

% in the frequency spread selection table.

The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
proach is f

MAX

MOD

%. Whenever this expression is used,

Cypress has taken care to ensure that f

MAX

will never be ex-

ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.

OE# Pin

An internal pull-down resistor defaults the chip into a mode in
which all outputs are active. If OE# goes HIGH, all outputs are
three-stated. The chip will not prevent short cycles in a transi-
tion from three-state to enabled.

SSFTG

Typical Clock

5dB/div

Amp

l
itu

e (d

Figure 2. Typical Clock and SSFTG Comparison

100%

60%

20%

80%

40%

20%
40%
60%
80%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

00%

10%

20%

30%

40%

50%

60%

70%

80%

90%

00%

Time

r
e

i
f
t

Figure 3. Modulation Waveform Profile

W42C31-03

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability

Parameter

Description

Rating

Unit

, V

Voltage on any pin with respect to GND

0.5 to +7.0

STG

Storage Temperature

65 to +150

°C

Operating Temperature

0 to +70

°C

Ambient Temperature under Bias

55 to +125

°C

Power Dissipation

0.5

DC Electrical Characteristics:

0°C < T

< 70°C, V

= 5V ą10%

Parameter

Description

Test Condition

Min

Typ

Max

Unit

Supply Current

Power Up Time

First locked clock cycle after
Power Good

Input Low Voltage

0.15V

Input High Voltage

0.7V

Output Low Voltage

0.4

Output High Voltage

2.5

Input Low Current

Note 1

100

Input High Current

Note 1

Output Low Current

@ 0.4V, V

= 5V

Output High Current

@ 2.4V, V

= 5V

Input Capacitance

All pins except X1, X2

Load Capacitance (as seen
by XTAL)

Pins X1, X2

[2]

Input Pull-Up Resistor

500

OUT

Clock Output Impedance

AC Electrical Characteristics:

= 0°C to +70°C, V

= 5Vą10%

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Input Frequency

Input Clock

MHz

OUT

Output Frequency

MHz

Output Rise Time

, 15-pF load 0.82.4

Output Fall Time

, 15-pF load 2.40.8

Output Duty Cycle

15-pF load

Input Duty Cycle

JCYC

Jitter, Cycle-to-Cycle

300

Harmonic Reduction

Notes:

Inputs FS1:0 have a pull-up resistor; Input OE# has a pull-down resistor.

Pins X1 and X2 each have a 34-pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 17 pF. If driving X1 with a
reference clock signal, the load capacitance will be 34 pF (typical).

W42C31-03

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.

decoupling is important to both reduce phase jitter and

EMI radiation. The 0.1-

F decoupling capacitor should be

placed as close to the V

pin as possible, otherwise the in-

creased trace inductance will negate its decoupling capability.

The 10-

F decoupling capacitor shown should be a tantalum

type. For further EMI protection, the V

connection can be

made via a ferrite bead, as shown.

The 6-pF XTAL load capacitors can be used to raise the inte-
grated 17-pF capacitance up to a total load of 20 pF on the
crystal.

Recommended Board Layout

Figure 5 shows a recommended 2-layer board layout.

Document #: 38-00802

Figure 4. Recommended Circuit Configuration

GND

-
0

XTAL1

Output

6 pF

5V System Supply

10 ĩF Tantalum

VDD

0.1 ĩF

Ordering Information

Ordering Code

Freq. Mask

Code

Package

Name

Package Type

W42C31

8-pin Plastic SOIC (150-mil)

Figure 5. Recommended Board Layout (2-Layer Board)

Optional Guard Ring for
XTAL Oscillator Circuitry

Clock Output

XTAL1

is not required for operation).
Typical value is 6 pF.

High frequency supply decoupling
capacitor (0.1-ĩF recommended).

Common supply low frequency
decoupling capacitor (10-ĩF tantalum
recommended).

XTAL load capacitors (optional; use

Ferrite Bead

C1, C2 =

C3 =

C4 =

Match value to line impedance

R1 =

Power Supply Input

(5V)

Via To GND Plane

W42C31-03

Š Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)

Part Number W42C31-03