SDRAM Buffer - 4 DIMM

W40S01-04

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

June 20, 2000, rev. **

Features

· Eighteen skew controlled CMOS outputs (SDRAM0:17)
· Supports four SDRAM DIMMs
· Ideal for high-performance systems designed around

Intel®'s 440BX chip set

· I

C serial configuration interface

· Output skew between any two outputs is less than

250 ps

· 1 to 5 ns propagation delay
· DC to 133-MHz operation
· Single 3.3V supply voltage
· Low power CMOS design packaged in a 48-pin SSOP

(Small Shrink Outline Package)

Overview

The Cypress W40S01-04 is a low-voltage, eighteen-output
signal buffer. Output buffer impedance is approximately 15

which is ideal for driving SDRAM DIMMs.

Key Specifications

Supply Voltages: ....................................... V

DDQ3

= 3.3V±5%

Operating Temperature:.................................... 0°C to +70°C

Input Threshold: .................................................. 1.5V typical

Maximum Input Voltage: ...................................V

DDQ3

+ 0.5V

Input Frequency:............................................... 0 to 133 MHz

BUF_IN to SDRAM0:17 Propagation Delay: ...... 1.0 to 5.0 ns

Output Edge Rate:.................................................. >1.5 V/ns

Output Skew: ............................................................ ±250 ps

Output Duty Cycle: .................................. 45/55% worst case

Output Impedance: ........................................15 ohms typical

Output Type: ................................................ CMOS rail-to-rail

Part to Part Skew:........................................................700 ps

Intel is a registered trademark of Intel Corporation.

Pin Configuration

SSOP

Block Diagram

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

SDRAM7

SDRAM8

SDRAM9

SDRAM10

SDRAM11

SDRAM12

SDRAM16

SDRAM17

SDRAM13

SDRAM14

SDRAM15

SDRAM0

Serial Port

SCLOCK

SDATA

Device Control

BUF_IN

NC
NC

VDDQ3

SDRAM0
SDRAM1

GND

VDDQ3

SDRAM2
SDRAM3

GND

BUF_IN

VDDQ3

SDRAM4
SDRAM5

GND

VDDQ3

SDRAM6
SDRAM7

GND

VDDQ3

SDRAM16

GND

VDDQ3

SDATA

NC
NC
VDDQ3
SDRAM15
SDRAM14
GND
VDDQ3
SDRAM13
SDRAM12
GND
OE
VDDQ3
SDRAM11
SDRAM10
GND
VDDQ3
SDRAM9
SDRAM8
GND
VDDQ3
SDRAM17
GND
GND
SCLOCK

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

[1]

Note:

Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE
inputs (not CMOS level).

[1]

W40S01-04

Pin Definitions

Pin Name

Pin
No.

Pin

Type

Pin Description

SDRAM0:17

4, 5, 8, 9,

13, 14, 17,
18, 21, 28,
31, 32, 35,
36, 40, 41,

44, 45

SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled
to within ± 250 ps of each other.

BUF_IN

Clock Input: This clock input has an input threshold voltage of 1.5V (typ).

SDATA

I/O

C Data Input: Data should be presented to this input as described in the I

C section

of this data sheet. Internal 250-k

pull-up resistor.

SCLOCK

C clock Input: The I

C data clock should be presented to this input as described in

the I

C section of this data sheet. Internal 250-k

pull-up resistor.

VDDQ3

3, 7, 12, 16,

20, 23, 29,
33, 37, 42,

Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.

GND

6, 10, 15,

19, 22, 26,
27, 30, 34,

39, 43

Ground Connection: Connect all ground pins to the common system ground plane.

Output Enable: Internal 250-k

pull-up resistor. Three-states outputs when LOW.

1, 2, 47, 48

No Connect: Do not connect.

W40S01-04

Functional Description

Output Control Pins

Outputs three-stated when OE = 0, and toggle when OE = 1.
Outputs are in phase with BUF_IN but are phase delayed by 1
to 5 ns. Outputs can also be controlled via the I

C interface.

Output Drivers

The W40S01-04 output buffers are CMOS type which deliver
a rail-to-rail (GND to V

) output voltage swing into a nominal

capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15 ohms.

Operation

Data is written to the W40S01-04 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.

Table 1. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

Slave Address

11010010

Commands the W40S01-04 to accept the bits in Data Bytes 0-6 for inter-
nal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the
W40S01-04 is 11010010. Register setting will not be made if the Slave
Address is not correct (or is for an alternate slave receiver).

Command
Code

Don't Care

Unused by the W40S01-04, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.

Byte Count

Don't Care

Unused by the W40S01-04, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.

Data Byte 0

Refer to Table 2

The data bits in these bytes set internal W40S01-04 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 2, Data Byte Serial Configuration Map.

Data Byte 1

Data Byte 2

Data Byte 3

Don't Care

Refer to Cypress clock drivers.

Data Byte 4

Data Byte 5

Data Byte 6

W40S01-04

Writing Data Bytes

Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.

Table 2 gives the bit formats for registers located in Data Bytes
06.

Note:

At power-up all SDRAM outputs are enabled and active. Program Reserved bits to 0.

Table 2. Data Bytes 02 Serial Configuration Map

[2]

Bit(s)

Affected Pin

Control Function

Bit Control

Pin No.

Pin Name

Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)

SDRAM7

Clock Output Disable

Low

Active

SDRAM6

Clock Output Disable

Low

Active

SDRAM5

Clock Output Disable

Low

Active

SDRAM4

Clock Output Disable

Low

Active

SDRAM3

Clock Output Disable

Low

Active

SDRAM2

Clock Output Disable

Low

Active

SDRAM1

Clock Output Disable

Low

Active

SDRAM0

Clock Output Disable

Low

Active

Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)

SDRAM15

Clock Output Disable

Low

Active

SDRAM14

Clock Output Disable

Low

Active

SDRAM13

Clock Output Disable

Low

Active

SDRAM12

Clock Output Disable

Low

Active

SDRAM11

Clock Output Disable

Low

Active

SDRAM10

Clock Output Disable

Low

Active

SDRAM9

Clock Output Disable

Low

Active

SDRAM8

Clock Output Disable

Low

Active

Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)

SDRAM17

Clock Output Disable

Low

Active

SDRAM16

Clock Output Disable

Low

Active

N/A

Reserved

(Reserved)

N/A

Reserved

(Reserved)

N/A

Reserved

(Reserved)

N/A

Reserved

(Reserved)

N/A

Reserved

(Reserved)

N/A

Reserved

(Reserved)

W40S01-04

How To Use the Serial Data Interface

Electrical Requirements

Figure 1 illustrates electrical characteristics for the serial inter-
face bus used with the W40S01-04. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up resis-
tor on the bus (both clock and data lines) establish a default

logic 1. All bus devices generally have logic inputs to receive
data.

Although the W40S01-04 is a receive-only device (no data
write-back capability), it does transmit an "acknowledge" data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.

The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration to-
tal bus line capacitance.

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Figure 1. Serial Interface Bus Electrical Characteristics

Part Number W40S01-04