ChipFind - Datasheet

Part Number VIC068A

Download:  PDF   ZIP
VMEbus Interface Controller
VIC068A
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
·
CA 95134
·
408-943-2600
December 1990 - Revised July 23, 1997
Features
· Complete VMEbus interface controller and arbiter
-- 58 internal registers provide configuration control
and status of VMEbus and local operations
-- Drives arbitration, interrupt, address modifier utility,
strobe, address lines A07 through A01 and data lines
D07 through D00 directly, and provides signals for
control logic to drive remaining address and data
lines
-- Direct connection to 68xxx family and mappable to
non-68xxx processors
· Complete master/slave capability
-- Supports read, write, write posting, and block trans-
fers
-- Accommodates VMEbus timing requirements with
internal digital delay line (
1
/
2
-clock granularity)
-- Programmable metastability delay
-- Programmable data acquisition delays
-- Provides timeout timers for local bus and VMEbus
transactions
· Interleaved block transfers over VMEbus
-- Acts as DMA master on local bus
-- Programmable burst count, transfer length, and in-
terleaved period interval
-- Supports local module-based DMA
· Arbitration support
-- Supports single-level, priority and round robin arbi-
tration
-- Supports fair request option as requester
· Interrupt support
-- Complete support for the VMEbus interrupts: inter-
rupter and interrupt handler
-- Seven local interrupt lines
-- 8-level interrupt priority encode
-- Total of 29 interrupts mapped through the VIC068A
· Miscellaneous features
-- Refresh option for local DRAM
-- Four broadcast location monitors
-- Four module-specific location monitors
-- Eight interprocessor communications registers
-- PGA or QFP packages
-- Compatible with IEEE Specification 1014, Rev. C
-- Supports RMC operations
· See the VMEbus Interface Handbook for more informa-
tion
Functional Description
The VMEbus interface controller (VIC068A) is a single chip
designed to minimize the cost and board area requirements
and to maximize performance of the VMEbus interface of a
VMEbus master/slave module. This can be implemented on
VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The
VIC068A performs all VMEbus system controller functions
plus many others, which simplify the development of
VIC068Aa VMEbus interface. The VIC068A utilizes patented
on-chip output buffers. These CMOS high-drive buffers pro-
vide direct connection to the address and data lines. In addi-
tion to these signals, the VIC068A connects directly to the ar-
bitration, interrupt, address modifier, utility and strobe lines.
Signals are provided which control data direction and latch
functions needed for a 32-bit implementation.
The VIC068A was developed through the efforts of a consor-
tium of board vendors, under the auspices of the VMEbus In-
ternational Trade Association (VITA). The VIC068A thus in-
sures compatibility between boards designed by different
manufacturers.
VIC068A
2
Pin Configurations
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
GND
LD6
LD2
LA7
LA3
LA2
LA1
CS*
PAS*
DSACK0*
HALT*
FC2
SIZ1
BLT*
LD5
LD3
LD0
LA5
LA4
LA0
DSACK1*
LBERR*
R/W*
IPL2*
RMC*
SIZ0
IRESET*
ABEN*
LIACKO*
IPL1*
DEDLK*
LD7
LD4
LA6
GND
VCC
DS*
RESET*
FC1
LBR*
SCON*
LADO
VCC
LIRQ2*
VCC
IPL0*
LOCATOR
PIN
CLK64M
LEDI
LEDO
LIRQ5*
LIRQ1*
LAEN
ASIZ1
LIRQ4*
LIRQ3*
LADI
DDIR
UWDENIN*
GND
LWDENIN*
SWDEN*
ASIZ0
LIRQ6*
LIRQ7*
VCC
DENO*
ISOBE*
SLSEL1*
ICFSEL*
GND
GND
D06
D07
WORD*
MWB*
SLSEL0*
VCC
D03
D05
FIACK*
A01
GND
D00
D01
D04
A02
A03
A06
BGOUT1*
GND
D02
A04
A05
IRQ1*
BGIN2*
BGOUT0*
BGOUT3*
VCC
A07
IRQ2*
IRQ5*
SYSFAIL*
IACKIN*
GND
GND
VCC
BERR*
BR2*
BBSY*
BGIN0*
BGIN3*
BGOUT2*
GND
IRQ3*
IRQ6*
VCC
SYSRESET*
IACK*
AS*
AM2
LWORD*
WRITE*
DS1*
BR1*
BR3*
BGIN1*
SYSCLK
IRQ4*
IRQ7*
ACFAIL*
IACKOUT*
DTACK*
AM0
AM1
AM3
AM4
AM5
DS0*
BR0*
GND
BCLR*
GND
Pin Grid Array (PGA)
Bottom View
LBG*
LD1
VIC068A­1
VIC068A
3
Pin Configurations
(continued)
VIC068A­2
1
GND
120
GND
2
GND
119
GND
3
IPL0*
118
LBG*
4
IPL1*
117
IRESET*
5
IPL2*
116
SCON*
6
VCC
115
CLK64M
7
LAEN
114
ABEN*
8
LIAKO*
113
LADO
9
LIRQ1*
112
LADI
10
LIRQ2*
111
LEDI
11
LIRQ3*
110
VCC
12
LIRQ4*
109
LEDO
13
LIRQ5*
108
DDIR
14
LIRQ6*
107
UWDENIN*
15
LIRQ7*
106
GND
16
ASIZ1*
105
LWDENIN*
17
ASIZ0*
104
DENO*
18
ICFSEL*
103
SWDEN*
19
SLSEL1*
102
ISOBE*
20
GND
101
VCC
21
SLSEL0*
100
GND
22
WORD*
99
D07
23
FCIACK*
98
D06
24
MWB*
97
D05
25
A1
96
D04
26
GND
95
VCC
27
A2
94
D03
28
A3
93
D02
29
A4
92
D01
30
VCC
91
D00
31
A5
90
BGOUT3*
32
A6
89
GND
33
A7
88
BGOUT2*
34
VSS
87
BGOUT1*
35
IRQ1*
86
BGOUT0*
36
IRQ2*
85
SYSCLK
37
IRQ3*
84
BGIN3*
38
IRQ4*
83
BGIN2*
39
GND
82
GND
40
GND
81
GND
41
VC
C
160
V
C
C
42
VC
C
159
V
C
C
43
IRQ
5
*
158
G
N
D
44
IRQ
6
*
157
B
L
T
*
45
IRQ
7
*
1
5
6
DE
DL
K
*
46
VC
C
155
LD
7
47
SY
SF
AI
L
*
154
LD
6
48
AC
F
A
I
L
*
153
LD
5
49
SY
SR
ES
ET
*
152
LD
4
50
IA
CK
O
U
T
*
151
LD
3
51
IA
CK
IN*
150
LD
2
52
IA
CK
*
149
LD
1
53
D
T
AC
K*
148
LD
0
54
AS
*
147
LA
7
55
GN
D
146
LA
6
56
AM
0
145
LA
5
57
AM
1
144
LA
4
58
AM
2
143
LA
3
59
AM
3
142
LA
2
60
GN
D
141
G
N
D
61
VC
C
140
V
C
C
62
AM
4
139
LA
1
63
AM
5
138
LA
0
64
L
W
O
RD*
137
C
S
*
65
WR
I
T
E*
1
3
6
PA
S*
66
B
E
RR*
135
D
S
*
67
DS
0
*
134
D
S
A
C
K
1
*
68
DS
1
*
133
D
S
A
C
K
0
*
69
BR
0
*
132
LB
E
R
R
*
70
GN
D
131
R
E
S
E
T
*
71
BR
1
*
130
H
A
LT
*
72
BR
2
*
129
R
/
W
*
73
BR
3
*
128
F
C
2
74
BC
L
R
*
127
F
C
1
75
BB
SY*
1
2
6
RM
C*
76
BG
I
N
0
*
125
S
I
Z
1
77
BG
I
N
1
*
124
S
I
Z
0
78
GN
D
123
LB
R
*
79
VC
C
122
V
C
C
80
VC
C
121
V
C
C
160-Pin Quad Flatpack (QFP)
Top View
VIC068A
4
Pin Configurations
(continued)
144-Pin Thin Quad Flatpack (TQFP)
Top View
VIC068A­3
GN
D
LBG*
IRQ
5
*
IPL0*
2
3
4
IPL1*
IRESET*
5
IPL2*
SCON*
6
VCC
CLK64M
7
LAEN
ABEN*
8
LIAKO*
LADO
9
LIRQ1*
LADI
10
LIRQ2*
LEDI
11
LIRQ3*
VCC
12
LIRQ4*
LEDO
13
LIRQ5*
108
DDIR
14
LIRQ6*
107
UWDENIN*
15
LIRQ7*
106
GND
16
ASIZ1*
105
LWDENIN*
17
ASIZ0*
104
DENO*
18
ICFSEL*
103
SWDEN*
19
SLSEL1*
102
ISOBE*
20
GND
101
VCC
21
SLSEL0*
100
GND
22
WORD*
99
D07
23
FCIACK*
98
D06
24
MWB*
97
D05
25
A1
96
D04
26
GND
95
VCC
27
A2
94
D03
28
A3
93
D02
29
A4
92
D01
30
VCC
91
D00
31
A5
90
BGOUT3*
32
A6
89
GND
33
A7
88
BGOUT2*
34
GND
87
BGOUT1*
35
IRQ1*
86
BGOUT0*
36
IRQ2*
85
SYSCLK
IRQ3*
84
BGIN3*
IRQ4*
83
BGIN2*
82
81
41
42
43
44
IRQ
6
*
BL
T
*
45
IRQ
7
*
DE
D
L
K
*
46
VC
C
LD
7
47
SYS
F
A
I
L
*
LD
6
48
AC
F
A
I
L
*
LD
5
49
SYS
R
ESE
T
*
LD
4
50
IA
CK
O
U
T
*
LD
3
51
IA
CK
IN*
LD
2
52
IA
CK
*
LD
1
53
D
T
AC
K*
LD
0
54
AS*
LA
7
55
GN
D
LA
6
56
AM
0
LA
5
57
AM
1
LA
4
58
AM
2
14
3
LA
3
59
AM
3
14
2
LA
2
60
GN
D
14
1
GN
D
61
VC
C
14
0
VC
C
62
AM
4
13
9
LA
1
63
AM
5
13
8
LA
0
64
L
W
O
RD*
13
7
CS
*
65
WR
I
T
E*
13
6
PAS
*
66
B
E
RR*
13
5
DS
*
67
DS
0
*
13
4
D
S
AC
K1
*
68
DS
1
*
13
3
D
S
AC
K0
*
69
BR
0
*
13
2
L
B
E
RR*
70
VS
S
13
1
R
E
SET
*
71
BR
1
*
13
0
HA
L
T
*
72
BR
2
*
12
9
R/
W
*
123
BR
3
*
12
8
FC
2
122
BC
L
R
*
12
7
FC
1
121
BBS
Y*
12
6
RM
C
*
120
BG
I
N
0
*
12
5
SI
Z
1
119
BG
I
N
1
*
12
4
SI
Z
0
118
GN
D
LB
R
*
117
116
37
38
39
40
80
79
78
77
76
75
74
73
115
114
113
112
111
110
109
14
4
1
VIC068A
5