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Part Number GVT71256E18

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256K x 18 Synchronous Flow-Through Burst SRAM
CY7C1325A/GVT71256E18
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
·
CA 95134
·
408-943-2600
Document #: 38-05118 Rev. *A
Revised November 12, 2002
325A
Features
· Fast access times: 7.5 and 8 ns
· Fast clock speed: 117 and 100 MHz
· Provide high-performance 2-1-1-1 access rate
· Fast OE access times: 4.0 ns
· 3.3V ­5% and +10% power supply
· 2.5V or 3.3V I/O supply
· 5V tolerant inputs except I/Os
· Clamp diodes to V
SSQ
at all inputs and outputs
· Common data inputs and data outputs
· Byte Write Enable and Global Write control
· Three chip enables for depth expansion and address
pipeline
· Address, data and control registers
· Internally self-timed Write Cycle
· Burst control pins (interleaved or linear burst se-
quence)
· Automatic power-down for portable applications
· Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1325A/GVT71256E18 SRAM integrates
262,144x18 SRAM cells with advanced synchronous periph-
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE), and Sleep Mode Control (ZZ).
The data outputs (DQ), enabled by OE, are also asynchro-
nous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1­DQ8 and DQP1. WEH controls DQ9­DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written.
The CY7C1325A/GVT71256E18 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PCTM systems and for systems that benefit from a wide syn-
chronous data bus.
Selection Guide
7C1325A-117
71256E18-7
7C1325A-100
71256E18-8
7C1325A-100
71256E18-9
7C1325A-100
71256E18-10
Maximum Access Time (ns)
7.5
8
8
8
Maximum Operating Current (mA)
370
320
320
320
Maximum CMOS Standby Current (mA)
10
10
10
10
CY7C1325A/GVT71256E18
Document #: 38-05118 Rev. *A
Page 2 of 16
Note:
1.
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
256K x 18 (CY7C1325A/GVT71256E18) Functional Block Diagram
[1]
D
Q
D
Q
WEH#
BWE#
WEL#
GW#
CE#
CE2
CE2#
UPPER BYTE
WRITE
LOWER BYTE
WRITE
ENABLE
OE#
hi byte write
ADSP#
ADSC#
CLK
Address
Register
Binary
Counter
& Logic
CLR
A17-A2
A1-A0
ADV#
MODE
256K x 9 x 2
S
RAM
Array
Output B
u
ffers
Input
Register
lo byte write
DQ1-DQ16
DQP1
DQP2
D
Q
Power Down Logic
ZZ
CY7C1325A/GVT71256E18
Document #: 38-05118 Rev. *A
Page 3 of 16
Pin Configurations
100-Pin TQFP
Top View
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
CC
NC
NC
A15
A14
A13
A12
A11
A16
A1
7
A10
NC
NC
V
CCQ
V
SSQ
NC
DQP1
DQ8
DQ7
V
SSQ
V
CCQ
DQ6
DQ5
V
SS
NC
V
CC
ZZ
DQ4
DQ3
V
CCQ
V
SSQ
DQ2
DQ1
NC
NC
V
SSQ
V
CCQ
NC
NC
NC
NC
NC
NC
V
CCQ
V
SSQ
NC
NC
DQ9
DQ10
V
SSQ
V
CCQ
DQ11
DQ12
V
CC
NC
V
SS
DQ13
DQ14
V
CCQ
V
SSQ
DQ15
DQ16
DQP2
NC
V
SSQ
V
CCQ
NC
NC
NC
A6
A7
CE
CE
2
NC
NC
WE
H
WE
L
CE
2
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MO
D
E
CY7C1325A
(256K X 18)
NC
CY7C1325A/GVT71256E18
Document #: 38-05118 Rev. *A
Page 4 of 16
Pin Configurations
(continued)
119-Ball Bump BGA
1
2
3
4
5
6
7
A
V
CCQ
A6
A4
ADSP
A8
A16
V
CCQ
B
NC
CE2
A3
ADSC
A9
CE2
NC
C
NC
A7
A2
V
CC
A12
A15
NC
D
DQ9
NC
V
SS
NC
V
SS
DQ"P1
NC
E
NC
DQ10
V
SS
CE
V
SS
NC
DQ8
F
V
CCQ
NC
V
SS
OE
V
SS
DQ7
V
CCQ
G
NC
DQ11
BWH
ADV
V
SS
NC
DQ6
H
DQ12
NC
V
SS
GW
V
SS
DQ5
NC
J
V
CCQ
V
CC
NC
V
CC
NC
V
CC
V
CCQ
K
NC
DQ13
V
SS
CLK
V
SS
NC
DQ4
L
DQ14
NC
V
SS
NC
BWL
DQ3
NC
M
V
CCQ
DQ15
V
SS
BWE
V
SS
NC
V
CCQ
N
DQ18
NC
V
SS
A1
V
SS
DQ2
NC
P
NC
DQP2
V
SS
A0
V
SS
NC
DQ1
R
NC
A5
MODE
V
CC
NC
A13
NC
T
NC
A10
A11
NC
A14
A17
ZZ
U
V
CCQ
NC
NC
NC
NC
NC
V
CCQ
256Kx18--CY7C1325A/GVT71256E18
Top View
Pin Descriptions
BGA Pins
QFP Pins
Pin
Name
Type
Description
4P, 4N, 2A, 3A,
5A, 6A, 3B, 5B,
2C, 3C, 5C, 6C,
2R, 6R, 2T, 3T,
5T, 6T
37, 36, 35, 34,
33, 32, 100, 99,
82, 81, 80, 48,
47, 46, 45, 44,
49, 50
A0­A17
Input-
Synchronous
Addresses: These inputs are registered and must meet the set-up
and hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
5L, 3G
93, 94
WEL,
WEH
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a Write cycle
and HIGH for a Read cycle. WEL controls DQ1­DQ8 and DQP1.
WEH controls DQ9­DQ16 and DQP2. Data I/O are high-imped-
ance if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations
and must meet the set-up and hold times around the rising edge of
CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 18-bit Write to
occur independent of the BWE and WEn lines and must meet the
set-up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables, write
control and burst control inputs on its rising edge. All synchronous
inputs must meet set-up and hold times around the clock's rising
edge.
CY7C1325A/GVT71256E18
Document #: 38-05118 Rev. *A
Page 5 of 16
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device
and to gate ADSP.
6B
92
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
2B
97
CE2
input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle (no
address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with CE
being LOW, causes a new external address to be registered and a
Read cycle is initiated using the new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes device to
be deselected or selected along with new external address to be
registered. A Read or Write cycle is initiated depending upon write
control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
7T
64
ZZ
Input-
Asynchro-
nous
Snooze: This active HIGH input puts the device in low power con-
sumption standby mode. For normal operation, this input has to be
either LOW or NC (No Connect).
7P, 6N, 6L, 7K,
6H, 7G, 6F, 7E,
1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N
58, 59, 62, 63,
68, 69, 72, 73, 8,
9, 12, 13, 18, 19,
22, 23
DQ1-
DQ16
Input/
Output
Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-
DQ16. Input data must meet setup and hold times around the rising
edge of CLK.
6D, 2P
74, 24
DQP1,
DQP2
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2
is parity bit for DQ9-DQ16.
4C, 2J, 4J, 6J,
4R
15, 41,65, 91
V
CC
Supply
Power Supply: +3.3V ­5% and +10%
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
17, 40, 67, 90
V
SS
Ground
Ground: GND
1A, 7A, 1F, 7F,
1J, 7J, 1M, 7M,
1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
V
CCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to V
CC
)
5, 10, 21, 26, 55,
60, 71, 76
V
SSQ
I/O Ground
Output Buffer Ground: GND
1B, 7B, 1C, 7C,
2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R,
7R, 1T, 4T, 2U,
3U, 4U, 5U, 6U
1­3, 6, 7, 14, 16,
25, 28-30, 38,
39, 42, 43, 51-
53, 56, 57, 66,
75, 78, 79, 80,
95, 96
NC
-
No Connect: These signals are not internally connected.
Pin Descriptions
(continued)
BGA Pins
QFP Pins
Pin
Name
Type
Description