64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
fax id: 5410
CY7C4425/4205/4215
CY7C4225/4235/4245
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
·
CA 95134
·
408-943-2600
April 1995 - Revised August 18, 1997
1CY 7C42 25
Features
· High-speed, low-power, first-in first-out (FIFO)
memories
· 64 x 18 (CY7C4425)
· 256 x 18 (CY7C4205)
· 512 x 18 (CY7C4215)
· 1K x 18 (CY7C4225)
· 2K x 18 (CY7C4235)
· 4K x 18 (CY7C4245)
· High-speed 100-MHz operation (10 ns read/write cycle
time)
· Low power (I
CC
=45 mA)
· Fully asynchronous and simultaneous read and write
operation
· Empty, Full, Half Full, and Programmable Almost
Empty/Almost Full status flags
· TTL-compatible
· Retransmit function
· Output Enable (OE) pin
· Independent read and write enable pins
· Center power and ground for reduced noise
· Supports free-running 50% duty cycle clock inputs
· Width Expansion Capability
· Depth Expansion Capability
· Space saving 64-pin 10x10 TQFP, and 14x14 TQFP
· 68-pin PLCC
Functional Description
T
he CY7C42X5 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to
IDT722x5. The CY7C42X5 can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
device should be connected to the WXI and RXI pins of the
first device. The FL pin of the first device is tied to V
SS
and the
FL pin of all the remaining devices should be tied to V
CC
.
The CY7C42X5 provides five status pins. These pins are de-
coded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see
Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
V
CC
/SMODE is tied to V
SS
. All configurations are fabricated
using an advanced 0.65
µ
N-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is prevent-
ed by the use of guard rings.
CY7C4425/4205/4215
CY7C4225/4235/4245
2
Logic Block Diagram
42X51
THREESTATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0 17
REN
RCLK
FF
EF
PAE
Q
0 17
WEN
WCLK
RS
FL/RT
WXI
OE
DUAL PORT
RAM ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
PAF
WXO/HF
RXI
RXO
SMODE
Pin Configurations
EF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
Top View
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 3940
4142 43
5
4
3
2 1 68
66 65 64 63 62 61
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
2728 2930
9 8
7
6
47
46
45
44
Q
6
Q
5
GND
Q
4
D
3
D
2
D
1
D
0
25
26
V
CC
/SMODE
42x52
TQFP
Top View
42X53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
16
PLCC
PA
E
FL
/RT
WC
L
K
WE
N
WX
I
V
CC
PA
F
RX
I
FF
WX
O
/HF
RX
O
Q
0
Q
1
GN
D
Q
2
Q
3
V
CC
Q
15
GN
D
Q
16
Q
17
V
CC
EF
GN
D
V
CC
RS
OE
LD
RE
N
RCL
K
GN
D
D
17
D
16
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
15
Q
15
GN
D
Q
16
Q
17
GN
D
V
CC
RS
OE
LD
RE
N
RCL
K
GN
D
D
17
D
16
PA
E
WC
L
K
WE
N
WX
I
V
CC
PA
F
RX
I
FF
WX
O
/HF
RX
O
Q
0
Q
1
GN
D
Q
2
Q
3
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
V
CC
/S
MO
DE
FL
/RT
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C4425/4205/4215
CY7C4225/4235/4245
3
Selection Guide
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Maximum Frequency (MHz)
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
Minimum Data or Enable Set-Up (ns)
3
4
6
7
Minimum Data or Enable Hold (ns)
0.5
1
1
2
Maximum Flag Delay (ns)
8
10
15
20
Operating Current (I
CC2
)
(mA) @ freq=20MHz
Commercial
45
45
45
45
Industrial
50
50
50
50
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
Density
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
Packages
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name
Description
I/O
Function
D
017
Data Inputs
I
Data inputs for an 18-bit bus
Q
017
Data Outputs
O
Data outputs for an 18-bit bus
WEN
Write Enable
I
Enables the WCLK input
REN
Read Enable
I
Enables the RCLK input
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
LD
Load
I
When LD is LOW, D
0 - 17
(O
0 - 17
) are written (read) into (from) the programma-
ble-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode of width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded - Tied to V
SS
. Retransmit function is also available in standalone
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
SS
.
CY7C4425/4205/4215
CY7C4225/4235/4245
4
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
....................................-
65
°
C to +150
°
C
Ambient Temperature with
Power Applied
.................................................-
55
°
C to +125
°
C
Supply Voltage to Ground Potential
.................-
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................-
0.5V to +7.0V
DC Input Voltage
.................................................-
3.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
RXI
Read Expansion
Input
I
Cascaded - Connected to RXO of previous device.
Not Cascaded - Tied to V
SS
.
RXO
Read Expansion
Output
O
Cascaded - Connected to RXI of next device.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO's data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state.
V
CC
/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags - tied to V
CC
.
Synchronous Almost Empty/Almost Full flags - tied to V
SS
.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Pin Definitions
(continued)
Signal Name
Description
I/O
Function
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
°
C to +70
°
C
5V
±
10%
Industrial
[1]
-
40
°
C to +85
°
C
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter
Description
Test Conditions
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
=
-
2.0 mA
2.4
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
0.4
V
V
IH
[3]
Input HIGH Voltage
2.2
V
CC
2.2
V
CC
2.2
V
CC
2.2
V
CC
V
V
IL
[3]
Input LOW Voltage
-
3.0
0.8
-
3.0
0.8
-
3.0
0.8
-
3.0
0.8
V
I
IX
Input Leakage
Current
V
CC
= Max.
-
10
+10
-
10
+10
-
10
+10
-
10
+10
µ
A
I
OS
[4]
Output Short
Circuit Current
V
CC
= Max.,
V
OUT
= GND
-
90
-
90
-
90
-
90
mA
I
OZL
I
OZH
Output OFF,
High Z Current
OE > V
IH
,
V
SS
< V
O
< V
CC
-
10
+10
-
10
+10
-
10
+10
-
10
+10
µ
A
I
CC2
[5]
Operating Current
V
CC
= Max.,
I
OUT
= 0 mA
Com'l
45
45
45
45
mA
Ind
50
50
50
50
mA
I
SB
[6]
Standby Current
V
CC
= Max.,
I
OUT
= 0 mA
Com'l
10
10
10
10
mA
Ind
15
15
15
15
mA
Notes:
1.
T
A
is the "instant on" case temperature.
2.
See the last page of this specification for Group A subgroup testing information.
3.
The V
IH
and V
IL
specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or V
SS
.
4.
Test no more than one output at a time for not more than one second.
5.
Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6.
All input signals are connected to V
CC
. All outputs are unloaded.
CY7C4425/4205/4215
CY7C4225/4235/4245
5
Notes:
7.
Tested initially and after any design or process changes that may affect these parameters.
8.
C
L
= 30 pF for all AC parameters except for t
OHZ
.
9.
C
L
= 5 pF for t
OHZ
.
Capacitance
[7]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
5
pF
C
OUT
Output Capacitance
7
pF
AC Test Loads and Waveforms
[8, 9]
3.0V
5V
OUTPUT
R11.1K
R2
680
C
L
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 3 ns
< 3 ns
OUTPUT
1.91V
Equivalent to:
THÉ
EVENIN
EQUIVALENT
42X54
410
ALL INPUT PULSES
42X55
Switching Characteristics
Over the Operating Range
Parameter
Description
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
S
Clock Cycle Frequency
100
66.7
40
28.6
MHz
t
A
Data Access Time
2
8
2
10
2
15
2
20
ns
t
CLK
Clock Cycle Time
10
15
25
35
ns
t
CLKH
Clock HIGH Time
4.5
6
10
14
ns
t
CLKL
Clock LOW Time
4.5
6
10
14
ns
t
DS
Data Set-Up Time
3
4
6
7
ns
t
DH
Data Hold Time
0.5
1
1
2
ns
t
ENS
Enable Set-Up Time
3
4
6
7
ns
t
ENH
Enable Hold Time
0.5
1
1
2
ns
t
RS
Reset Pulse Width
[10]
10
15
25
35
ns
t
RSR
Reset Recovery Time
8
10
15
20
ns
t
RSF
Reset to Flag and Output Time
10
15
25
35
ns
t
PRT
Retransmit Pulse Width
12
15
25
35
ns
t
RTR
Retransmit Recovery Time
12
15
25
35
ns
t
OLZ
Output Enable to Output in Low Z
[11]
0
0
0
0
ns
t
OE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
t
OHZ
Output Enable to Output in High Z
[12]
3
7
3
8
3
12
3
15
ns
t
WFF
Write Clock to Full Flag
8
10
15
20
ns
t
REF
Read Clock to Empty Flag
8
10
15
20
ns
t
PAFasynch
Clock to Programmable Almost-Full Flag
[12]
(Asynchronous mode, V
CC
/SMODE tied to V
CC
)
12
16
20
25
ns
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