Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-06010 Rev. *A

Revised August 22, 2003

Features

· High-speed, low-power, first-in, first-out (FIFO)

memories

· 64 x 9 (CY7C4421V)
· 256 x 9 (CY7C4201V)
· 512 x 9 (CY7C4211V)
· 1K x 9 (CY7C4221V)
· 2K x 9 (CY7C4231V)
· 4K x 9 (CY7C4241V)
· 8K x 9 (CY7C4251V)
· High-speed 66-MHz operation (15-ns read/write cycle

time)

· Low power (I

= 20 mA)

· 3.3V operation for low power consumption and easy

integration into low-voltage systems

· 5V-tolerant inputs V

IH max

= 5V

· Fully asynchronous and simultaneous read and write

operation

· Empty, Full, and Programmable Almost Empty and

Almost Full status flags

· TTL compatible
· Output Enable (OE) pin
· Independent read and write enable pins
· Center power and ground pins for reduced noise
· Width expansion capability
· Space saving 32-pin 7 mm × 7 mm TQFP
· 32-pin PLCC

Functional Description

The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.

Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.

Logic Block Diagram

Pin Configuration

THREE-STATE

OUTPUTREGISTER

READ

CONTROL

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER

READ

POINTER

RESET

LOGIC

INPUT

FLAG

PROGRAM

RCLK

EF
PAE
PAF

WEN1

WCLK

Dual Port
RAM Array

64 x 9

8Kx 9

WEN2/LD

REN1 REN2

PLCC

RCLK

GND

WCLK
WEN2/LD

PAF

PAE

5
6
7
8
9
10
11
12
13

REN1

REN2

4 3 2 1

3130

RCLK

GND

PAF

PAE

REN1

REN2

141516 171819 20

14 15 16

9 10 11 12 13

31 30

29 28 27

WEN1

WCLK
WEN2/LD

WEN1

TQFP

Top View

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *A

Page 2 of 17

Functional Description

(continued)

The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty-7 and Full-7.

The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).

When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.65m
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.

Selection Guide

CY7C42X1V-15

CY7C42X1V-25

CY7C42X1V-35

Unit

Maximum Frequency

66.7

28.6

MHz

Maximum Access Time

Minimum Cycle Time

Minimum Data or Enable Set-up

Minimum Data or Enable Hold

Maximum Flag Delay

Active Power Supply Current

Commercial

CY7C4421V

CY7C4201V

CY7C4211V

CY7C4221V

CY7C4231V

CY7C4241V

CY7C4251V

Density

64 x 9

256 x 9

512 x 9

1K x 9

2K x 9

4K x 9

8K x 9

Pin Definitions

Signal Name

Description

I/O

Description

Data Inputs

Data Inputs for 9-bit bus.

Data Outputs

Data Outputs for 9-bit bus.

WEN1

Write Enable 1

The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.

WEN2/LD
Dual Mode Pin

Write Enable 2

If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.

Load

REN1, REN2

Read Enable
Inputs

Enables the device for Read operation.

WCLK Write

Clock

The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.

RCLK

Read Clock

The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.

Empty Flag

When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

Full Flag

When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

PAE

Programmable
Almost Empty

When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.

PAF

Programmable
Almost Full

When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.

Reset

Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.

Output Enable

When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state.

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *A

Page 3 of 17

Architecture

The CY7C42X1V consists of an array of 64 to 8K words of nine
bits each (implemented by a dual-port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF.)

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q

0-8

) go LOW

RSF

after the rising edge of RS. In order for the FIFO to reset

to its default state, a falling edge must occur on RS and the
user must not read or write while RS is LOW. All flags are
guaranteed to be valid t

RSF

after RS is taken LOW.

FIFO Operation

When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D

0 -8

pins is written into the FIFO on each

rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q

0-8

outputs. New data will be presented

on each rising edge of RCLK while REN1 and REN2 are
active. REN1 and REN2 must set up t

ENS

before RCLK for it

to be a valid read function. WEN1 and WEN2 must occur t

ENS

before WCLK for it to be a valid write function.

An Output Enable (OE) pin is provided to three-state the Q

0-8

outputs when OE is asserted. When OE is enabled (LOW), data
in the output register will be available to the Q

0-8

outputs after t

The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q

0-8

outputs

even after additional reads occur.

Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.

Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS=LOW), this pin operates as a second write
enable pin.

If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK.) Data is stored in the RAM array sequentially and
independently of any on-going read operation.

Programming

When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1V for writing or reading data to
these registers.

When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset Least Significant Bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset Most Significant Bit (MSB) register, full
offset LSB register, and full offset MSB register, respectively,
when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again. Figure 1 shows
the register sizes and default values for the various device
types.

It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in
sequence.

The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *A

Page 4 of 17

Programmable Flag (PAE, PAF) Operation

Whether the flag offset registers are programmed as described
in Table 1 or the default values are used, the programmable
Almost Empty Flag (PAE) and programmable Almost Full Flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write
pointers.

The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK
when the FIFO contains (n+1) or greater unread words.

The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421V (64 m), CY7C4201V
(256 m), CY7C4211V (512 m), CY7C4221V (1K m),
CY7C4231V (2K m), CY7C4241V (4K m), and
CY7C4251V (8K m). PAF is set HIGH by the LOW-to-HIGH
transition of WCLK when the number of available memory
locations is greater than m.

Note:

The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.

Figure 1. Offset Register Location and Default Values

64 x 9

256 x 9

512 x 9

1K x 9

2K x 9

4K x 9

8K x 9

(MSB)

000

(MSB)

000