ChipFind - Datasheet

Part Number CY7C1354V25

Download:  PDF   ZIP
PRELIMINARY
256Kx36/512Kx18 Pipelined SRAM with NoBLTM Architecture
CY7C1354V25
CY7C1356V25
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
·
CA 95134
·
408-943-2600
Document #: 38-05263 Rev. **
Revised March 6, 2002
356V25
Features
· Pin compatible and functionally equivalent to ZBTTM
· Supports 200-MHz bus operations with zero wait states
-- Data is transferred on every clock
· Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
· Fully Registered (inputs and outputs) for pipelined op-
eration
· Byte Write capability
· Common I/O architecture
· Single 2.5V power supply
· Fast clock-to-output times
-- 3.2 ns (for 200-MHz device)
-- 3.5 ns (for 166-MHz device)
-- 4.2 ns (for 133-MHz device)
-- 5.0 ns (for 100-MHz device)
· Clock Enable (CEN) pin to suspend operation
· Synchronous self-timed writes
· Available in 100 TQFP & 119 BGA Packages
· Burst Capability--linear or interleaved burst order
Functional Description
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36
and 512K by 18 Synchronous-Pipelined Burst SRAMs, re-
spectively. They are designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The CY7C1354V25/CY7C1356V25 is equipped
with the advanced No Bus LatencyTM (NoBLTM) logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically im-
proves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions. The
CY7C1354V25/CY7C1356V25 is pin compatible and function-
ally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.2 ns (200-MHz device).
Write operations are controlled by the Byte Write Selects
(BWS
a
­BWS
d
for CY7C1354V25 and BWS
a
­BWS
b
for
CY7C1356V25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
CLK
A
x
CEN
WE
BWS
x
CE
1
CE
CE
2
OE
256KX36/
MEMORY
ARRAY
Logic Block Diagram
DQ
x
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
Mode
DP
x
CY7C1354
CY7C1356
A
X
DQ
X
DP
X
BWS
X
512KX18
X = 17:0
X = 18:0
X = a, b, c, d
X = a, b
X = a, b
X = a, b
X = a, b, c, d
X = a, b, c, d
OUT
O
UT
R
E
GI
ST
ER
S
and
LO
G
I
C
Selection Guide
7C1354V25-200
7C1356V25-200
7C1354V25-166
7C1356V25-166
7C1354V25-133
7C1356V25-133
7C1354V25-100
7C1356V25-100
Maximum Access Time (ns)
3.2
3.5
4.0
5.0
Maximum Operating Current (mA)
Com'l
475
450
370
300
Maximum CMOS Standby Current (mA) Com'l
10
10
10
10
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
CY7C1354V25
CY7C1356V25
PRELIMINARY
Document #: 38-05263 Rev. **
Page 2 of 27
Pin Configurations
A
A
A
A
A
1
A
0
DN
U
DNU
V
SS
V
DD
DNU
A
A
A
A
A
A
V
DDQ
V
SS
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
V
DD
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
V
SS
V
DDQ
V
DDQ
V
SS
DQc
DQc
V
SS
V
DDQ
DQc
DQc
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
V
SS
V
DDQ
A
A
CE
1
CE
2
BW
S
a
CE
3
V
DD
V
SS
CL
K
WE
CEN
OE
NC
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/L
D
NC
DNU
CY7C1354V25
100-Pin TQFP Packages
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
A
A
A
A
A
A
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
V
DD
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
SN
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DPb
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1
CE
2
NC
NC
BW
S
b
BW
S
a
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
NC
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV
/
L
D
NC
MO
D
E
DNU
CY7C1356V25
BW
S
d
MO
D
E
BW
S
c
DQc
DQc
DQc
DQc
DPc
DQd
DQd
DPd
DQd
SN
DPb
DQb
DQa
DQa
DQa
DQa
DPa
DQb
DQb
(256K x 36)
(512K x 18)
BW
S
b
V
DD
V
DD
CY7C1354V25
CY7C1356V25
PRELIMINARY
Document #: 38-05263 Rev. **
Page 3 of 27
Pin Configurations
(continued)
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQ
a
V
DDQ
NC
NC
DQ
c
DQ
d
DQ
c
DQ
d
A
A
A
A
16M
V
DDQ
CE
2
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
64M
A
DQ
c
DQ
c
DQ
d
DQ
d
TMS
V
DD
A
NC
DP
d
A
A
ADV/LD
A
CE
3
NC
V
DD
A
A
NC
V
SS
V
SS
NC
DP
b
DQ
b
DQ
b
DQ
a
DQ
b
DQ
b
DQ
a
DQ
a
DNU
TDI
TDO
V
DDQ
TCK
V
SS
V
SS
V
SS
V
DD(1)
V
SS
V
SS
V
SS
V
SS
MODE
CE
1
V
SS
OE
V
SS
V
DDQ
BWS
c
A
V
SS
WE
V
DDQ
V
DD
V
DD(1)
V
DD
V
SS
CLK
NC
BWS
a
CEN
V
SS
V
DDQ
V
SS
NC
NC
A
A
A1
A0
V
SS
V
DD
SN
CY7C1354 (256K x 36) - 7 x 17 BGA
DP
c
DQ
b
A
32M
DQ
c
DQ
b
DQ
c
DQ
c
DQ
c
DQ
b
DQ
b
DQ
a
DQ
a
DQ
a
DQ
a
DP
a
DQ
d
DQ
d
DQ
d
DQ
d
BWS
d
119-Ball Bump BGA
BWS
b
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
32M
DQ
a
V
DDQ
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
A
A
A
A
16M
V
DDQ
CE
2
A
NC
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
NC
NC
NC
64M
A
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
TMS
V
DD
A
A
DP
b
A
A
ADV/LD
A
CE
3
NC
V
DD
A
A
NC
V
SS
V
SS
NC
NC
DP
a
DQ
a
DQ
a
DQ
a
DQ
a
DQ
a
DQ
a
DQ
a
DNU
TDI
TDO
V
DDQ
TCK
V
SS
V
SS
V
SS
V
DD(1)
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
CE
1
V
SS
NC
OE
V
SS
V
DDQ
BWS
b
A
V
SS
NC
V
SS
WE
NC
V
DDQ
V
DD
V
DD(1)
V
DD
NC
V
SS
CLK
NC
NC
BWS
a
CEN
V
SS
NC
V
DDQ
V
SS
NC
NC
NC
A
A
A
A1
A0
V
SS
NC
V
DD
SN
CY7C1356(512K x 18) - 7 x 17 BGA
CY7C1354V25
CY7C1356V25
PRELIMINARY
Document #: 38-05263 Rev. **
Page 4 of 27
Pin Definitions (100-Pin TQFP)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
37, 36, 32­35,
44­50, 80­83, 99,
100
37, 36, 32­35,
44­50, 81-83, 99,
100
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the 266,144 ad-
dress locations. Sampled at the rising edge of the CLK.
93, 94
93, 94, 95, 96
BWS
a
BWS
b
BWS
c
BWS
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
con-
trols DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
88
88
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
85
85
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
89
89
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only rec-
ognized if CEN is active LOW.
98
98
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device.
97
97
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
92
92
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and
CE
2
to
select/deselect the device.
86
86
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchro-
nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
87
87
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
(a)58, 59, 62, 63,
68, 69, 72­74
(b)8, 9, 12, 13, 18,
19, 22­24
(a)52, 53, 56­59,
62, 63,
(b)68, 69, 72­75,
78, 79
(c)2, 3, 6­9, 12, 13,
(d)18, 19, 22­25,
28, 29
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQ
a
­DQ
d
are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
CY7C1354V25
CY7C1356V25
PRELIMINARY
Document #: 38-05263 Rev. **
Page 5 of 27
74, 24
51, 80, 1, 30
DP
a
DP
b
DP
c
DP
d
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ
[31:0]
. During write sequences,
DP
a
is controlled by BWS
a
, DP
b
is controlled by BWS
b
,
DP
c
is controlled by BWS
c
, and DP
d
is controlled by
BWS
d
.
31
31
MODE
Input
Strap Pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
14
14
SN
Input-
Asynchronous
This is a reserved pin. Tie it to V
DD
for normal operation.
15, 16, 41, 65, 66,
91
15, 16, 41, 65, 66,
91
V
DD
Power Supply
Power supply inputs to the core of the device.
4, 11, 20, 27, 54,
61, 70, 77
4, 11, 20, 27, 54,
61, 70, 77
V
DDQ
I/O Power
Supply
Power supply for the I/O circuitry.
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
V
SS
Ground
Ground for the device. Should be connected to ground of
the system.
NC
-
No connects. Reserved for address expansion to 512K
depths.
38, 39, 42, 43
38, 39, 42, 43
DNU
-
Do Not Use pins. These pins should be left floating.
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
Pin Definitions (119 BGA)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5, C6, G4, R2, R6,
T2, T3, T5, T6
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5, C6, R2, R6, G4,
T3, T4, T5
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the 266,144
address locations. Sampled at the rising edge of the
CLK.
L5, G3
L5, G5, G3, L3
BWS
a
BWS
b
BWS
c
BWS
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with
WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK. BWS
a
controls DQ
a
and DP
a
,
BWS
b
controls DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
H4
H4
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the ris-
ing edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
B4
B4
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH
(and CEN is asserted LOW) the internal burst
counter is advanced. When LOW, a new address can
be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order
to load a new address.
K4
K4
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs
to the device. CLK is qualified with CEN. CLK is only
recognized if CEN is active LOW.
E4
E4
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and
CE
3
to select/deselect the device.
B2
B2
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
3
to select/deselect the device.