Programmable Spread Spectrum

Clock Generator for EMI Reduction

CY25000

PRELIMINARY

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07424 Rev. *A

Revised December 14, 2002

Features

Benefits

ˇ Wide operating output (SSCLK) frequency range

-- 3200 MHz

Services most PC peripherals, networking, and consumer appli-
cations.

ˇ Programmable spread spectrum with nominal

30-kHz modulation frequency.

-- Center spread: ą0.25% to ą2.5%

-- Down spread: 0.5% to 5.0%

Provides wide range of spread percentages for maximum EMI
reduction, to meet regulatory agency Electro Magnetic Compli-
ance (EMC) requirements. Reduces development and manufac-
turing costs and time-to-market.

ˇ Input frequency range

-- External crystal: 830 MHz fundamental crystals.

-- External reference: 8166 MHz Clock

Eliminates the need for expensive and difficult to use higher order
crystals.

ˇ Integrated phase-locked loop (PLL)

Internal PLL to generate up to 200-MHz output. Able to generate
custom frequencies from an external crystal or a driven source.

ˇ Programmable crystal load capacitor tuning array

Enables fine-tuning of output clock frequency by adjusting C

Load

of the crystal. Eliminates the need for external C

Load

capacitors.

ˇ Low cycle-to-cycle Jitter

Suitable for most PC, consumer, and networking applications

ˇ 3.3V operation

Application compatibility in standard and low-power systems.

ˇ Spread spectrum On/Off function

Provides ability to enable or disable spread spectrum with an ex-
ternal pin.

ˇ Power-down or Output Enable function

Enables low-power state or output clocks to High-Z state.

Logic Block Diagram

XIN/CLKIN

Dividers

PLL

OSC.

REFCLK

VSS

SSCLK

VDD

SSON

XOUT

MUX

Output

and

with

Modulation Control

Programmable Configuration

XIN

XOUT

8-pin SOIC

CY25000

Pin Configuration

XOUT

SSCLK

VSS

SSON

REFCLK

VDD

XIN/CLKIN

PD#/OE

PRELIMINARY

CY25000

Document #: 38-07424 Rev. *A

Page 2 of 9

General Description

The CY25000 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing Electro Magnetic Interfer-
ence (EMI) found in today's high-speed digital electronic sys-
tems.

The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to syn-
thesize and modulate the frequency of the input clock. By fre-
quency modulating the clock, the measured EMI at the funda-
mental and harmonic frequencies are greatly reduced. This
reduction in radiated energy can significantly reduce the cost
of complying with regulatory agency requirements (EMC) and
improve time to market without degrading system perfor-
mance.

The CY25000 uses a factory-programmable configuration
memory array to synthesize output frequency, spread %, crys-
tal load capacitor, reference clock on/off and PD#/OE options.

The spread % is factory programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ą0.25% to ą2.50%. The range for
down spread is from 0.5% to 5.0%. Contact the factory for
smaller or larger spread % amounts if required.

The input to the CY25000 can be either a crystal or a clock
signal. The input frequency range for crystals is 830 MHz,
and for clock signals is 8166 MHz.

The CY25000 has two clock outputs, REFCLK and SSCLK.
The non-spread spectrum REFCLK output has the same fre-
quency as the input of the CY25000. The frequency modulated
SSCLK output can be programmed from 3200 MHz.

The CY25000 products are available in an 8-pin SOIC
(150-mil) package with a commercial operating temperature
range of 0 to 70

Absolute Maximum Rating

Supply Voltage (VDD) .......................................0.5 to +7.0V

DC Input Voltage...................................... 0.5V to V

+ 0.5

Storage Temperature (Non-Condensing) .... 55

C to +125

Junction Temperature ................................ 40

C to +125

Data Retention @ Tj=125

C................................. > 10 Years

Package Power Dissipation...................................... 350 mW

Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)

Pin Description

Pin

Name

Description

XIN/CLKIN

Crystal input or reference clock input

VDD

3.3V voltage supply

PD#/OE

Power-down pin: Active LOW. If PD# = 0, SSCLK and REFCLK are three-stated.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
User has the option of choosing either PD# or OE function.

VSS

GND

SSCLK

Spread spectrum clock output

REFCLK

Buffered reference output.

SSON

Spread spectrum control. 1 = Spread on. 0 = Spread off.

XOUT

Crystal output. Leave this pin floating if external clock is used.

Operating Conditions

Parameter

Description

Min.

Typ.

Max.

Unit

Supply Voltage

3.13

3.30

3.45

Ambient Temperature

°C

LOAD

Max. Load Capacitance @ pin 5 and pin 6

ref

External Reference Crystal
(Fundamental tuned crystals only)

MHz

External Reference Clock

166

MHz

SSCLK

SSCLK output frequency, C

LOAD

= 15 pF

200

MHz

REFCLK

REFCLK output frequency, C

LOAD

= 15 pF

166

MHz

Power-up time for all VDD's to reach minimum
specified voltage (power ramps must be monotonic)

0.05

500

PRELIMINARY

CY25000

Document #: 38-07424 Rev. *A

Page 3 of 9

DC Electrical Characteristics

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

Output High Current

= V

0.5, V

= 3.3V (source)

Output Low Current

= 0.5, V

= 3.3V (sink)

Input High Voltage

CMOS levels, 70% of V

0.7V

Input Low Voltage

CMOS levels, 30% of V

0.3V

Input High Current,
PD#/OE and SSON pins

= V

Input Low Current,
PD#/OE and SSON pins

= V

Output Leakage Current

Three-state output, PD#/OE = 0

XIN

XOUT

[1, 2]

Programmable Capaci-
tance at pin 1 and pin 8

Capacitance at minimum setting

Capacitance at maximum setting

[1]

Input Capacitance at pin 3
and pin 7

Input pins excluding XIN and XOUT

VDD

Supply Current

= 3.45V, Fin = 30 MHz,

REFCLK = 30 MHz, SSCLK = 66 MHz,
C

LOAD

= 15 pF, PD#/OE = SSON = V

DDS

Stand by current

= 3.45V, Device powered down with

PD#/OE = 0V

AC Electrical Characteristics

[1]

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

Output Duty Cycle

SSCLK, Measured at V

Output Duty Cycle

REFCLK, Measured at V

Duty Cycle of CLKIN = 50%.

SR1

Rising Edge Slew Rate

SSCLK from 3 to 100 MHz; REFCLK
from 10 to 100 MHz. 20%80% of V

0.7

1.1

1.5

V/ns

SR2

Falling Edge Slew Rate

SSCLK from 3 to 100 MHz; REFCLK
from 10 to 100 MHz. 80%20% of V

0.7

1.1

1.5

V/ns

SR3

Rising Edge Slew Rate

SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 20%80% of V

1.2

1.6

2.0

V/ns

SR4

Falling Edge Slew Rate

SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 80%20% of V

1.2

1.6

2.0

V/ns

tj1

Peak Cycle-to-Cycle Jitter.
SSCLK pin

SSCLK = 200 MHz. Spread on

100

200

SSCLK = 66 MHz. Spread on

150

300

SSCLK = 14.3 MHz. Spread on

200

400

tj2

Peak Cycle-to-Cycle Jitter,
REFCLK

REFCLK output only

100

200

STP

Power-down Time
(pin3 = PD#)

Time from falling edge on PD# to stopped
outputs (Asynchronous)

150

300

OE1

Output Disable Time
(pin3 = OE)

Time from falling edge on OE to stopped
outputs (Asynchronous)

150

300

OE2

Output Enable Time
(pin3 = OE)

Time from rising edge on OE to outputs
at a valid frequency (Asynchronous)

150

300

PU1

Power-up Time,
Crystal is used

Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)

PU2

Power-up Time,
Reference clock is used

Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)

Notes:

Guaranteed by characterization, not 100% tested.

Contact factory for desired crystal load programming.

PRELIMINARY

CY25000

Document #: 38-07424 Rev. *A

Page 4 of 9

Programming Description

The customers planning to use the CY25000 need to provide
the programming information described as "ENTER DATA" in
Table 1 and should contact local Cypress Sales.

Additional information on the CY25000 can be obtained from
the Cypress web site at www.cypress.com.

Product Functions

Input Frequency (XIN, pin 1 and XOUT

pin 8)

The input to the CY25000 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock sig-
nal is 8 to 166 MHz.

XIN

and C

XOUT

(pin 1 and pin 8)

The load capacitors at pin 1 (C

XIN

) and pin 8 (C

XOUT

) can be

programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).

The required values of C

XIN

and C

XOUT

can be calculated us-

ing the following formula:

XIN

= C

XOUT

= 2C

- C

Where C

is the crystal load capacitor as specified by the crys-

tal manufacturer and C

is the parasitic PCB capacitance.

For example, if a fundamental 16-MHz crystal with C

of 16 pF

is used and C

is 2 pF, C

XIN

and C

XOUT

can be calculated as:

XIN

= C

XOUT

= (2 x 16) 2 = 30 pF.

If using a driven reference, set C

XIN

and

XOUT

to the mini-

mum value 12 pF.

Output Frequency, SSCLK Output (SSCLK, pin 5)

The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON digital control input (SSON = LOW, no mod-
ulation). If modulation is stopped, the clock frequency is the
nominal value of the synthesized frequency without modula-
tion (spread % = 0). The range of synthesized clock is from
3200 MHz.

Spread Percentage (SSCLK, pin 5)

The SSCLK frequency can be programmed at any percentage
value from ą0.25% to ą2.5% for Center Spread and from
0.5% to 5.0% Down Spread.

Reference Output (REFOUT, pin 6)

The reference clock output has the same frequency and the
same phase as the input clock. This output can be pro-
grammed to be enabled (clock on) or disabled (High-Z, clock
off). If this output is not needed, it is recommended that users
request the disabled (High-Z, Clock Off) option.

Frequency Modulation

The frequency modulation is programmed at 30 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.

Power-down or Output Enable (PD# or OE, pin 3):

Users can select either PD# or OE function which are also
factory programmable.

Table 1.

Pin

Function

Input

Frequency

XIN

and

XOUT

Output

Frequency

Spread

Percent

Reference

Output

Power-down or

Output Enable

Frequency

Modulation

Pin Name

XIN and XOUT

XIN and

XOUT

SSCLK

REFOUT

PD#/OE

SSCLK

Pin#

1 and 8

Units

MHz

On or Off

Select PD# or OE

kHz

Program

Value

ENTER

DATA

ENTER

DATA

ENTER

DATA

ENTER

DATA

ENTER

DATA

ENTER

DATA

Application Circuit

[3, 4, 5]

Notes:

Since the load capacitors (C

XIN

and C

XOUT

) are provided by the CY25000, no external capacitors are needed on the XIN

and XOUT pins to match the crystal

load capacitor (C

). Only a single 0.1-

F bypass capacitor is required on the V

pin.

If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).

If SSON (pin 7) is LOW (V

), the frequency modulation will be stopped on SSCLK pin (pin 5).

VDD

XOUT

VSS

SSCLK

REFCLK

XIN

SSON

5000

Power

0.1

VDD

PD#/OE

Crystal

Part Number CY25000