FailsafeTM 2.5V/ 3.3V Zero Delay Buffer

CY23FS08

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07518 Rev. *A

Revised May 12, 2004

Features

· Internal DCXO for continuous glitch-free operation
· Zero input-output propagation delay
· Low jitter (< 35 ps RMS) outputs
· Low output-output skew (< 200 ps)
· 1 MHz200 MHz reference input
· Supports industry standard input crystals
· 200 MHz (commercial), 166 MHz (industrial) outputs
· 5V-tolerant inputs
· Phase-locked loop (PLL) Bypass Mode
· Dual Reference Inputs
· 28-pin SSOP
· Split 2.5V or 3.3V output power supplies
· 3.3V core power supply
· Industrial temperature available

Functional Description

The CY23FS08 is a FailSafe

Zero Delay Buffer with two

reference clock inputs and eight phase-aligned outputs. The

device provides an optimum solution for applications where

continuous operation is required in the event of a primary clock

failure.
Continuous, glitch-free operation is achieved by using a

DCXO, which serves as a redundant clock source in the event

of a reference clock failure by maintaining the last frequency

and phase information of the reference clock.
The unique feature of the CY23FS08 is that the DCXO is in

fact the primary clocking source, which is synchronized

(phase-aligned) to the external reference clock. When this

external clock is restored, the DCXO automatically resynchro-

nizes to the external clock.
The frequency of the crystal, which will be connected to the

DCXO must be chosen to be an integer factor of the frequency

of the reference clock. This factor is set by four select lines:

S[4:1]. please see Table 1. The CY23FS08 has three split

power supplies; one for core, another for Bank A outputs and

the third for Bank B outputs. Each output power supply, except

VDDC can be connected to either 2.5V or 3.3V. VDDC is the

power supply pin for internal circuits and must be connected

to 3.3V.

Block Diagram

Pin Configuration

CLKA[1:4]

CLKB[1:4]

DCXO

Decoder

Failsafe

Block

PLL

XIN XOUT

REF2

FBK

S[4:1]

FAIL# /SAFE

REF1

REFSEL

CLKB1

VDDB

CLKB2

VDDB

XIN

VDDC

FAIL#/SAFE

28
27
26
25
24
23
22
21

1
2
3
4
5
6
7
8

CY23FS08

28 pin SSOP

REF1
REF2

VSSB

REFSEL
FBK
VSSA
CLKA1

CLKA2
S1

VDDA

10
11
12
13
14

VSSB

CLKB3
CLKB4

20
19
18
17
16
15

VSSA
CLKA3
CLKA4
VDDA

XOUT

CY23FS08

Document #: 38-07518 Rev. *A

Page 2 of 12

Pin Definitions

Pin Number

Pin Name

Description

1,2

REF1,REF2

5V-tolerant, reference clock inputs

[4]

4,5,10,11

CLKB[1:4]

Bank B clock outputs.

[1,2]

25,24,19,18

CLKA[1:4]

Bank A clock outputs.

[1,2]

FBK

Feedback input to the PLL.

[1,4]

23,6,7,22

S[1:4]

Frequency select pins/PLL and DCXO bypass.

[3]

XIN

Reference crystal input.

XOUT

Reference crystal output.

FAIL#/SAFE

Valid reference indicator. A high level indicates a valid reference input.

VDDC

3.3V power supply for the internal circuitry.

8,12

VDDB

2.5V or 3.3V power supply for Bank B outputs.

3,9

VSSB

Ground.

17,21

VDDA

2.5V or 3.3V power supply for Bank A outputs.

20,26

VSSA

Ground.

REFSEL

Reference select. Selects the active reference clock from either REF1 or REF2.

REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected.

Table 1. Configuration Table

S[4:1]

XTAL (MHz)

REF(MHz)

OUT(MHz)

REF:OUT

ratio

REF:XTAL

ratio

Out:XTAL ratio

Min.

Max.

Min.

Max.

Min.

Max.

0000

PLL and DCXO Bypass mode

1000

8.33

16.67

60.00

8.33

30.00

÷2

1110

9.50

57.00

180.00

28.50

90.00

÷2

0101

8.50

6.80

24.00

1.70

6.00

÷4

4/5

1/5

1011

8.33

25.00

90.00

6.25

22.50

÷4

3/4

0011

8.33

2.78

10.00

2.78

10.00

1/3

1001

8.33

30.00

8.33

30.00

1111

8.00

32.00

100.00

32.00

100.00

1100

8.00

64.00

200.00

64.00

200.00

0001

8.33

1.04

3.75

2.08

7.50

1/8

1/4

0110

8.33

4.17

15.00

8.33

30.00

1/2

1101

8.33

16.67

60.00

33.33

120.00

0100

8.33

4.17

15.00

16.67

60.00

1/2

1010

8.33

12.50

45.00

50.00

180.00

3/2

0010

8.33

1.39

5.00

11.11

40.00

1/6

4/3

0111

8.33

6.25

22.50

50.00

180.00

3/4

Notes:

For normal operation, connect either one of the eight clock outputs to the FBK input.

Weak pull-downs on all outputs.

Weak pull-ups on these inputs.

Weak pull-downs on these inputs.

CY23FS08

Document #: 38-07518 Rev. *A

Page 3 of 12

FailSafe Function

The CY23FS08 is targeted at clock distribution applications

that could or which currently require continued operation

should the main reference clock fail. Existing approaches to

this requirement have utilized multiple reference clocks with

either internal or external methods for switching between

references. The problem with this technique is that it leads to

interruptions (or glitches) when transitioning from one

reference to another, often requiring complex external circuitry

or software to maintain system stability. The technique imple-

mented in this design completely eliminates any switching of

references to the PLL, greatly simplifying system design.

The CY23FS08 PLL is driven by the crystal oscillator, which is

phase-aligned to an external reference clock so that the output

of the device is effectively phase-aligned to reference via the

external feedback loop. This is accomplished by utilizing a

digitally controlled capacitor array to pull the crystal frequency

over an approximate range of +300 ppm from its nominal

frequency.

In this mode, should the reference frequency fail (i.e., stop or

disappear), the DCXO maintains its last setting and a flag

signal (FAIL#/SAFE) is set to indicate failure of the reference

clock.
The CY23FS08 provides four select bits, S1 through S4 to

control the reference to crystal frequency ratio. The DCXO is

internally tuned to the phase and frequency of the external

reference only when the reference frequency divided by this

ratio is within the DCXO capture range. If the frequency is out

of range, a flag will be set on the FAIL#/SAFE pin notifying the

system that the selected reference is not valid. If the reference

moves in range, then the flag will be cleared, indicating to the

system that the selected reference is valid.

Table 2. FailSafe Timing Table

Parameter

Description

Conditions

Min.

Max.

Unit

FSL

Fail#/Safe Assert Delay

Measured at 80% to 20%, Load = 15 pF

See Figure 2

FSH

Fail#/Safe Deassert Delay

Measured at 80% to 20%, Load = 15 pF

See Figure 2

R E F

O U T

F A I L # / S A F E

F S L

F S H

Figure 1. Fail#/Safe Timing for Input Reference Failing Catastrophically

R E F

X T A L

= 4

( in a b o v e e x a m p le )

F S L ( m a x )

= 2

R E F

x n

(

)

2 5 n s

F S H ( m in )

= 1 2

R E F

x n

(

)

2 5 n s

Figure 2. Fail#/Safe Timing Formula

CY23FS08

Document #: 38-07518 Rev. *A

Page 7 of 12

XTAL Selection Criteria and Application Example

Choosing the appropriate XTAL will ensure the FailSafe device

will be able to span an appropriate frequency of operation.

Also, the XTAL parameters will determine the holdover

frequency stability. Critical parameters are as follows. Our

recommendation is to choose:

· Low C0/C1 ratio (240 or less) so that the XTAL has enough

range of pullability.

· Low temperature frequency variation
· Low manufacturing frequency tolerance
· Low aging.

C0 is the XTAL shunt capacitance (3 pF 7 pF typ.).

C1 is the XTAL motional capacitance (10 fF 30 fF typ).
The capacitive load as "seen" by the XTAL is across its

terminals. It is named Clmin (for minimum value), and Clmax

(for maximum value).These are used for calculating the pull

range.
Please note that the Cl range "center" is approximately 20 pF,

but we may not want a XTAL calibrated to that load. This is

because the pullability is not linear, as represented in the

equation above. Plotting the pullability of the XTAL shows this

expected behavior as shown in Figure 8. In this example,

specifying a XTAL calibrated to 14 pF load provides a

balanced ppm pullability range around the nominal frequency.

Notes:

The above example shows the maximum range the FailSafe internal capacitor array is capable of (0 to 48.6 pF).Cypress recommends the min./max capacitor

array values be programmed to a narrower range such as 6 pF30 pF, or 7.5 pF27 pF. This ensures the XTAL operates between series resonance and

anti-resonance. Please contact Cypress for choosing these range settings.

Clmin = (12 pF IC input cap + 0 pF pulling cap+ 6 pF trace cap on board)/2 = 9 pF
Clmax = (12 pF IC input cap + 48 pF pulling cap+ 6 pF trace cap on board)/2 = 33 pF
Pull Range =(fClminfClmax)/fClmin = ((C1)/2)[(1/(C0+Clmin))(1/(C0+Clmax))]
Pull Range in ppm = ((C1)/2)[(1/(C0+Clmin))(1/(C0+Clmax))] × 10

Example:

[5]

Figure 8. Frequency vs. Cload Behavior for Example XTAL

Pullability Range Vs. Cload

(Normalized to 14pF Cload)

-400.00

-300.00

-200.00

-100.00

0.00

100.00

200.00

300.00

400.00

8 10 12 14 16 18 20 22 24 26 28 30 32 34

Cload (pF)

Delta Freq. from nom

C0/C1 = 200

C0/C1 = 300

C0/C1 = 400

CY23FS08

Document #: 38-07518 Rev. *A

Page 8 of 12

Calculated value of the pullability range for the XTAL with

C0/C1 ratio of 200, 300 and 400 are shown in Table 3. For this

calculation Cl(min) = 8pF and Cl(max)= 32pF has been used.

Using a XTAL that has a nominal frequency specified at load

capacitance of 14pF, almost symmetrical pullability range has

been obtained.
Next, it is important to calculate the pullability range including

error tolerances. This would be the capture range of the input

reference frequency that the FailSafe device and XTAL combi-

nation would reliably span.

Calculating the capture range involves subtracting error

tolerances as follows:
Parameter........................................................ f error (ppm)
Manufacturing frequency tolerance ...................................15
Temperature stability ..........................................................30
Aging ................................................................................... 3
Board/trace variation ........................................................... 5
Total ....................................................................................53
Example: Capture Range for XTAL with C0/C1 Ratio of 200
Negative Capture Range= 385 ppm + 53 ppm = 332 ppm
Positive Capture Range = 333 ppm 53 ppm = +280 ppm
It is important to note that the XTAL with lower C0/C1 ratio has

wider pullability/capture range as compared to the higher

C0/C1 ratio. This will help the user in selecting the appropriate

XTAL for use in the FailSafe application.

Table 3. Pullability Range from XTAL with Different C0/C1

Ratio

C0/C1 Ratio

Cload(min.)

Cload(max.)

Pullability

Range

200

8.0

32.0

385 333

300

8.0

32.0

256 222

400

8.0

32.0

192 166

Absolute Maximum Conditions

Parameter

Description

Condition

Min.

Max.

Unit

Supply Voltage

0.5

4.6

Input Voltage

Relative to V

0.5

+0.5

VDC

Temperature, Storage

Non Functional

+150

°C

Temperature, Operating Ambient

Commercial Grade

°C

Industrial Grade

°C

Temperature, Junction

Functional

125

°C

ESD

HBM

ESD Protection (Human Body Model)

MIL-STD-883, Method 3015

2000

Dissipation, Junction to Case

Mil-Spec 883E Method 1012.1

36.17

°C/W

Dissipation, Junction to Ambient

JEDEC (JESD 51)

100.6

°C/W

UL94

Flammability Rating

At 1/8 in.

MSL

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

Recommended Pullable Crystal Specifications

[6]

Parameter

Name

Comments

Min.

Typ.

Max.

Unit

NOM

Nominal crystal frequency

Parallel resonance, fundamental mode,

AT cut

8.00

30.00

MHz

LNOM

Nominal load capacitance

Equivalent series resistance (ESR)

Fundamental mode

Ratio of third overtone mode ESR to

fundamental mode ESR

Ratio used because typical R

values

are much less than the maximum spec

Crystal drive level

No external series resistor assumed

0.5

3SEPLI

Third overtone separation from 3*F

NOM

High side

300

ppm

3SEPLO

Third overtone separation from 3*F

NOM

Low side

150

ppm

Crystal shunt capacitance

Ratio of shunt to motional capacitance

180

250

Crystal motional capacitance

14.4

21.6

Note:

Ecliptek ECX-5788-13.500M, ECX-5807-19.440M, ECX-5872-19.53125M, ECX-5806-18.432M, ECX-5808-27.000M, ECX-5884-17.664M,

ECX-5883-16.384M,ECX-5882-19.200M,ECX-5880-24.576M meet these specifications.

CY23FS08

Document #: 38-07518 Rev. *A

Page 9 of 12

Table 4. Operating Conditions for FailSafe Commercial/Industrial Temperature Devices

Parameter

Description

Min. Max. Unit

DDC

3.3V Supply Voltage

3.135 3.465

DDA,

DDB

2.5V Supply Voltage Range

2.375 2.625

3.3V Supply Voltage Range

3.135 3.465

Ambient Operating Temperature, Commercial

°C

Ambient Operating Temperature, Industrial

°C

Output Load Capacitance (Fout < 100 MHz)

Output Load Capacitance (Fout > 100 MHz)

Input Capacitance (except XIN)

XIN

Crystal Input Capacitance (all internal caps off)

Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05

500

Table 5. Electrical Characteristics for FailSafe Commercial/Industrial Temperature Devices

Parameter

Description

Test Conditions

Min.

Typ.

Max.

Unit

Input Low Voltage

CMOS Levels, 30% of V

0.3xV

Input High Voltage

CMOS Levels, 70% of V

0.7xV

Input Low Current

(100k pull-up only)

µA

Input High Current

(100k pull-down only)

µA

Output Low Current

=0.5V, V

= 2.5V

=0.5V, V

= 3.3V

Output High Current

0.5V, V

= 2.5V

0.5V, V

= 3.3V

DDQ

Quiescent Current

All Inputs grounded, PLL and DCXO in

bypass mode, Reference Input = 0

250

µA

Table 6. Switching Characteristics for FailSafe Commercial/Industrial Temperature Devices

Parameter

[8]

Description

Test Conditions

Min.

Max.

Unit

REF

Reference Frequency

Commercial Grade

1.04

200

MHz

Industrial Grade

1.04

166.7

MHz

OUT

Output Frequency

15-pF Load, Commercial Grade

1.70

200

MHz

15-pF Load, Industrial Grade

1.70

166.7

MHz

XIN

DCXO Frequency

8.0

MHz

Duty Cycle

Measured at V

SR(I)

Input Slew Rate

Measured on REF1 Input, 30% to 70% of V

0.5

4.0

V/ns

SR(O)

Output Slew Rate

Measured from 20% to 80% of V

= 3.3V, 15 pF Load

0.8

4.0

V/ns

Measured from 20% to 80% of V

=2.5V, 15 pF Load

0.4

3.0

V/ns

SK(O)

Output to Output Skew All outputs equally loaded, measured at V

200

SK(IB)

Intrabank Skew

All outputs equally loaded, measured at V

SK(PP)

Part to Part Skew

Measured at V

500

(

)

[7]

Static Phase Offset

Measured at V

250

)

[7]

Dynamic Phase Offset Measured at V

200

J(CC)

Cycle-to-Cycle Jitter

Load = 15 pF, f

OUT

6.25 MHz

200

RMS

LOCK

PLL Lock Time

Stable power supply, valid clock at REF

1.0

Note:

The

(

)

reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as

SR(I) is maintained.

Parameters guaranteed by design and characterization, not 100% tested in production.

Includes typical board trace capacitance of 67pF each XIN, XOUT.

CY23FS08

Document #: 38-07518 Rev. *A

Page 11 of 12

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.

Package Drawing and Dimensions

FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks

of their respective holders.

28-Lead (5.3 mm) Shrunk Small Outline Package O28

51-85079-*C

Part Number CY23FS08