10-output, 400-MHz LVPECL Zero Delay Buffer

CY23020-3

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07473 Rev. *A

Revised June 5, 2003

Features

· 400-ps max Total Timing Budget

(TTB

) window

· 10 LVPECL outputs
· 1 LVPECL differential input
· Selectable output frequency range from 100 to 400 MHz
· Multiply by 2 option
· 15-ps RMS Cycle-Cycle Jitter
· Power-down mode
· Lock indicator
· 3.3V power supply
· Available in 48-pin QFN package

Overview

TheCY23020-3 is a high-performance 400-MHz LVPECL
Output phase-locked loop (PLL)-based zero delay buffer
(ZDB) designed for high- speed clock distribution applications.
The device features a guaranteed TTB window specifying all
occurrences of output clocks with respect to the input
reference clock across variations in voltage, temperature,
process, frequency, and ramp rate.

Additionally, the CY23020-3 can be used as a fan-out buffer
via the S[1:2] control pins. In this mode, the PLL is bypassed
and the reference clock is routed to the output buffers.

Block Diagram

Pin Configurations

CY23020-3

F
B
O
U
T
+

V
D
D

F
B
I
N
+

F
B
I
N
-

N
C

L
O
C
K

V
D
D
C

G
N
D
C

R
E
F
-

R
E
F
+

V
D
D

Q
9
+

Q
4
-

G
N
D

S
2

S
1

M
U
L

R
A
N
G
E

G
N
D
C

V
D
D
C

G
N
D
C

G
N
D

Q
5
-

FBOUT-

GND

Q1-

Q1+

VDD

Q2+

Q2-

GND

Q3-

Q3+

VDD

Q4+

Q9-

GND

Q8-

Q8+

VDD

Q7+

Q7-

GND

Q6-

Q6+

VDD

Q5+

Q1+

Q1-

Q3+

Q3-

Q2+

Q2-

Q4+

Q4-

Q5+

Q4-

Q6+
Q6-

Q7+
Q7-

Q8+
Q8-

Q9+
Q9-

FBOUT+

FBOUT-

PLL

Control

Logic

FBIN-

FBIN+

S1:2

RANGE

MUL

REF-

REF+

LOCK

CY23020-3

Document #: 38-07473 Rev. *A

Page 2 of 9

Pin Definitions

[1]

Pin Name

Pin No.

Pin

Type

Pin Description

REF+
REF-

39
40

Reference Inputs. Output signals are synchronized to the crossing point of REF+ and REF
signals. In DC mode, the REF+/REF- inputs must be held at opposite logical states. For
optimal performance, the impedances seen by these two inputs must be equal.

FBIN+
FBIN-

46
45

Feedback Inputs. Input FBIN+/FBIN- must be fed by one of the outputs to ensure proper
functionality. If the trace between FBIN+/FBIN- and FBOUT+/FBOUT- is equal in length to
the traces between the outputs and the signal destinations, then the signals received at the
destinations will be synchronized to the clock signal at REF+/REF- inputs. In DC mode,
FBIN+/FBIN- inputs must be held at opposite logical states. For best performance, the
impedances seen by these two inputs must be equal.

FBOUT+
FBOUT-

Feedback Output. In order to complete the phase locked loop, similar polarity outputs must
be connected back to the FBIN+ and FBIN- pins. Any of the outputs may actually be used
as the feedback source.

Q1+, Q1-

4, 3

Differential Q1 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q2+, Q2-

6, 7

Differential Q2 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q3+, Q3-

10, 9

Differential Q3 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q4 +, Q4-

12, 13

Differential Q4 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q5+, Q5-

25, 24

Differential Q5 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q6+, Q6-

27, 28

Differential Q6 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q7+, Q7-

31, 30

Differential Q7 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q8+, Q8-

33, 34

Differential Q8 Outputs. Refer to Tables 1,2, and 3 for configuration.

Q9+, Q9-

37, 36

Differential Q9 Outputs. Refer to Tables 1,2, and 3 for configuration.

RANGE

Frequency Range Selection Input. To determine the correct connection for this pin, refer
to Table 2. This should be a static input

LOCK

PLL Locked Output. When this output is HIGH, the PLL in the CY23020-3 is in steady state
operation mode (Locked). When this signal is LOW, the PLL is in the process of locking onto
the reference signal.

S1:2

16, 15

Output/PLL Enable Selection Bits. Refer to Table 1.

VDDC

20, 21, 42

Analog Power Connection. Connect to 3.3V.

GNDC

19, 22, 41

Analog Ground Connection. Connect to common system ground plane.

VDD

5, 11, 26, 32,

38, 47

Output Buffer Power Connections. Connect 3.3V

GND

2, 8, 14, 23,

29, 35

Ground Connections. Connect to common system ground plane.

MUL

[2]

Multiplication Factor Select. When set HIGH, the outputs will run at twice the speed of the
reference signal. This should be a static input.

Do Not Connect. This pin must be left floating. This pin is used by the factory for testing
purposes.

Table 1. Output Configuration

Outputs

PLL

Three-state

Shutdown

Reserved

Reference Input

Shutdown

PLL Output

Enabled

Notes:

There are no power-up sequence requirements on the power supply pins of the CY23020-3.

RANGE and MUL have a ~100k pull-down.

CY23020-3

Document #: 38-07473 Rev. *A

Page 3 of 9

How to Implement Zero Delay

Typically, ZDBs multiply (fan-out) single-clock signals quantity
while simultaneously reducing or mitigating the time delay
associated with passing the clock through a buffering device.
In many cases the output clock is adjusted, in phase, to occur
later or more often before the device's input clock to
compensate for a design's physical delay inadequacies. Most
commonly this is done using a simple PCB trace as a time
delay element. The longer the trace the earlier the output clock
edges occur with respect to the reference input clock edges.

In this way such effects as undesired transit time of a clock
signal across a PCB can be compensated for.

Inserting Other Devices in Feedback Path

Due to the fact that the device has an external feedback path
the user has a wide range of control over its output to input
skewing effect. One of these is to be able to synchronize the
outputs of an external clock that is resultant from any of the
output clocks. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.

Referring to Figure 1, if the traces between the ASIC/buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin (B), the
signals at the destination(s) device (C) will be driven high at
the same time the Reference clock provided to the ZDB goes
high. Synchronizing the other outputs of the ZDB to the outputs
from the ASIC/Buffer is more complex however, as any propa-
gation delay in the ASIC/Buffer must be accounted for.

There are constraints when inserting other devices. If the
devices contain PLLs or excessively long delay times they can
easily cause the overall clocking system to become unstable
as the components interact. For these designs it is advisable
to contact Cypress for applications support.

Table 2. Frequency Range Setting

RANGE

Output Frequency Range

100200 MHz

200400 MHz

Table 3. Frequency Multiplication Table

MUL

Output Frequency

= REF

= 2 * REF

Reference

Signal

Feedback

Input

ASIC/
Buffer

Zero
Delay
Buffer

Figure 1. Output Buffer in Feedback Path

Table 4. Absolute Maximum Ratings

[3]

Parameter

Description

Rating

Unit

Voltage on any V

pin with respect to GND

0.5 to +5.0

Voltage on any input pin with respect to GND

0.5 to V

+ 0.5

STG

Storage Temperature

65 to +150

°C

Operation Temperature (QFN)

40 to 85

°C

Junction Temperature

135

°C

Table 5. PECL DC Output Specification

[4]

Parameter

Description

Conditions

= 3.135

= 3.3

= 3.465

Min.

Max.

Min.

Max.

Min.

Max.

1.835

2.435

2.6

2.165

2.765

1.135

1.735

1.3

1.9

1.465

2.065

(rel to V

)

1.3

0.7

1.3

0.7

1.3

0.7

(rel to V

)

1.4

These result in the following mid point values:

[4]

MID

((V

OH +

)/2)

1.485

2.085

1.65

2.25

1.815

2.415

MID

Relative to V

1.65

1.05

1.65

1.05

1.65

1.05

Notes:

Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at
these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may
affect reliability.

The midpoint voltage is average value of a waveform. For differential signals the midpoint is assumed to be the same for both the true and complement since
the V

and V

of both the true and complement signals in general should be the same. V

MID

is not necessarily equal to the differential crossover voltage,

which may be skewed if there is differential time delays between the signals.

CY23020-3

Document #: 38-07473 Rev. *A

Page 4 of 9

Min.

Max.

Unit

Power-down Current

70°C, V

max

100

= 0

= V

100

Table 5. PECL DC Output Specification (continued)

[4]

Parameter

Description

Conditions

= 3.135

= 3.3

= 3.465

Min.

Max.

Min.

Max.

Min.

Max.

Table 6. V

DDC

= 3.3V ±5%, V

= 3.3V ±5% (See Test Set-ups, C

= 5 pF)

Parameter

Description

Condition

Min.

Typ. Max.

Unit

Loaded, V

max, Cold, 400 MHz,

all outputs switching

300

REF or FBIN ± Pin Capacitance

[5]

Load Cap

ISW

Single Ended Input Swing

0.5

1.25

[6]

Input Crossover Voltage
(expressed relative to V

)

1.79

0.96

Input Slew Rate

Measured from V

IX MEAS

+ 0.15 to

IX MEAS

0.15. (20 80% of a min

input swing sig.)

0.9

V/ns

OSW

Single Ended Output Swing

0.6

1.1

[7]

Output Crossing Point

MID

= (VH_

MEAS

VL_

MEAS

)/2

MID

0.20

MID

0.20

[8]

Output Crossing Point (relative
to V

)

MID

= (VH_

MEAS

VL_

MEAS

)/2

1.79

0.96

Table 7. V

DDC

= 3.3V ±5%, V

= 3.3V ±5% (See Test Set-ups, C

= 5 pF)

Parameter

Description

Condition

Min.

Typ. Max.

Unit

Output Rise/Fall Slew
Rate

Measured from V

IX MEAS

+ 0.15 to V

IX MEAS

0.15.

(2080% of a min input swing sig.)

0.9

V/ns

Input Duty Cycle

Input duty cycle

Output Duty Cycle

Differential crossing point

PDIO

REFin-FBin prop delay

External feedback REF, FB same frequency

200

PDIOD

REFin-FBin prop delay

External feedback REF, FB same frequency x2

150

PDO

FBout to any output prop
delay

325

100

PDOB

Output-Output skew within a bank

150

PDOB133

Output-Output skew @133 MHz

Total Timing Budget

400

JCCPP

Cycle-Cycle Jitter (1000
cycles) p-p

REF and outputs, same frequency

100

JCCRMS

RMS Cycle-Cycle Jitter

REF and outputs, same frequency

Tjccop

Ref = x2

125

Tjrms

Ref = x2

Notes:

Same as input. PECL is assumed to drive single point loads.

This is the output DC mid-voltage range ± the crossover voltage tolerance. Refer Input Voltage is assumed to be derived from same supply as part. This is why
it is spec'd relative to V

Crossover is within ± 20% of the center of the minimum swing.

Part Number CY23020-3