High-accuracy EPROM Programmable
Single-PLL Clock Generator
CY2077
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
·
CA 95134
·
408-943-2600
Document #: 38-07210 Rev. *A
Revised July 22, 2002
Features
Benefits
· High-accuracy PLL with 12-bit multiplier and 10-bit
divider
Enables synthesis of highly accurate and stable output clock
frequencies with zero PPM
· EPROM-programmability
Enables quick turnaround of custom frequencies
· 3.3V or 5V operation
Supports industry standard design platforms
· Operating frequency
-- 390 kHz133 MHz at 5V
-- 390 kHz100 MHz at 3.3V
Services most PC, networking, and consumer applications
· Reference input from either a 1030 MHz fundamental
toned crystal or a 175 MHz external clock
Lowers cost of oscillator as PLL can be programmed to a high
frequency using either a low-frequency, low-cost crystal, or an
existing system clock
· EPROM-selectable TTL or CMOS duty-cycle levels
Duty cycle centered at 1.5V or V
DD
/2
Provides flexibility to service most TTL or CMOS applications
· Sixteen selectable post-divide options, using either PLL
or reference oscillator/external clock
Provides flexibility in output configurations and testing
· Programmable PWR_DWN or OE pin, with
asynchronous or synchronous modes
Enables low-power operation or output enable function and
flexibility for system applications, through selectable instanta-
neous or synchronous change in outputs
· Low jitter outputs typically
-- 80 ps at 3.3V/5V
Suitable for most PC, consumer, and networking applications
· Controlled rise and fall times and output slew rate
Has lower EMI than oscillators
· Available in both commercial and industrial
temperature ranges
Suitable to fit most applications
· Factory-programmable device options
Easy customization and fast turnaround
Osc
i
ll
at
o
r
Logic Block Diagram
XTALIN
PWR_DWN
Configuration
Cry
s
t
a
l
CLKOUT
/ 1, 2, 4, 8, 16, 32, 64, 128
or OE
MUX
HIGH
ACCURACY
PLL
EPROM
1
2
3
4
5
8
7
6
V
DD
XTALOUT
XTALIN
PD/OE
V
SS
CLKOUT
V
SS
V
SS
8-pin
Top View
Q
10 bits
P
12 bits
Phas
e D
e
tec
t
or
Charge
Pump
VCO
or
external clock
Pin Configuration
Note:
1.
When using an external clock source, leave XTALOUT floating.
XTALOUT
[1]
CY2077
Document #: 38-07210 Rev. *A
Page 2 of 13
Functional Description
The CY2077 is an EPROM-programmable, high-accuracy,
general-purpose, PLL-based design for use in applications
such as modems, disk drives, CD-ROM drives, video CD
players, DVD players, games, set-top boxes, and
data/telecommunications.
The CY2077 can generate a clock output up to 133 MHz at 5V
or 100 MHz at 3.3V. It has been designed to give the customer
a very accurate and stable clock frequency with little to zero
PPM error. The CY2077 contains a 12-bit feedback counter
divider and 10-bit reference counter divider to obtain a very
high resolution to meet the needs of stringent design specifi-
cations. Furthermore, there are eight output divide options of
/1, /2, /4, /8, /16, /32, /64, and /128. The output divider can
select between the PLL and crystal oscillator output/external
clock, providing a total of 16 different options to add more flexi-
bility in designs. TTL or CMOS duty cycles can be selected.
Power management with the CY2077 is also very flexible. The
user may choose either a PWR_DWN or an OE feature with
which both have integrated pull-up resistors. PWR_DWN and
OE signals can be programmed to have asynchronous and
synchronous timing with respect to the output signal. There is
a weak pull-down on the output that will pull CLKOUT LOW
when either the PWR_DWN or OE signal is active. This weak
pull-down can easily be overridden by another clock signal in
designs where multiple clock signals share a signal path.
Multiple options for output selection, better power distribution
layout, and controlled rise and fall times enable the CY2077 to
be used in applications that require low jitter and accurate
reference frequencies.
EPROM Configuration Block
Table 1 summarizes the features configurable by EPROM.
PLL Output Frequency
The CY2077 contains a high-resolution PLL with 12-bit multi-
plier and 10-bit divider.
[2]
The output frequency of the PLL is
determined by the following formula:
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
The calculation of P and Q values for a given PLL output
frequency is handled by the CyClocks
software. Refer to the
"Custom Configuration Request Procedure" section for details.
Power Management Features
PWR_DWN and OE options are configurable by EPROM
programming for the CY2077. In PWR_DWN mode, all active
circuits are powered down when the control pin is set LOW.
When the control pin is set back HIGH, both the PLL and oscil-
lator circuit must re-lock. In the case of OE, the output is
three-stated and weakly pulled down when the control pin is
set LOW. The oscillator and PLL are still active in this state,
which leads to a quick clock output return when the control pin
is set back HIGH.
Additionally, PWR_DWN and OE can be configured to occur
asynchronously or synchronously with respect to CLKOUT. In
asynchronous mode, PWR_DWN or OE disables CLKOUT
immediately (allowing for logic delays), without respect to the
current state of CLKOUT. Synchronous mode will prevent
output glitches by waiting for the next falling edge of CLKOUT
after PWR_DWN or OE becomes asserted. In either
asynchronous or synchronous setting, the output is always
enabled synchronously by waiting for the next falling edge of
CLKOUT.
Table 1. EPROM Adjustable Features
EPROM Adjustable Features
Adjust
Freq.
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing (synchronous or asynchronous)
F
PLL
2
P
5
+
(
)
·
Q
2
+
(
)
---------------------------
F
REF
·
=
Pin Summary
Pin Name
Pin #
Pin Description
V
DD
1
Voltage supply.
V
SS
5,6,7
Ground (all the pins have to be grounded).
X
D
2
Crystal output (leave this pin floating when external reference is used).
X
G
3
Crystal input or external input reference.
PWR_DWN / OE 4
EPROM programmable power-down or output enable pin. Weak pull-up.
CLKOUT
8
Clock output. Weak pull-down.
Note:
2.
When using CyClocks, please note that the PLL frequency range is from 50 MHz to 250 MHz for 5V V
DD
supply, and 50 MHz to 180 MHz for 3V V
DD
supply.
The output frequency is determined by the selected output divider.
CY2077
Document #: 38-07210 Rev. *A
Page 3 of 13
Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ..................................................0.5 to +7.0V
Input Voltage........................................... 0.5V to V
DD
+0.5V
Storage Temperature (Non-Condensing).... 55°C to +150°C
Junction Temperature ................................................. 150°C
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Device Functionality: Output Frequencies
Symbol
Description
Condition
Min.
Max.
Unit
Fo
Output frequency
V
DD
= 4.55.5V
0.39
133
MHz
V
DD
= 3.03.6V
0.39
100
MHz
Operating Conditions for Commercial Temperature Device
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
3.0
5.5
V
T
A
Operating Temperature, Ambient
0
+70
°C
C
TTL
Max. Capacitive Load on outputs for TTL levels
V
DD
= 4.5 5.5V, Output frequency = 1 40 MHz
V
DD
= 4.5 5.5V, Output frequency = 40 125 MHz
V
DD
= 4.5 5.5V, Output frequency = 125 133 MHz
50
25
15
pF
pF
pF
C
CMOS
Max. Capacitive Load on outputs for CMOS levels
V
DD
= 4.5 5.5V, Output frequency = 1 40 MHz
V
DD
= 4.5 5.5V, Output frequency = 40 125 MHz
V
DD
= 4.5 5.5V, Output frequency = 125 133 MHz
V
DD
= 3.0 3.6V, Output frequency = 1 40 MHz
V
DD
= 3.0 3.6V, Output frequency = 40 100 MHz
50
25
15
30
15
pF
pF
pF
pF
pF
X
REF
Reference Frequency, input crystal with C
load
= 10 pF
10
30
MHz
Reference Frequency, external clock source
1
75
MHz
Electrical Characteristics
T
A
= 0
°
C to +70
°
C
Parameter Description
Test Conditions
Min.
Typ.
Max.
Unit
V
IL
Low-level Input Voltage
V
DD
= 4.5 5.5V
V
DD
= 3.0 3.6V
0.8
0.2V
DD
V
V
V
IH
High-level Input Voltage
V
DD
= 4.5 5.5V
V
DD
= 3.0 3.6V
2.0
0.7V
DD
V
V
V
OL
Low-level Output Voltage
V
DD
= 4.5 5.5V, I
OL
= 16 mA
V
DD
= 3.0 3.6V, I
OL
= 8 mA
0.4
0.4
V
V
V
OHCMOS
High-level Output Voltage,
CMOS levels
V
DD
= 4.5 5.5V, I
OH
= 16 mA
V
DD
= 3.0 3.6V, I
OH
= 8 mA
V
DD
0.4
V
DD
0.4
V
V
V
OHTTL
High-level Output Voltage,
TTL levels
V
DD
= 4.5 5.5V, I
OH
= 8 mA
2.4
V
I
IL
Input Low Current
V
IN
= 0V
10
µ
A
I
IH
Input High Current
V
IN
= V
DD
5
µ
A
I
DD
Power Supply Current,
Unloaded
V
DD
= 4.5 5.5V, Output frequency <= 133 MHz
V
DD
= 3.0 3.6V, Output frequency <= 100 MHz
45
25
mA
mA
I
DDS
[3]
Stand-by current
(PD = 0)
V
DD
= 4.5 5.5V
V
DD
= 3.0 3.6V
25
10
100
50
µ
A
R
UP
Input Pull-Up Resistor
V
DD
= 4.5 5.5V, V
IN
= 0V
V
DD
= 4.5 5.5V, V
IN
= 0.7V
DD
1.1
50
3.0
100
8.0
200
M
k
I
OE_CLKOUT
CLKOUT Pulldown current V
DD
= 5.0
20
µ
A
Note:
3.
If external reference is used, it is required to stop the reference (set reference to LOW) during power down.
CY2077
Document #: 38-07210 Rev. *A
Page 4 of 13
Output Clock Switching Characteristics Commercial
Over the Operating Range
[4]
Parameter
Description
Test Conditions
Min. Typ. Max. Unit
t
1w
Output Duty Cycle at 1.4V,
V
DD
= 4.5 5.5V
t
1w
= t
1A
÷
t
1B
1 40 MHz, C
L
<= 50 pF
40 125 MHz, C
L
<= 25 pF
125 133 MHz, C
L
<= 15 pF
45
45
45
55
55
55
%
%
%
t
1x
Output Duty Cycle at
V
DD
/2, V
DD
= 4.5 5.5V
t
1x
= t
1A
÷
t
1B
1 40 MHz, C
L
<= 50 pF
40 125 MHz, C
L
<= 25 pF
125 133 MHz, C
L
<= 15 pF
45
45
45
55
55
55
%
%
%
t
1y
Output Duty Cycle at
V
DD
/2, V
DD
= 3.0 3.6V
t
1y
= t
1A
÷
t
1B
1 40 MHz, C
L
<= 30 pF
40 100 MHz, C
L
<= 15 pF
45
40
55
60
%
%
t
2
Output Clock Rise Time
Between 0.8 2.0V, V
DD
= 4.5V 5.5V, C
L
= 50 pF
Between 0.8 2.0V, V
DD
= 4.5V 5.5V, C
L
= 25 pF
Between 0.8 2.0V, V
DD
= 4.5V 5.5V, C
L
= 15 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 4.5V 5.5V, C
L
= 50 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V 3.6V, C
L
= 30 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V 3.6V, C
L
= 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t
3
Output Clock Fall Time
Between 0.8V 2.0V, V
DD
= 4.5V 5.5V, C
L
= 50 pF
Between 0.8 2.0V, V
DD
= 4.5V 5.5V, C
L
= 25 pF
Between 0.8 2.0V, V
DD
= 4.5V 5.5V, C
L
= 15 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 4.5V 5.5V, C
L
= 50 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V 3.6V, C
L
= 30 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V 3.6V, C
L
= 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t
4
Start-Up Time Out of
Power-down
PWR_DWN pin LOW to HIGH
[5]
1
2
ms
t
5a
Power-down Delay Time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T= period of output CLK)
T/2
T +
10
ns
t
5b
Power-down Delay Time
(asynchronous setting)
PWR_DWN pin LOW to output LOW
10
15
ns
t
6
Power-up Time
From power-on
[5]
1
2
ms
t
7a
Output Disable Time
(synchronous setting)
OE pin LOW to output high-Z
(T= period of output CLK)
T/2
T +
10
ns
t
7b
Output Disable Time
(asynchronous setting)
OE pin LOW to output high-Z
10
15
ns
t
8
Output Enable Time
(always synchronous
enable)
OE pin LOW to HIGH
(T= period of output CLK)
T
1.5T
+
25ns
ns
t
9
Peak-to-Peak Period
Jitter
V
DD
= 3.0V 3.6V, 4.5V 5.5V, Fo > 33 MHz, V
CO
> 100 MHz
V
DD
= 3.0V 5.5V, Fo < 33 MHz
80
0.3%
150
1%
ps
% of
F
O
Notes:
4.
Not all parameters measured in production testing.
5.
Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70
.
CY2077
Document #: 38-07210 Rev. *A
Page 5 of 13
Operating Conditions for Industrial Temperature Device
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
3.0
5.5
V
T
A
Operating Temperature, Ambient
40
+85
°C
C
TTL
Max. Capacitive Load on outputs for TTL levels
V
DD
= 4.5 5.5V, Output frequency = 1 40 MHz
V
DD
= 4.5 5.5V, Output frequency = 40 125 MHz
V
DD
= 4.5 5.5V, Output frequency = 125 133 MHz
35
15
10
pF
pF
pF
C
CMOS
Max. Capacitive Load on outputs for CMOS levels
V
DD
= 4.5 5.5V, Output frequency = 1 40 MHz
V
DD
= 4.5 5.5V, Output frequency = 40 125 MHz
V
DD
= 4.5 5.5V, Output frequency = 125 133 MHz
V
DD
= 3.0 3.6V, Output frequency = 1 40 MHz
V
DD
= 3.0 3.6V, Output frequency = 40 100 MHz
35
15
10
20
10
pF
pF
pF
pF
pF
X
REF
Reference Frequency, input crystal with C
load
= 10 pF
10
30
MHz
Reference Frequency, external clock source
1
75
MHz
Electrical Characteristics
T
A
= 40
°
C to +85
°
C
Parameter Description
Test Conditions
Min.
Typ.
Max.
Unit
V
IL
Low-level Input Voltage
V
DD
= 4.5 5.5V
V
DD
= 3.0 3.6V
0.8
0.2V
DD
V
V
V
IH
High-level Input Voltage
V
DD
= 4.5 5.5V
V
DD
= 3.0 3.6V
2.0
0.7V
DD
V
V
V
OL
Low-level Output Voltage
V
DD
= 4.5 5.5V, I
OL
= 16 mA
V
DD
= 3.0 3.6V, I
OL
= 8 mA
0.4
0.4
V
V
V
OHCMOS
High-level Output Voltage,
CMOS levels
V
DD
= 4.5 5.5V, I
OH
= 16 mA
V
DD
= 3.0 3.6V, I
OH
= 8 mA
V
DD
0.4
V
DD
0.4
V
V
V
OHTTL
High-level Output Voltage,
TTL levels
V
DD
= 4.5 5.5V, I
OH
= 8 mA
2.4
V
I
IL
Input Low Current
V
IN
= 0V
10
µ
A
I
IH
Input High Current
V
IN
= V
DD
5
µ
A
I
DD
Power Supply Current,
Unloaded
V
DD
= 4.5 5.5V, Output frequency <= 133 MHz
V
DD
= 3.0 3.6V, Output frequency <= 100 MHz
45
25
mA
mA
I
DDS
[3]
Stand-by current
(PD = 0)
V
DD
= 4.5 5.5V
V
DD
= 3.0 3.6V
25
10
100
50
µ
A
R
UP
Input Pull-Up Resistor
V
DD
= 4.5 5.5V, V
IN
= 0V
V
DD
= 4.5 5.5V, V
IN
= 0.7V
DD
1.1
50
3.0
100
8.0
200
M
k
I
OE_CLKOUT
CLKOUT Pull-down current V
DD
= 5.0
20
µ
A
Output Clock Switching Characteristics Industrial
Over the Operating Range
[4]
Parameter
Description
Test Conditions
Min. Typ.
Max. Unit
t
1w
Output Duty Cycle at
1.4V, V
DD
= 4.5 5.5V
t
1w
= t
1A
÷
t
1B
1 40 MHz, C
L
<= 35 pF
40 125 MHz, C
L
<= 15 pF
125 133 MHz, C
L
<= 10 pF
45
45
45
55
55
55
%
%
%
t
1x
Output Duty Cycle at
V
DD
/2, V
DD
= 4.5 5.5V
t
1x
= t
1A
÷
t
1B
1 40 MHz, C
L
<= 35 pF
40 125 MHz, C
L
<= 15 pF
125 133 MHz, C
L
<= 10 pF
45
45
45
55
55
55
%
%
%
t
1y
Output Duty Cycle at
V
DD
/2, V
DD
= 3.0 3.6V
t
1y
= t
1A
÷
t
1B
1 40 MHz, C
L
<= 20 pF
40 100 MHz, C
L
<= 10 pF
45
40
55
60
%
%
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