Copyright Cirrus Logic, Inc. 2003

Nov '03

DS506PP1

http://www.cirrus.com

High-Performance,

Low-Power System on Chip with

SDRAM and Enhanced Digital

Audio Interface

EP7311 Data Sheet

OVERVIEW

BLOCK DIAGRAM

FEATURES

(cont.)

I ARM720T Processor

-- ARM7TDMI CPU
-- 8 KB of four-way set-associative cache
-- MMU with 64-entry TLB
-- Thumb code support enabled

I Ultra low power

-- 90 mW at 74 MHz typical
-- 30 mW at 18 MHz typical
-- 10 mW in the Idle State
-- <1 mW in the Standby State

I 48 KB of on-chip SRAM
I MaverickKeyTM IDs

-- 32-bit unique ID can be used for SDMI compliance
-- 128-bit random ID

I Dynamically programmable clock speeds of

18, 36, 49, and 74 MHz

LCD

Controller

Boot
ROM

MaverickKey

T M

ARM7TDMI CPU Core

MMU

8 KB

Cache

Write

Buffer

Internal Data Bus

EPB Bus

Memory Controller

SDRAM I/F

SRAM I/F

On-chip SRAM

48 KB

ICE-JTAG

Clocks &

Timers

Keypad&

Touch

Screen I/F

Interrupts,

PWM & GPIO

Bus

Bridge

(2) UARTs

w/ IrDA

Power

Management

Serial

Interface

Multimedia
Codec Port

ARM720T

MEMORY AND STORAGE

INTE

RF
A

The MaverickTM EP7311 is designed for ultra-low-power
applications such as PDAs, smart cellular phones, and
industrial hand held information appliances. The core-
logic functionality of the device is built around an
ARM720T processor with 8 KB of four-way set-
associative unified cache and a write buffer. Incorporated
into the ARM720T is an enhanced memory management
unit (MMU) which allows for support of sophisticated
operating systems like Linux

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

FEATURES

(cont)

I LCD controller

-- Interfaces directly to a single-scan panel

monochrome STN LCD

-- Interfaces to a single-scan panel color STN LCD

with minimal external glue logic

I Full JTAG boundary scan and Embedded ICE

support

I Integrated Peripheral Interfaces

-- 32-bit SDRAM Interface up to 2 external banks
-- 8/32/16-bit SRAM/FLASH/ROM Interface
-- Multimedia Codec Port
-- Two Synchronous Serial Interfaces (SSI1, SSI2)
-- CODEC Sound Interface
-- 8

×8 Keypad Scanner

-- 27 General Purpose Input/Output pins
-- Dedicated LED flasher pin from the RTC

I Internal Peripherals

-- Two 16550 compatible UARTs
-- IrDA Interface
-- Two PWM Interfaces
-- Real-time Clock
-- Two general purpose 16-bit timers

-- Interrupt Controller
-- Boot ROM

I Package

-- 208-Pin LQFP
-- 256-Ball PBGA
-- 204-Ball TFBGA

I The fully static EP7311 is optimized for low power

dissipation and is fabricated on a 0.25 micron CMOS
process

I Development Kits

-- EDB7312: Development Kit with color STN LCD

on board.

-- EDB7312-LW: EDB7312 with Lynuxworks'

BlueCat Linux Tools and software for Windows
host (free 30 day BlueCat support from
Lynuxworks).

-- EDB7312-LL: EDB7312 with Lynuxworks' BlueCat

Linux Tools and software for Linux host (free 30
day BlueCat support from Lynuxworks).

Note:

* BlueCat available separately through Lynuxworks
only.
* Use the EDB7312 Development Kit for all the EP73xx
devices.

OVERVIEW

(cont.)

The EP7311 is designed for low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation
range of 2.5 V3.3 V. The device has three basic power
states: operating, idle and standby.

One of its notable features is MaverickKey unique IDs.
These are factory programmed IDs in response to the
growing concern over secure web content and commerce.
With Internet security playing an important role in the
delivery of digital media such as books or music,
traditional software methods are quickly becoming
unreliable. The MaverickKey unique IDs consist of two
registers, one 32-bit series register and one random 128-
bit register that may be used by an OEM for an
authentication mechanism.

Simply by adding desired memory and peripherals to the
highly integrated EP7311 completes a low-power system
solution. All necessary interface logic is integrated on-
chip.

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

Processor Core - ARM720T

The

EP7311

incorporates

ARM

32-bit

RISC

microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:

· ARM (32-bit) and Thumb (16-bit compressed)

instruction sets

· Enhanced MMU for Microsoft Windows CE and other

operating systems

· 8 KB of 4-way set-associative cache.
· Translation Look Aside Buffers with 64 Translated

Entries

Power Management

The EP7311 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:

· Operating -- This state is the full performance

state. All the clocks and peripheral logic are
enabled.

· Idle -- This state is the same as the Operating

State, except the CPU clock is halted while
waiting for an event such as a key press.

· Standby -- This state is equivalent to the

computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.

MaverickKey

Unique ID

MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure

Digital Music Initiative) or any other authentication
mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7311 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7311 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today's
Internet appliances.

Memory Interfaces

There are two main external memory interfaces. The first
one is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-
mode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-
bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory.

further

minimize

system

memory

requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density.

Note:

Pins are multiplexed. See

Table S on page 8

for more

information.

Pin Mnemonic

I/O

Pin Description

BATOK

Battery ok input

nEXTPWR

External power supply sense
input

nPWRFL

Power fail sense input

nBATCHG

Battery changed sense input

Table A. Power Management Pin Assignments

Pin Mnemonic

I/O

Pin Description

nCS[5:0]

Chip select out

A[27:0]

Address output

D[31:0]

I/O

Data I/O

nMOE/nSDCAS

(Note)

ROM expansion OP enable

nMWE/nSDWE

(Note)

ROM expansion write enable

HALFWORD

Halfword access select
output

WORD

Word access select output

WRITE/nSDRAS

(Note)

Transfer direction

Table B. Static Memory Interface Pin Assignments

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

The second is the programmable 16- or 32-bit-wide
SDRAM interface that allows direct connection of up to
two banks of SDRAM, totaling 512 Mb. To assure the
lowest

possible

power

consumption,

the

EP7311

supports self-refresh SDRAMs, which are placed in a
low-power state by the device when it enters the low-
power Standby State.

Note:

1. Pins A[27:13] map to DRA[0:14] respectively.

(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to

balance the load for large memory systems.
2. Pins are multiplexed. See

Table S on page 8

for

more information.

Digital Audio Capability

The EP7311 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7311

Universal Asynchronous
Receiver/Transmitters (UARTs)

The EP7311 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the

RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.

Multimedia Codec Port (MCP)

The Multimedia Codec Port provides access to an audio
codec, a telecom codec, a touchscreen interface, four
general purpose analog-to-digital converter inputs, and
ten programmable digital I/O lines.

Note:

See

Table R on page 8

for information on pin

multiplexes.

Pin Mnemonic

I/O

Pin Description

SDCLK

SDRAM clock output

SDCKE

SDRAM clock enable output

nSDCS[1:0]

SDRAM chip select out

WRITE/nSDRAS

(Note 2)

SDRAM RAS signal output

nMOE/nSDCAS

(Note 2)

SDRAM CAS control signal

nMWE/nSDWE

(Note 2)

SDRAM write enable control
signal

A[27:15]/DRA[0:12]

(Note 1)

SDRAM address

A[14:13]/DRA[12:14]

SDRAM internal bank select

PD[7:6]/SDQM[1:0]

(Note 2)

I/O

SDRAM byte lane mask

SDQM[3:2]

SDRAM byte lane mask

D[31:0]

I/O

Data I/O

Table C. SDRAM Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

TXD[1]

UART 1 transmit

RXD[1]

UART 1 receive

CTS

UART 1 clear to send

DCD

UART 1 data carrier detect

DSR

UART 1 data set ready

TXD[2]

UART 2 transmit

RXD[2]

UART 2 receive

LEDDRV

Infrared LED drive output

PHDIN

Photo diode input

Table D. Universal Asynchronous Receiver/Transmitters Pin

Assignments

Pin Mnemonic

I/O

Pin Description

SIBCLK

Serial bit clock

SIBDOUT

Serial data out

SIBDIN

Serial data in

SIBSYNC

Sample clock

Table E. MCP Interface Pin Assignments

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

CODEC Interface

The EP7311 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the MCP and
SSI2.

Note:

See

Table R on page 8

for information on pin

multiplexes.

SSI2 Interface

An additional SPI/Microwire1-compatible interface is
available

for

both

master

and

slave

mode

communications. The SSI2 unit shares the same pins as
the MCP and CODEC interfaces through a multiplexer.

· Synchronous clock speeds of up to 512 kHz
· Separate 16 entry TX and RX half-word wide FIFOs
· Half empty/full interrupts for FIFOs
· Separate RX and TX frame sync signals for

asymmetric traffic

Note:

See

Table R on page 8

for information on pin

multiplexes.

Synchronous Serial Interface

· ADC (SSI) Interface: Master mode only; SPI and

Microwire1-compatible (128 kbps operation)

· Selectable serial clock polarity

LCD Controller

A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.

· Interfaces directly to a single-scan panel monochrome

STN LCD

· Interfaces to a single-scan panel color STN LCD with

minimal external glue logic

· Panel width size is programmable from 32 to 1024

pixels in 16-pixel increments

· Video frame buffer size programmable up to

128 KB

· Bits per pixel of 1, 2, or 4 bits

Pin Mnemonic

I/O

Pin Description

PCMCLK

Serial bit clock

PCMOUT

Serial data out

PCMIN

Serial data in

PCMSYNC

Frame sync

Table F. CODEC Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

SSICLK

I/O

Serial bit clock

SSITXDA

Serial data out

SSIRXDA

Serial data in

SSITXFR

I/O

Transmit frame sync

SSIRXFR

I/O

Receive frame sync

Table G. SSI2 Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

ADCLK

SSI1 ADC serial clock

ADCIN

SSI1 ADC serial input

ADCOUT

SSI1 ADC serial output

nADCCS

SSI1 ADC chip select

SMPCLK

SSI1 ADC sample clock

Table H. Serial Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

CL1

LCD line clock

CL2

LCD pixel clock out

DD[3:0]

LCD serial display data bus

FRM

LCD frame synchronization pulse

LCD AC bias drive

Table I. LCD Interface Pin Assignments

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

64-Keypad Interface

Matrix keyboards and keypads can be easily read by the
EP7311. A dedicated 8-bit column driver output
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
selectively OR'ed together to provide a keyboard
interrupt that is capable of waking the system from a
STANDBY or IDLE state.

· Column outputs can be individually set high with the

remaining bits left at high-impedance

· Column outputs can be driven all-low, all-high, or all-

high-impedance

· Keyboard interrupt driven by OR'ing together all Port

A bits

· Keyboard interrupt can be used to wake up the

system

· 8

×8 keyboard matrix usable with no external logic,

extra keys can be added with minimal glue logic

Interrupt Controller

When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7311 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.

· Supports 22 interrupts from a variety of sources (such

as UARTs, SSI1, and key matrix.)

· Routes interrupt sources to the ARM720T's IRQ or

FIQ (Fast IRQ) inputs

· Five dedicated off-chip interrupt lines operate as level

sensitive interrupts

Note:

Pins are multiplexed. See

Table S on page 8

for more

information.

Real-Time Clock

The EP7311 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
register which can be programmed to generate an
interrupt.

· Driven by an external 32.768 kHz crystal oscillator

PLL and Clocking

· Processor and Peripheral Clocks operate from a single

3.6864 MHz crystal or external 13 MHz clock

· Programmable clock speeds allow the peripheral bus

to run at 18 MHz when the processor is set to 18 MHz
and at 36 MHz when the processor is set to 36, 49 or
74 MHz

Pin Mnemonic

I/O

Pin Description

COL[7:0]

Keyboard scanner column drive

Table J. Keypad Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

nEINT[2:1]

External interrupt

EINT[3]

External interrupt

nEXTFIQ

External Fast Interrupt input

nMEDCHG/nBROM

(Note)

Media change interrupt input

Table K. Interrupt Controller Pin Assignments

Pin Mnemonic

Pin Description

RTCIN

Real-Time Clock Oscillator Input

RTCOUT

Real-Time Clock Oscillator Output

VDDRTC

Real-Time Clock Oscillator Power

VSSRTC

Real-Time Clock Oscillator Ground

Table L. Real-Time Clock Pin Assignments

Pin Mnemonic

Pin Description

MOSCIN

Main Oscillator Input

MOSCOUT

Main Oscillator Output

VDDOSC

Main Oscillator Power

VSSOSC

Main Oscillator Ground

Table M. PLL and Clocking Pin Assignments

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

DC-to-DC converter interface (PWM)

· Provides two 96 kHz clock outputs with

programmable duty ratio (from 1-in-16 to 15-in-16)
that can be used to drive a positive or negative DC to
DC converter

Timers

· Internal (RTC) timer
· Two internal 16-bit programmable hardware count-

down timers

General Purpose Input/Output (GPIO)

· Three 8-bit and one 3-bit GPIO ports
· Supports scanning keyboard matrix

Note:

Pins are multiplexed. See

Table S on page 8

for more

information.

Hardware debug Interface

· Full JTAG boundary scan and Embedded ICE

support

LED Flasher

A dedicated LED flasher module can be used to generate
a low frequency signal on Port D pin 0 for the purpose of
blinking an LED without CPU intervention. The LED
flasher feature is ideal as a visual annunciator in battery
powered applications, such as a voice mail indicator on a
portable phone or an appointment reminder on a PDA.

· Software adjustable flash period and duty cycle
· Operates from 32 kHz RTC clock
· Will continue to flash in IDLE and STANDBY states
· 4 mA drive current

Note:

Pins are multiplexed. See

Table S on page 8

for more

information.

Internal Boot ROM

The internal 128 byte Boot ROM facilitates download of
saved code to the on-board SRAM/FLASH.

Packaging

The EP7311 is available in a 208-pin LQFP package, 256-
ball PBGA package or a 204-ball TFBGA package.

Pin Mnemonic

I/O

Pin Description

DRIVE[1:0]

I/O

PWM drive output

FB[1:0]

PWM feedback input

Table N. DC-to-DC Converter Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

PA[7:0]

I/O

GPIO port A

PB[7:0]

I/O

GPIO port B

PD[0]/LEDFLSH

(Note)

I/O

GPIO port D

PD[5:1]

I/O

GPIO port D

PD[7:6]/SDQM[1:0]

(Note)

I/O

GPIO port D

PE[1:0]/BOOTSEL[1:0] (Note)

I/O

GPIO port E

PE[2]/CLKSEL

(Note)

I/O

GPIO port E

Table O. General Purpose Input/Output Pin Assignments

Pin Mnemonic

I/O

Pin Description

TCLK

JTAG clock

TDI

JTAG data input

TDO

JTAG data output

nTRST

JTAG async reset input

TMS

JTAG mode select

Table P. Hardware Debug Interface Pin Assignments

Pin Mnemonic

I/O

Pin Description

PD[0]/LEDFLSH

(Note)

LED flasher driver

Table Q. LED Flasher Pin Assignments

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

Pin Multiplexing

The following table shows the pin multiplexing of the
MCP, SSI2 and the CODEC. The selection between SSI2
and the CODEC is controlled by the state of the SERSEL
bit in SYSCON2. The choice between the SSI2, CODEC,
and the MCP is controlled by the MCPSEL bit in
SYSCON3 (see the EP73xx User's Manual for more
information).

The following table shows the pins that have been
multiplexed in the EP7311.

Pin

Mnemonic

I/O

MCP

SSI2

CODEC

SSICLK

I/O

SIBCLK

SSICLK PCMCLK

SSITXDA

SIBDOUT

SSITXDA

PCMOUT

SSIRXDA

SIBDIN

SSIRXDA

PCMIN

SSITXFR

I/O

SIBSYNC

SSITXFR

PCMSYNC

SSIRXFR

p/u

SSIRXFR

p/u

BUZ

Table R. MCP/SSI2/CODEC Pin Multiplexing

Signal

Block

Signal

Block

nMOE

Static Memory

nSDCAS

SDRAM

nMWE

Static Memory

nSDWE

SDRAM

WRITE

Static Memory

nSDRAS

SDRAM

A[27:15]

Static Memory

DRA[0:12]

SDRAM

A[14:13]

Static Memory

DRA[13:14]

SDRAM

PD[7:6]

GPIO

SDQM[1:0]

SDRAM

RUN

System
Configuration

CLKEN

System
Configuration

nMEDCHG

Interrupt
Controller

nBROM

Boot ROM
select

PD[0]

GPIO

LEDFLSH

LED Flasher

PE[1:0]

GPIO

BOOTSEL[1:0]

System
Configuration

PE[2]

GPIO

CLKSEL

System
Configuration

Table S. Pin Multiplexing

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

System Design

As shown in system block diagram, simply adding
desired memory and peripherals to the highly integrated

EP7311 completes a low-power system solution. All
necessary interface logic is integrated on-chip.

Figure 1. A Maximum EP7311 Based System

Note:

A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or MCP.

LCD

KEYBOARD

BATTERY

DC-TO-DC

CONVERTERS

ADC

DIGITIZER

IR LED AND

PHOTODIODE

× RS-232

TRANSCEIVERS

ADDITIONAL I/O

PC CARD

CONTROLLER

PC CARD

SOCKET

nCS[4]
PB0
EXPCLK

DD[0-3]

CL1
CL2

FRM

D[0-31]

A[0-27]

COL[0-7]

PA[0-7]

INPUT

nMOE
WRITE

PB[0-7]

PD[0-7]

PE[0-2]

nPOR

nPWRFL

BATOK

nEXTPWR
nBATCHG

RUN

WAKEUP

nCS[0]
nCS[1]

DRIVE[0-1]

FB[0-1]

EP731

ADCCLK

nADCCS

ADCOUT

ADCIN

SMPCLK

LEDDRV

PHDIN

RXD1/2

TXD1/2

DSR

CTS

DCD

CS[n]
WORD

nCS[2]
nCS[3]

×16

FLASH

×16

FLASH

×16

FLASH

EXTERNAL MEMORY-
MAPPED EXPANSION

BUFFERS

AND

LATCHES

×16

FLASH

POWER

SUPPLY UNIT

AND

COMPARATORS

CRYSTAL

CODEC/SSI2/

MCP

SSICLK

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

RTCIN

LEDFLSH

CRYSTAL

MOSCIN

×16

SDRAM

×16

SDRAM

×16

SDRAM

×16

SDRAM

SDCS[1]

SDQM[0-3]

SDCS[0]

SDQM[0-3]

SDRAS/

SDCAS

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Recommended Operating Conditions

DC Characteristics

All characteristics are specified at V

DDCORE

= 2.5 V, V

DDIO

= 3.3 V and V

= 0 V over an operating temperature of 0°C

to +70°C for all frequencies of operation. The current consumption figures have test conditions specified per
parameter."

DC Core, PLL, and RTC Supply Voltage

2.9 V

DC I/O Supply Voltage (Pad Ring)

3.6 V

DC Pad Input Current

±10 mA/pin; ±100 mA cumulative

Storage Temperature, No Power

°C to +125°C

DC core, PLL, and RTC Supply Voltage

2.5 V

± 0.2 V

DC I/O Supply Voltage (Pad Ring)

2.3 V - 3.5 V

DC Input / Output Voltage

OI/O supply voltage

Operating Temperature

Extended -20

°C to +70°C; Commercial 0°C to +70°C;

Industrial -40

°C to +85°C

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

VIH

CMOS input high voltage

0.65

× V

DDIO

+ 0.3

DDIO

= 2.5 V

VIL

CMOS input low voltage

- 0.3

0.25

× V

DDIO

= 2.5 V

VT+

Schmitt trigger positive going
threshold

2.1

VT-

Schmitt trigger negative going
threshold

0.8

Vhst

Schmitt trigger hysteresis

0.1

0.4

VIL to VIH

VOH

CMOS output high voltage

Output drive 1

Output drive 2

0.2

2.5
2.5

-
-
-

V
V
V

IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA

VOL

CMOS output low voltage

Output drive 1

Output drive 2

-
-
-

0.3
0.5
0.5

V
V
V

IOL = 0.1 mA
IOL = 4 mA
IOL = 12 mA

IIN

Input leakage current

1.0

µA

VIN = V

or GND

IOZ

Bidirectional 3-state leakage

current

b c

100

µA

VOUT = V

or GND

CIN

Input capacitance

10.0

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

Note:

1) Total power consumption = IDD

CORE

x 2.5 V + IDD

x 3.3 V

2) A typical design will provide 3.3 V to the I/O supply (i.e., V

DDIO

), and 2.5 V to the remaining logic. This is to allow the I/O to be

compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).

2) Pull-up current = 50 µA typical at V

= 3.3 V.

COUT

Output capacitance

10.0

CI/O

Transceiver capacitance

10.0

IDD

STANDBY

@ 25 C

Standby current consumption

Core, Osc, RTC @2.5 V
I/O @ 3.3 V

-
-

77
41

-
-

µA

Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V

± 0.1 V,

VIL = GND ± 0.1 V

IDD

STANDBY

@ 70 C

Standby current consumption

Core, Osc, RTC @2.5 V
I/O @ 3.3 V

-
-

570
111

µA

Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V

± 0.1 V,

VIL = GND ± 0.1 V

IDD

STANDBY

@ 85 C

Standby current consumption

Core, Osc, RTC @2.5 V
I/O @ 3.3 V

-
-

1693

163

µA

Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V

± 0.1 V,

VIL = GND ± 0.1 V

IDD

idle

at 74 MHz

Idle current consumption

Core, Osc, RTC @2.5 V
I/O @ 3.3 V

-
-

Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V

± 0.1 V, VIL

= GND ± 0.1 V

VDD

STANDBY

Standby supply voltage

2.0

Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only

Refer to the strength column in the pin assignment tables for all package types.

Assumes buffer has no pull-up or pull-down resistors.

The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

Timings

Timing Diagram Conventions

This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any
variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless
specifically stated.

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are
specified at V

DDIO

= 3.1 - 3.5 V and V

= 0 V over an operating temperature of -40

°C to +85°C. Pin loadings is 50 pF.

The timing values are referenced to 1/2 V

C l o c k

H i g h t o L o w

H i g h / L o w t o H i g h

B u s C h a n g e

B u s V a l i d

U n d e f i n e d / I n v a l i d

V a l i d B u s t o T r i s t a t e

B u s / S i g n a l O m i s s i o n

Figure 2. Legend for Timing Diagrams

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

SDRAM Interface

Figure 3

through

Figure 6

define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter

Symbol

Min

Typ

Max

Unit

SDCLK rising edge to SDCS assert delay time

CSa

SDCLK rising edge to SDCS deassert delay time

CSd

- 3

SDCLK rising edge to SDRAS assert delay time

RAa

SDCLK rising edge to SDRAS deassert delay time

RAd

- 3

SDCLK rising edge to SDRAS invalid delay time

RAnv

SDCLK rising edge to SDCAS assert delay time

CAa

- 2

SDCLK rising edge to SDCAS deassert delay time

CAd

- 5

SDCLK rising edge to ADDR transition time

ADv

- 3

SDCLK rising edge to ADDR invalid delay time

ADx

- 2

SDCLK rising edge to SDMWE assert delay time

MWa

- 2

SDCLK rising edge to SDMWE deassert delay time

MWd

- 4

DATA transition to SDCLK rising edge time

DAs

SDCLK rising edge to DATA transition hold time

DAh

SDCLK rising edge to DATA transition delay time

DAd

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

Static Memory

Figure 7

through

Figure 10

define the timings associated with all phases of the Static Memory. The following table

contains the values for the timings of each of the Static Memory modes.

Parameter

Symbol

Min

Typ

Max

Unit

EXPCLK rising edge to nCS assert delay time

CSd

EXPCLK falling edge to nCS deassert hold time

CSh

EXPCLK rising edge to A assert delay time

EXPCLK falling edge to A deassert hold time

EXPCLK rising edge to nMWE assert delay time

MWd

EXPCLK rising edge to nMWE deassert hold time

MWh

EXPCLK falling edge to nMOE assert delay time

MOEd

EXPCLK falling edge to nMOE deassert hold time

MOEh

EXPCLK falling edge to HALFWORD deassert delay time

HWd

EXPCLK falling edge to WORD assert delay time

WDd

EXPCLK rising edge to data valid delay time

EXPCLK falling edge to data invalid delay time

Dnv

Data setup to EXPCLK falling edge time

EXPCLK falling edge to data hold time

EXPCLK rising edge to WRITE assert delay time

WRd

EXPREADY setup to EXPCLK falling edge time

EXs

EXPCLK falling edge to EXPREADY hold time

EXh

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

Static Memory Single Read Cycle

Note:

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.

EXPCLK

nCS

nMWE

HALF-

WORD

WRITE

nMOE

CSd

CSh

MOEh

HWd

WDd

WRd

MOEd

EXPRDY

EXh

EXs

Figure 7. Static Memory Single Read Cycle Timing Measurement

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

Static Memory Single Write Cycle

Note:

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with

valid timing under zero wait state conditions.

3. Address, Data, Halfword, Word, and Write hold state until next cycle.

EXPCLK

nCS

nMWE

HALF-

WORD

WRITE

HWd

WDd

CSd

MWd

MWh

CSh

nMOE

EXPRDY

EXh

EXs

Figure 8. Static Memory Single Write Cycle Timing Measurement

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

Static Memory Burst Read Cycle

Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive

cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.

EXPCLK

nCS

nMOE

HALF

WORD

nMWE

EXPRDY

WRITE

CSd

CSh

MOEh

MOEd

EXs

EXh

WRd

HWd

WDd

Figure 9. Static Memory Burst Read Cycle Timing Measurement

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

Static Memory Burst Write Cycle

Note:

1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.

EXPCLK

nCS

nMOE

HALF

WORD

nMWE

EXPRDY

WRITE

CSd

MWd

MWh

MWd

MWh

EXs

EXh

CSh

Dnv

HWd

WDd

Figure 10. Static Memory Burst Write Cycle Timing Measurement

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

SSI2 Interface

Parameter

Symbol

Min

Max

Unit

SSICLK period (slave mode)

clk_per

185

2050

SSICLK high time

clk_high

925

1025

SSICLK low time

clk_low

925

1025

SSICLK rise/fall time

clkrf

SSICLK rising edge to RX and/or TX frame sync high time

FRd

SSICLK rising edge to RX and/or TX frame sync low time

FRa

SSIRXFR and/or SSITXFR period

FR_per

960

990

SSIRXDA setup to SSICLK falling edge time

RXs

SSIRXDA hold from SSICLK falling edge time

RXh

SSICLK rising edge to SSITXDA data valid delay time

TXd

SSITXDA valid time

TXv

960

990

SSI

CLK

SSIRXFR/

SSITXFR

SSI

TXDA

SSI

RXDA

clk_per

clk_high

clk_low

FRd

FR_per

RXs

TXd

FRa

RXh

clkrf

TXv

Figure 12. SSI2 Interface Timing Measurement

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

Packages

208-Pin LQFP Package Characteristics

208-Pin LQFP Package Specifications

Note:

1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see

Figure 16

. For pin descriptions see the EP7311 User's Manual.

Figure 15. 208-Pin LQFP Package Outline Drawing

Pin 1 Indicator

29.60 (1.165)
30.40 (1.197)

0.17 (0.007)
0.27 (0.011)

27.80 (1.094)
28.20 (1.110)

0.50

(0.0197)

BSC

29.60 (1.165)
30.40 (1.197)

27.80 (1.094)
28.20 (1.110)

1.35 (0.053)
1.45 (0.057)

° MIN

° MAX

0.09 (0.004)
0.20 (0.008)

1.40 (0.055)

0.45 (0.018)
0.75 (0.030)

0.05 (0.002)

1.00 (0.039) BSC

Pin 1

Pin 208

1.60 (0.063)

0.15 (0.006)

EP7311

208-Pin LQFP

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

208-Pin LQFP Pin Diagram

Note:

1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7211 and the EP7311 are bolded.

160

159

158

157

106

107

108

109

120

121

100

101

102

103

104

122

124

125

126

127

128

129

130

105

131

132

133

134

156

155

154

153

152

151

150

149

148

147

146

145

144

143

140

139

138

137

136

141

142

135

161
162
163
164
165
166
167
168
169
170
171
172
173
174

180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199

201
202
203
204
205
206
207
208

200

175
176
177
178
179

123

EP7311

208-Pin LQFP

(Top View)

VSSOSC

VDDOSC

MOSCIN

MOSCOUT

URE

WAKEUP

A[6]
D[6]
A[5]
D[5]

VDDIO

VSSIO

A[4]

D[4]

A[3]
D[3]

nPWRFL

A[2]

D[2]
A[1]

A[0]
D[0]

VDDCORE

VSSIO

VDDIO

CL[2]
CL[1]

FRM

DD[2]

DD[1]
DD[0]

nSDCS[1]

SDQM[3]
SDQM[2]

VDDIO

VSSIO

SDCLK

nMWE/nSDWE

nMOE/nSDCAS

nCS[0]

nCS[1]
nCS[2]

nCS[3]

D[7

]

D[8

]

D[9

]

D[1

]

[
10]

SSI

I
O

[
11]

D[1

]

[
12]

D[1

]

[
13]

\
D

[
14]

D[1

]

DD[3]

D[1

]

D[1

]

[
17]

/DRA

]

SSI

I
O

D[1

]

/DRA

]

D[1

]

[
19]

/DRA

]

D[2

]

SSI

[
21]

/DRA

]

D[2

]

D[2

]

[
23]

/DRA

]

D[2

]

SSI

I
O

[
24]

/DRA

]

[
14]

/
D

[
13]

CHG

A[25]/DRA[2]

D[25]

D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]

ADCOUT
ADCCLK
DRIVE[0]

VDDIO

PD[2]

VSSIO

VSSCORE
nADCCS
ADCIN

SSIRXDA

SSIRXFR

SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]

PD[3]

[
22]

/DRA

]

PD[4]

VDDIO

PD[5]
PD[6]/SDQM[0]

DRIVE[1]

PD[7]/SDQM[1]

D[26]

[
15]

/DRA

]

D[1

]

[
16]

/DRA

]

nCS[4]

VDDCORE

A[26]/DRA[1]

D[2

]

TMS

[
20]

/DRA

]

SMPCLK

D[1

]

D[1]

VSSCORE

nSDCS[0]

SDCKE

SSI

VSSIO

EXP

I
T

/
n

DRAS

[
7

]

[
6

]

[
5

]

[
4

]

[
3

]

[
2

]

[
1

]

SSI

DDI

PE[

]
/
C

KSE

I
Q

[
6

]

[
5

]

[
4

]

[
3

]

[
2

]

[
1

]

[
0

]

DRV

[
2

]

HDIN

]

CIN

VSS

I
O

[
7

]

DDI

VSSI

[
5]

[
0

]

[
1

]

D[1

]

EST

[
1

]

EST

[
0

]

[
3

]

I
N

[
2]

I
N

[
1]

]

N/C

VSSR

DDRT

Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

DCHG

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

208-Pin LQFP Numeric Pin Listing

Table T. 208-Pin LQFP Numeric Pin Listing

Pin
No.

Signal

Type

Strength

Reset

State

nCS[5]

Low

VDDIO

Pad Pwr

VSSIO

Pad Gnd

EXPCLK

I/O

WORD

Out

Low

WRITE/nSDRAS

Out

Low

RUN/CLKEN

O 1

Low

EXPRDY

TXD[2]

1 High

RXD[2]

TDI

with p/u*

VSSIO

Pad Gnd

PB[7]

I/O

Input

PB[6]

I/O

Input

PB[5]

I/O

Input

PB[4]

I/O

Input

PB[3]

I/O

Input

PB[2]

I/O

Input

PB[1]/PRDY2

I/O

Input

PB[0]/PRDY1

I/O

Input

VDDIO

Pad Pwr

TDO

Three state

PA[7]

I/O

Input

PA[6]

I/O

Input

PA[5]

I/O

Input

PA[4]

I/O

Input

PA[3]

I/O

Input

PA[2]

I/O

Input

PA[1]

I/O

Input

PA[0]

I/O

Input

LEDDRV

Low

TXD[1]

High

VSSIO

Pad Gnd

High

PHDIN

CTS

RXD[1]

DCD

DSR

nTEST[1]

With p/u*

nTEST[0]

With p/u*

EINT[3]

nEINT[2]

nEINT[1]

nEXTFIQ

PE[2]/CLKSEL

I/O

1 Input

PE[1]/

BOOTSEL[1]

I/O

Input

PE[0]/

BOOTSEL[0]

I/O

Input

VSSRTC

RTC Gnd

RTCOUT

RTCIN

VDDRTC

RTC power

N/C

PD[7]/SDQM[1]

I/O

Low

PD[6]/SDQM[0]

I/O

Low

PD[5]

I/O

Low

PD[4]

I/O

Low

VDDIO

Pad Pwr

TMS

with p/u*

PD[3]

I/O

Low

PD[2]

I/O

Low

PD[1]

I/O

Low

PD[0]/LEDFLSH

I/O

Low

SSICLK

I/O

Input

VSSIO

Pad Gnd

SSITXFR

I/O

Low

SSITXDA

Low

SSIRXDA

SSIRXFR

I/O

Input

ADCIN

nADCCS

High

VSSCORE

Core Gnd

VDDCORE

Core Pwr

VSSIO

Pad Gnd

Table T. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

Signal

Type

Strength

Reset

State

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

VDDIO

Pad Pwr

DRIVE[1]

I/O 2

High /

Low

DRIVE[0]

I/O 2

High /

Low

ADCCLK

Low

ADCOUT

Low

SMPCLK

Low

FB[1]

VSSIO

Pad Gnd

FB[0]

COL[7]

High

COL[6]

High

COL[5]

High

COL[4]

High

COL[3]

High

COL[2]

High

VDDIO

Pad Pwr

TCLK

COL[1]

High

COL[0]

High

BUZ

Low

D[31]

I/O

Low

D[30]

I/O

Low

D[29]

I/O

Low

D[28]

I/O

Low

VSSIO

Pad Gnd

A[27]/DRA[0]

Low

100

D[27]

I/O

Low

101

A[26]/DRA[1]

Low

102

D[26]

I/O

Low

103

A[25]/DRA[2]

Low

104

D[25]

I/O

Low

105

HALFWORD

Low

106

A[24]/DRA[3]

Low

107

VDDIO

Pad Pwr

108

VSSIO

Pad Gnd

109

D[24]

I/O

Low

110

A[23]/DRA[4]

Low

Table T. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

Signal

Type

Strength

Reset

State

111

D[23]

I/O

Low

112

A[22]/DRA[5]

Low

113

D[22]

I/O

Low

114

A[21]/DRA[6]

Low

115

D[21]

I/O

Low

116

VSSIO

Pad Gnd

117

A[20]/DRA[7]

Low

118

D[20]

I/O

Low

119

A[19]/DRA[8]

Low

120

D[19]

I/O

Low

121

A[18]/DRA[9]

Low

122

D[18]

I/O

Low

123

VDDIO

Pad Pwr

124

VSSIO

Pad Gnd

125

nTRST

126

A[17]/DRA[10]

Low

127

D[17]

I/O

Low

128

A[16]/DRA[11]

Low

129

D[16]

I/O

Low

130

A[15]/DRA[12]

Low

131

D[15]

I/O

Low

132

A[14]/DRA[13]

Low

133

D[14]

I/O

Low

134

A[13]/DRA[14]

Low

135

D[13]

I/O

Low

136

A[12]

Low

137

D[12]

I/O

Low

138

A[11]

Low

139

VDDIO

Pad Pwr

140

VSSIO

Pad Gnd

141

D[11]

I/O

Low

142

A[10]

Low

143

D[10]

I/O

Low

144

A[9]

Low

145

D[9]

I/O

Low

146

A[8]

Low

147

D[8]

I/O

Low

148

A[7]

Low

Table T. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

Signal

Type

Strength

Reset

State

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

*With p/u' means with internal pull-up on the pin.

149

VSSIO

Pad Gnd

150

D[7]

I/O

Low

151

nBATCHG

152

nEXTPWR

153

BATOK

154

nPOR

Schmitt

155

nMEDCHG/

nBROM

156

nURESET

Schmitt

157

VDDOSC

Osc Pwr

158

MOSCIN

Osc

159

MOSCOUT

Osc

160

VSSOSC

Osc Gnd

161

WAKEUP

Schmitt

162

nPWRFL

163

A[6]

Low

164

D[6]

I/O

Low

165

A[5]

Out

Low

166

D[5]

I/O

Low

167

VDDIO

Pad Pwr

168

VSSIO

Pad Gnd

169

A[4]

Low

170

D[4]

I/O

Low

171

A[3]

Low

172

D[3]

I/O

Low

173

A[2]

Low

174

VSSIO

Pad Gnd

175

D[2]

I/O

Low

176

A[1]

Low

177

D[1]

I/O

Low

178

A[0]

Low

179

D[0]

I/O

Low

180

VSS CORE

Core Gnd

181

VDD CORE

Core Pwr

182

VSSIO

Pad Gnd

183

VDDIO

Pad Pwr

184

CL[2]

Low

185

CL[1]

Low

186

FRM

Low

Table T. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

Signal

Type

Strength

Reset

State

187

Low

188

DD[3]

I/O

Low

189

DD[2]

I/O

Low

190

VSSIO

Pad Gnd

191

DD[1]

I/O

Low

192

DD[0]

I/O

Low

193

nSDCS[1]

High

194

nSDCS[0]

High

195

SDQM[3]

I/O

Low

196

SDQM[2]

I/O

Low

197

VDDIO

Pad Pwr

198

VSSIO

Pad Gnd

199

SDCKE

I/O

Low

200

SDCLK

I/O

Low

201

nMWE/nSDWE

High

202

nMOE/nSDCAS

High

203

VSSIO

Pad Gnd

204

nCS[0]

High

205

nCS[1]

High

206

nCS[2]

High

207

nCS[3]

High

208

nCS[4]

High

Table T. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

Signal

Type

Strength

Reset

State

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

204-Ball TFBGA Package Characteristics

204-Ball TFBGA Package Specifications

Figure 17. 204-Ball TFBGA Package

Ø0.25~0.35(204X)

Ø0.15 M C A B

Ø0.08 M C

0.15(4X) C

0.20

.30

1.20

SEATING PLANE

0.36

0.53±

0.05

0.20

TOP VIEW

BOTTOM VIEW

13±0.05

13±

0.05

0.10

Ball Diameter :

Ball Pitch :

0.53

0.3

Substrate Thickness :

Mold Thickness :

0.65

0.36

0.65

19 18 17 16 15 14 13 12 11 10 9 8

7 6 5 4 3

2 1

12.35

0.65

19 20

14 15

12 13

9 10 11

7 8

2 3

A1 CORNER

12.35

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

204-Ball TFBGA Pinout (Top View)

A VDDIO EXPCLK nCS3

nCS1

nMWE/

nSDWE

SDQM2 nSDCS1

DD2

FRM

CL1

GNDCOR

nPWRFL MOSCOUT GNDIO

GNDIO

B WORD

VDDIO

nCS5

nCS2

nMOE/

nSDCAS

SDCKE nSDCS0

DD1

CL2

WAKEUP MOSCIN

GNDIO

GNDIO nURESET B

RUN/

CLKEN

EXPRDY VDDIO

nCS4

nCS0

SDCLK SDQM3

DD0

DD3

VDDCO

GNDOS

VDDOSC

GNDIO

BATOK

nPOR

PB7

RXD2

VDDIO

GNDIO

nBATCHG

PB4

TXD2

WRITE/

nSDRAS

nMEDCHG

/nBROM

nEXTPWR

PB3

PB6

TDI

D10

PB1/

PRDY2

PB2

PB5

D11

PA7

TDO

PB0/

PRDY1

A10

D12

A12

PA4

PA5

PA6

A11

D13

A13/

DRA14

PA1

PA2

VDDIO

D14

A14/

DRA13

D15

TXD1 LEDDRV

PA3

VDDIO

D16

A16/

DRA11

RXD1

CTS

PA0

A15/

DRA12

A17/

DRA10

nTRST M

DSR

nTEST1 PHDIN

D17

D19

A18/

DRA9

EINT3

nEINT2

DCD

D18

A20/

DRA7

D20

R nEXTFIQ

PE2/

CLKSEL

nTEST0

A19/

DRA8

D22

A21/

DRA6

PE1/

BOOT

SEL1

PE0/

BOOT

SEL0

nEINT1

D21

D23

A22/

DRA5

U GNDRTCRTCOUT RTCIN

HALF

WORD

D24

A23/

DRA4

V VDDRTC GNDIO GNDIO

PD7/

SDQM1

PD4

PD2

SSICLK SSIRXDA nADCCS VDDIO ADCCLK

COL7

COL4

TCLK

BUZ

D29

A26/

DRA1

VDDIO

A24/

DRA3

W GNDIO

GNDIO GNDIO

PD6/SD

QM0

TMS

PD1

SSITXFR SSIRXFR

GNDCO

DRIVE1 ADCOUT

FB0

COL5

COL2

COL0

D30

A27/

DRA0

D26

VDDIO

D25

Y GNDIO

GNDIO GNDIO

PD5

PD3

PD0/

LED

FLSH

SSITXDA ADCIN

VDDCO

DRIVE0 SMPLCK

FB1

COL6

COL3

COL1

D31

D28

D27

A25/

DRA2

VDDIO

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

204-Ball TFBGA Ball Listing

The list is ordered by ball location.

Table 21. 204-Ball TFBGA Ball Listing

Ball Location

Name

Strength

Reset

State

Type

Description

VDDIO

Pad power

Digital I/O power,
3.3 V

EXPCLK

Expansion clock
input

nCS[3]

High

Chip select 3

nCS[1]

High

Chip select 1

nMWE/nSDWE

High

ROM, expansion
write enable/
SDRAM write enable
control signal

SDQM[2]

Low

SDRAM byte lane
mask

nSDCS[1]

High

SDRAM chip select
2

DD[2]

Low

LCD serial display
data

FRM

Low

LCD frame
synchronization
pulse

A10

CL[1]

Low

LCD line clock

A11

VSSCORE

Core ground

A12

D[1]

Low

I/O

Data I/O

A13

A[2]

Low

System byte address

A14

D[4]

Low

I/O

Data I/O

A15

A[5]

Low

System byte address

A16

nPWRFL

Power fail sense
input

A17

MOSCOUT

Main oscillator out

A18

VSSIO

Pad ground

I/O ground

A19

VSSIO

Pad ground

I/O ground

A20

VSSIO

Pad ground

I/O ground

WORD

Low

Word access select
output

VDDIO

Pad power

Digital I/O power, 3.3
V

nCS[5]

Low

Chip select 5

nCS[2]

High

Chip select 2

nMOE/nSDCAS

High

ROM, expansion OP
enable/SDRAM CAS
control signal

SDCKE

Low

SDRAM clock
enable output

nSDCS[0]

High

SDRAM chip select
0

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

DD[1]

Low

LCD serial display
data

Low

LCD AC bias drive

B10

CL[2]

Low

LCD pixel clock out

B11

D[0]

Low

I/O

Data I/O

B12

A[1]

Low

System byte address

B13

D[3]

Low

I/O

Data I/O

B14

A[4]

Low

System byte address

B15

D[6]

Low

I/O

Data I/O

B16

WAKEUP

Schmitt

System wake up
input

B17

MOSCIN

Main oscillator input

B18

VSSIO

Pad ground

I/O ground

B19

VSSIO

Pad ground

I/O ground

B20

nURESET

Schmitt

User reset input

RUN/CLKEN

Low

Run output / clock
enable output

EXPRDY

Expansion port
ready input

VDDIO

Pad power

Digital I/O power,
3.3 V

nCS[4]

High

Chip select 4

nCS[0]

High

Chip select 0

SDCLK

Low

SDRAM clock out

SDQM[3]

Low

SDRAM byte lane
mask

DD[0]

Low

LCD serial display
data

DD[3]

Low

LCD serial display
data

C10

VDDCORE

Core power

Digital core power,
2.5 V

C11

A[0]

Low

System byte address

C12

D[2]

Low

I/O

Data I/O

C13

A[3]

Low

System byte address

C14

D[5]

Low

I/O

Data I/O

C15

A[6]

Low

System byte address

C16

VSSOSC

Oscillator ground

PLL ground

C17

VDDOSC

Oscillator power

Oscillator power in,
2.5V

C18

VSSIO

Pad ground

I/O ground

C19

BATOK

Battery ok input

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

C20

nPOR

Schmitt

Power-on reset input

PB[7]

Input

GPIO port B

RXD[2]

UART 2 receive data
input

VDDIO

Pad power

Digital I/O power,
3.3V

D18

VSSIO

Pad ground

I/O ground

D19

nBATCHG

Battery changed
sense input

D20

A[7]

Low

System byte address

PB[4]

Input

GPIO port B

TXD[2]

High

UART 2 transmit
data output

WRITE/nSDRAS

Low

Transfer direction /
SDRAM RAS signal
output

E18

nMEDCHG/nBROM

Media change
interrupt input /
internal ROM boot
enable

E19

nEXTPWR

External power
supply sense input

E20

D[9]

Low

I/O

Data I/O

PB[3]

Input

I/O

GPIO port B

PB[6]

Input

I/O

GPIO port B

TDI

with p/u*

JTAG data input

F18

D[7]

Low

I/O

Data I/O

F19

A[8]

Low

System byte address

F20

D[10]

Low

I/O

Data I/O

PB[1]

Input

I/O

PB[2]

Input

I/O

GPIO port B

PB[5]

Input

I/O

GPIO port B

G18

D[8]

Input

I/O

Data I/O

G19

A[9]

Low

System byte address

G20

D[11]

Low

I/O

Data I/O

PA[7]

Input

I/O

GPIO port A

H[2]

TDO

Input

JTAG data out

H[3]

PB[0]

Input

I/O

GPIO port B

H[18]

A[10]

Low

System byte address

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

H19

D[12]

Low

I/O

Data I/O

H20

A[12]

Low

System byte address

PA[4]

Input

I/O

GPIO port A

PA[5]

Input

I/O

GPIO port A

PA[6]

Input

I/O

GPIO port A

J18

A[11]

Low

System byte address

J19

D[13]

Low

I/O

Data I/O

J20

A[13]/DRA[14]

Low

System byte address
/ SDRAM address

PA[1]

Input

I/O

GPIO port A

PA[2]

Input

I/O

GPIO port A

VDDIO

Pad power

Digital I/O power,
3.3V

K18

D[14]

Low

I/O

Data I/O

K19

A[14]/DRA[13]

Low

System byte address
/ SDRAM address

K20

D[15]

Low

I/O

Data I/O

TXD[1]

High

UART 1 transmit
data out

LEDDRV

Low

IR LED drive

PA[3]

Input

I/O

GPIO port A

L18

VDDIO

Pad power

Digital I/O power,
3.3V

L19

D[16]

Low

I/O

Data I/O

L20

A[16]/DRA[11]

Low

System byte address
/ SDRAM address

RXD[1]

UART 1 receive data
input

CTS

UART 1 clear to
send input

PA[0]

Input

I/O

GPIO port A

M18

A[15]/DRA[12]

Low

System byte address
/ SDRAM address

M19

A[17]/DRA[10]

Low

System byte address
/ SDRAM address

M20

nTRST

JTAG async reset
input

DSR

UART 1 data set
ready input

nTEST[1]

With p/u*

Test mode select
input

PHDIN

Photodiode input

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

N18

D[17]

Low

I/O

Data I/O

N19

D[19]

Low

I/O

Data I/O

N20

A[18]/DRA[9]

Low

System byte address
/ SDRAM address

EINT[3]

External interrupt

nEINT[2]

External interrupt
input

DCD

UART 1 data carrier
detect

P18

D[18]

Low

I/O

Data I/O

P19

A[20]/DRA[7]

Low

System byte address
/ SDRAM address

P20

D[20]

Low

I/O

Data I/O

nEXTFIQ

External fast
interrupt input

PE[2]/CLKSEL

Input

I/O

GPIO port E / clock
input mode select

nTEST[0]

With p/u*

Test mode select

input

R18

A[19]/DRA[8]

Low

System byte address
/ SDRAM address

R19

D[22]

Low

I/O

Data I/O

R20

A[21]/DRA[6]

Low

System byte address
/ SDRAM address

PE[1]/BOOTSEL[1]

Input

I/O

GPIO port E / boot
mode select

PE[0]/BOOTSEL[0]

Input

I/O

GPIO port E / boot
mode select

nEINT[1]

External interrupt
input

T18

D[21]

Low

I/O

Data I/O

T19

D[23]

Low

I/O

Data I/O

T20

A[22]/DRA[5]

Low

System byte address
/ SDRAM address

VSSRTC

RTC ground

Real time clock
ground

RTCOUT

Real time clock
oscillator output

RTCIN

I/O

Real time clock
oscillator input

U18

HALFWORD

Low

Halfword access
select output

U19

D[24]

Low

I/O

Data I/O

U20

A[23]/DRA[4]

Low

System byte address
/ SDRAM address

VDDRTC

RTC power

Real time clock
power, 2.5V

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

PD[7]/SDQM[1]

Low

I/O

GPIO port D /
SDRAM byte lane
mask

PD[4]

Low

I/O

GPIO port D

PD[2]

Low

I/O

GPIO port D

SSICLK

Input

I/O

DAI/CODEC/SSI2
serial clock

SSIRXDA

I/O

DAI/CODEC/SSI2
serial data input

nADCCS

High

SSI1 ADC chip
select

V10

VDDIO

Pad power

Digital I/O power,
3.3V

V11

ADCCLK

Low

SSI1 ADC serial
clock

V12

COL[7]

High

Keyboard scanner
column drive

V13

COL[4]

High

Keyboard scanner
column drive

V14

TCLK

JTAG clock

V15

BUZ

Low

Buzzer drive output

V16

D[29]

Low

I/O

Data I/O

V17

A[26]/DRA[1]

Low

System byte address
/ SDRAM address

V18

VDDIO

Pad power

Digital I/O power,
3.3 V

V19

VDDIO

Pad power

Digital I/O power,
3.3 V

V20

A[24]/DRA[3]

Low

System byte address
/ SDRAM address

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

PD[6]/SDQM[0]

Low

I/O

GPIO port D /
SDRAM byte lane
mask

TMS

with p/u*

JTAG mode select

PD[1]

Low

I/O

GPIO port D

SSITXFR

Low

I/O

DAI/CODEC/SSI2
frame sync

SSIRXFR

Input

I/O

DAI/CODEC/SSI2
frame sync

VSSCORE

Core Ground

W10

DRIVE[1]

High /

Low

I/O

PWM drive output

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

W11

ADCOUT

Low

SSI1 ADC serial
data output

W12

FB[0]

PWM feedback input

W13

COL[5]

High

Keyboard scanner
column drive

W14

COL[2]

High

Keyboard scanner
column drive

W15

COL[0]

High

Keyboard scanner
column drive

W16

D[30]

Low

I/O

Data I/O

W17

A[27]/DRA[0]

Low

System byte address
/ SDRAM address

W18

D[26]

Low

I/O

Data I/O

W19

VDDIO

Pad power

Digital I/O power,
3.3V

W20

D[25]

Low

I/O

Data I/O

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

PD[5]

Low

I/O

GPIO port D

PD[3]

Low

I/O

GPIO port D

PD[0]/LEDFLSH

Low

I/O

GPIO port D / LED
blinker output

SSITXDA

Low

DAI/CODEC/SSI2
serial data output

ADCIN

SSI1 ADC serial
input

VDDCORE

Core power

Digital core power,
2.5V

Y10

DRIVE[0]

Input

I/O

PWM drive output

Y11

SMPCLK

Low

SSI1 ADC sample
clock

Y12

FB[1]

PWM feedback input

Y13

COL[6]

High

Keyboard scanner
column drive

Y14

COL[3]

High

Keyboard scanner
column drive

Y15

COL[1]

High

Keyboard scanner
column drive

Y16

D[31]

Low

I/O

Data I/O

Y17

D[28]

Low

I/O

Data I/O

Y18

D[27]

Low

I/O

Data I/O

Y19

A[25]/DRA[2]

Low

System byte address
/ SDRAM address

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

"With p/u" means with internal pull-up of 100 KOhms on the pin.

Strength 1 = 4 ma

Strength 2 = 12 ma

Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.

256-Ball PBGA Package Characteristics

256-Ball PBGA Package Specifications

Figure 18. 256-Ball PBGA Package

Note:

1) For pin locations see

Table V

2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information.

256-Ball PBGA Pinout (Top View)

Y20

VDDIO

Pad power

Digital I/O power,
3.3V

VDDIO

nCS[4]

nCS[1]

SDCLK

SDQM[3]

DD[1]

VDDIO

D[0]

D[2]

A[3]

VDDIO

A[6]

MOSCOUT VDDOSC

VSSIO

nCS[5]

VDDIO

nCS[3]

nMOE/

nSDCAS

VDDIO

nSDCS[1]

DD[2]

CL[1]

VDDCORE

D[1]

A[2]

A[4]

A[5]

WAKEUP

VDDIO

nURESET B

VDDIO

EXPCLK

VSSIO

VDDIO

VSSIO

VDDIO

VSSIO

VDDIO

VSSIO

nPOR

nEXTPWR C

WRITE/

nSDRAS

EXPRDY

VSSIO

VDDIO

nCS[2]

nMWE/

nSDWE

nSDCS[0]

CL[2]

VSSRTC

D[4]

nPWRFL

MOSCIN

VDDIO

VSSIO

D[7]

D[8]

RXD[2]

PB[7]

TDI

WORD

VSSIO

nCS[0]

SDQM[2]

FRM

A[0]

D[5]

VSSOSC

VSSIO

nMEDCHG/

nBROM

VDDIO

D[9]

D[10]

PB[5]

PB[3]

VSSIO

TXD[2]

RUN/

CLKEN

VSSIO

SDCKE

DD[3]

A[1]

D[6]

VSSRTC

BATOK

nBATCHG

VSSIO

D[11]

VDDIO

PB[1]

VDDIO

TDO

PB[4]

PB[6]

VSSRTC

DD[0]

D[3]

VSSRTC

A[7]

A[8]

A[9]

VSSIO

D[12]

D[13]

PA[7]

PA[5]

VSSIO

PA[4]

PA[6]

PB[0]

PB[2]

VSSRTC

A[10]

A[11]

A[12]

A[13]/

DRA[14]

VSSIO

D[14]

D[15]

PA[3]

PA[1]

VSSIO

PA[2]

PA[0]

TXD[1]

CTS

VSSRTC

A[17]/

DRA[10]

A[16]/

DRA[11]

A[15]/

DRA[12]

A[14]/

DRA[13]

nTRST

D[16]

D[17]

K LEDDRV

PHDIN

VSSIO

DCD

nTEST[1]

EINT[3]

VSSRTC

ADCIN

COL[4]

TCLK

D[20]

D[19]

D[18]

VSSIO

VDDIO

RXD[1]

DSR

VDDIO

nEINT[1]

PE[2]/

CLKSEL

VSSRTC

PD[0]/

LEDFLSH

VSSRTC

COL[6]

D[31]

VSSRTC

A[22]/

DRA[5]

A[21]/

DRA[6]

VSSIO

A[18]/

DRA[9]

A[19]/

DRA[8]

M nTEST[0]

nEINT[2]

VDDIO

PE[0]/

BOOTSEL[0]

TMS

VDDIO

SSITXFR

DRIVE[1]

FB[0]

COL[0]

D[27]

VSSIO

A[23]/

DRA[4]

VDDIO

A[20]/

DRA[7]

D[21]

N nEXTFIQ

PE[1]/

BOOTSEL[1]

VSSIO

VDDIO

PD[5]

PD[2]

SSIRXDA

ADCCLK

SMPCLK

COL[2]

D[29]

D[26]

HALFWORD

VSSIO

D[22]

D[23]

P VSSRTC

RTCOUT

VSSIO

VDDIO

VSSIO

VDDIO

VSSIO

VDDIO

VSSIO

VDDIO

VSSIO

D[24]

VDDIO

RTCIN

VDDIO

PD[4]

PD[1]

SSITXDA

nADCCS

VDDIO

ADCOUT

COL[7]

COL[3]

COL[1]

D[30]

A[27]/

DRA[0]

A[25]/

DRA[2]

VDDIO

A[24]\

DRA[3]

T VDDRTC

PD[7]/

SDQM[1]

PD[6]/

SDQM[0]

PD[3]

SSICLK

SSIRXFR VDDCORE DRIVE[0]

FB[1]

COL[5]

VDDIO

BUZ

D[28]

A[26]/

DRA[1]

D[25]

VSSIO

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

Reset

State

Type

Description

Copyright Cirrus Logic, Inc. 2003

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

TOP VIEW

17.00 (0.669)

15.00 (0.590)

SIDE VIEW

BOTTOM VIEW

A
B
C
D
E
F

G
H

M
N

P
R
T

1.00 (0.040)

Pin 1 Indicator

Pin 1 Corner

16 15 14 13 12 11 10 9

15.00 (0.590)

2 Layer

17.00 (0.669)

1.00 (0.040)

30° TYP

REF

0.50

3 Places

0.85 (0.034)
±0.05 (.002)

0.40 (0.016)
±0.05 (.002)

0.36 (0.014)

17.00 (0.669)

±0.20 (.008)

±0.09 (0.004)

JEDEC #: MO-151
Ball Diameter: 0.50 mm ± 0.10 mm
17 ¥ 17 ¥ 1.61 mm body

DS506PP1

Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

256-Ball PBGA Ball Listing

The list is ordered by ball location.

Table V. 256-Ball PBGA Ball Listing

Ball Location

Name

Type

Description

VDDIO

Pad power

Digital I/O power, 3.3V

nCS[4]

Chip select out

nCS[1]

Chip select out

SDCLK

SDRAM clock out

SDQM[3]

SDRAM byte lane mask

DD[1]

LCD serial display data

LCD AC bias drive

VDDIO

Pad power

Digital I/O power, 3.3V

D[0]

I/O

Data I/O

A10

D[2]

I/O

Data I/O

A11

A[3]

System byte address

A12

VDDIO

Pad power

Digital I/O power, 3.3V

A13

A[6]

System byte address

A14

MOSCOUT

Main oscillator out

A15

VDDOSC

Oscillator

power

Oscillator power in, 2.5V

A16

VSSIO

Pad ground

I/O ground

nCS[5]

Chip select out

VDDIO

Pad power

I/O ground

nCS[3]

Chip select out

B4 nMOE/nSDCAS

ROM, expansion OP enable/SDRAM
CAS control signal

VDDIO

Pad power

Digital I/O power, 3.3V

nSDCS[1]

SDRAM chip select out

DD[2]

LCD serial display data

CL[1]

LCD line clock

VDDCORE

Core power

Digital core power, 2.5V

B10

D[1]

I/O

Data I/O

B11

A[2]

System byte address

B12

A[4]

System byte address

B13

A[5]

System byte address

B14

WAKEUP

System wake up input

B15

VDDIO

Pad power

Digital I/O power, 3.3V

B16

nURESET

User reset input

VDDIO

Pad power

Digital I/O power, 3.3V

EXPCLK

Expansion clock input

VSSIO

Pad ground

I/O ground

VDDIO

Pad power

Digital I/O power, 3.3V

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

VDDIO

Pad power

Digital I/O power, 3.3V

VSSIO

Pad ground

I/O ground

C10

VSSIO

Pad ground

I/O ground

C11

VSSIO

Pad ground

I/O ground

C12

VDDIO

Pad power

Digital I/O power, 3.3V

C13

VSSIO

Pad ground

I/O ground

C14

VSSIO

Pad ground

I/O ground

C15

nPOR

Power-on reset input

C16

nEXTPWR

External power supply sense input

D1 WRITE/nSDRAS

Transfer direction / SDRAM RAS signal
output

EXPRDY

Expansion port ready input

VSSIO

Pad ground

I/O ground

VDDIO

Pad power

Digital I/O power, 3.3V

nCS[2]

Chip select out

D6 nMWE/nSDWE

ROM, expansion write enable/ SDRAM
write enable control signal

nSDCS[0]

SDRAM chip select out

CL[2]

LCD pixel clock out

VSSRTC

Core ground Real time clock ground

D10

D[4]

I/O

Data I/O

D11

nPWRFL

Power fail sense input

D12

MOSCIN

Main oscillator input

D13

VDDIO

Pad power

Digital I/O power, 3.3V

D14

VSSIO

Pad ground

I/O ground

D15

D[7]

I/O

Data I/O

D16

D[8]

I/O

Data I/O

RXD[2]

UART 2 receive data input

PB[7]

GPIO port B

TDI

JTAG data input

WORD

Word access select output

VSSIO

Pad ground

I/O ground

nCS[0]

Chip select out

SDQM[2]

SDRAM byte lane mask

FRM

LCD frame synchronization pulse

A[0]

System byte address

E10

D[5]

I/O

Data I/O

E11

VSSOSC

Oscillator

ground

PLL ground

E12

VSSIO

Pad ground

I/O ground

E13

nMEDCHG/nBROM

Media change interrupt input / internal
ROM boot enable

E14

VDDIO

Pad power

Digital I/O power, 3.3V

E15

D[9]

I/O

Data I/O

E16

D[10]

I/O

Data I/O

PB[5]

GPIO port B

PB[3]

GPIO port B

VSSIO

Pad ground

I/O ground

TXD[2]

UART 2 transmit data output

RUN/CLKEN

Run output / clock enable output

VSSIO

Pad ground

I/O ground

Table V. 256-Ball PBGA Ball Listing (Continued)

Ball Location

Name

Type

Description

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

SDCKE

SDRAM clock enable output

DD[3]

LCD serial display data

A[1]

System byte address

F10

D[6]

I/O

Data I/O

F11

VSSRTC

RTC ground Real time clock ground

F12

BATOK

Battery ok input

F13

nBATCHG

Battery changed sense input

F14

VSSIO

Pad ground

I/O ground

F15

D[11]

I/O

Data I/O

F16

VDDIO

Pad power

Digital I/O power, 3.3V

PB[1]

GPIO port B

VDDIO

Pad power

Digital I/O power, 3.3V

TDO

JTAG data out

PB[4]

GPIO port B

PB[6]

GPIO port B

VSSRTC

Core ground Real time clock ground

VSSRTC

RTC ground Real time clock ground

DD[0]

LCD serial display data

D[3]

I/O

Data I/O

G10

VSSRTC

RTC ground Real time clock ground

G11

A[7]

System byte address

G12

A[8]

System byte address

G13

A[9]

System byte address

G14

VSSIO

Pad ground

I/O ground

G15

D[12]

I/O

Data I/O

G16

D[13]

I/O

Data I/O

PA[7]

GPIO port A

PA[5]

GPIO port A

VSSIO

Pad ground

I/O ground

PA[4]

GPIO port A

PA[6]

GPIO port A

PB[0]

GPIO port B

PB[2]

GPIO port B

VSSRTC

RTC ground Real time clock ground

VSSRTC

RTC ground Real time clock ground

H10

A[10]

System byte address

H11

A[11]

System byte address

H12

A[12]

System byte address

H13

A[13]/DRA[14]

System byte address / SDRAM address

H14

VSSIO

Pad ground

I/O ground

H15

D[14]

I/O

Data I/O

H16

D[15]

I/O

Data I/O

PA[3]

GPIO port A

PA[1]

GPIO port A

VSSIO

Pad ground

I/O ground

PA[2]

GPIO port A

PA[0]

GPIO port A

TXD[1]

UART 1 transmit data out

Table V. 256-Ball PBGA Ball Listing (Continued)

Ball Location

Name

Type

Description

CTS

UART 1 clear to send input

VSSRTC

RTC ground Real time clock ground

VSSRTC

RTC ground Real time clock ground

J10

A[17]/DRA[10]

System byte address / SDRAM address

J11

A[16]/DRA[11]

System byte address / SDRAM address

J12

A[15]/DRA[12]

System byte address / SDRAM address

J13

A[14]/DRA[13]

System byte address / SDRAM address

J14

nTRST

JTAG async reset input

J15

D[16]

I/O

Data I/O

J16

D[17]

I/O

Data I/O

LEDDRV

IR LED drivet

PHDIN

Photodiode input

VSSIO

Pad ground

I/O ground

DCD

UART 1 data carrier detect

nTEST[1]

Test mode select input

EINT[3]

External interrupt

VSSRTC

RTC ground Real time clock ground

ADCIN

SSI1 ADC serial input

COL[4]

Keyboard scanner column drive

K10

TCLK

JTAG clock

K11

D[20]

I/O

Data I/O

K12

D[19]

I/O

Data I/O

K13

D[18]

I/O

Data I/O

K14

VSSIO

Pad ground

I/O ground

K15

VDDIO

Pad power

Digital I/O power, 3.3V

K16

VDDIO

Pad power

Digital I/O power, 3.3V

RXD[1]

UART 1 receive data input

DSR

UART 1 data set ready input

VDDIO

Pad power

Digital I/O power, 3.3V

nEINT[1]

External interrupt input

PE[2]/CLKSEL

GPIO port E / clock input mode select

VSSRTC

RTC ground Real time clock ground

PD[0]/LEDFLSH

I/O

GPIO port D / LED blinker output

VSSRTC

Core ground Real time clock ground

COL[6]

Keyboard scanner column drive

L10

D[31]

I/O

Data I/O

L11

VSSRTC

RTC ground Real time clock ground

L12

A[22]/DRA[5]

System byte address / SDRAM address

L13

A[21]/DRA[6]

System byte address / SDRAM address

L14

VSSIO

Pad ground

I/O ground

L15

A[18]/DRA[9]

System byte address / SDRAM address

L16

A[19]/DRA[8]

System byte address / SDRAM address

nTEST[0]

Test mode select input

nEINT[2]

External interrupt input

VDDIO

Pad power

Digital I/O power, 3.3V

PE[0]/BOOTSEL[0]

GPIO port E / Boot mode select

TMS

JTAG mode select

VDDIO

Pad power

Digital I/O power, 3.3V

Table V. 256-Ball PBGA Ball Listing (Continued)

Ball Location

Name

Type

Description

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

SSITXFR

I/O

MCP/CODEC/SSI2 frame sync

DRIVE[1]

I/O

PWM drive output

FB[0]

PWM feedback input

M10

COL[0]

Keyboard scanner column drive

M11

D[27]

I/O

Data I/O

M12

VSSIO

Pad ground

I/O ground

M13

A[23]/DRA[4]

System byte address / SDRAM address

M14

VDDIO

Pad power

Digital I/O power, 3.3V

M15

A[20]/DRA[7]

System byte address / SDRAM address

M16

D[21]

I/O

Data I/O

nEXTFIQ

External fast interrupt input

PE[1]/BOOTSEL[1]

GPIO port E / boot mode select

VSSIO

Pad ground

I/O ground

VDDIO

Pad power

Digital I/O power, 3.3V

PD[5]

I/O

GPIO port D

PD[2]

I/O

GPIO port D

SSIRXDA

I/O

MCP/CODEC/SSI2 serial data input

ADCCLK

SSI1 ADC serial clock

SMPCLK

SSI1 ADC sample clock

N10

COL[2]

Keyboard scanner column drive

N11

D[29]

I/O

Data I/O

N12

D[26]

I/O

Data I/O

N13

HALFWORD

Halfword access select output

N14

VSSIO

Pad ground

I/O ground

N15

D[22]

I/O

Data I/O

N16

D[23]

I/O

Data I/O

VSSRTC

RTC ground Real time clock ground

RTCOUT

Real time clock oscillator output

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

VDDIO

Pad power

Digital I/O power, 3.3V

VSSIO

Pad ground

I/O ground

VSSIO

Pad ground

I/O ground

VDDIO

Pad power

Digital I/O power, 3.3V

VSSIO

Pad ground

I/O ground

P10

VDDIO

Pad power

Digital I/O power, 3.3V

P11

VSSIO

Pad ground

I/O ground

P12

VSSIO

Pad ground

I/O ground

P13

VDDIO

Pad power

Digital I/O power

P14

VSSIO

Pad ground

I/O ground

P15

D[24]

I/O

Data I/O

P16

VDDIO

Pad power

Digital I/O power, 3.3V

RTCIN

I/O

Real time clock oscillator input

VDDIO

Pad power

Digital I/O power, 3.3V

PD[4]

I/O

GPIO port D

PD[1]

I/O

GPIO port D

SSITXDA

MCP/CODEC/SSI2 serial data output

nADCCS

SSI1 ADC chip select

Table V. 256-Ball PBGA Ball Listing (Continued)

Ball Location

Name

Type

Description

VDDIO

Pad power

Digital I/O power, 3.3V

ADCOUT

SSI1 ADC serial data output

COL[7]

Keyboard scanner column drive

R10

COL[3]

Keyboard scanner column drive

R11

COL[1]

Keyboard scanner column drive

R12

D[30]

I/O

Data I/O

R13

A[27]/DRA[0]

System byte address / SDRAM address

R14

A[25]/DRA[2]

System byte address / SDRAM address

R15

VDDIO

Pad power

Digital I/O power, 3.3V

R16

A[24]/DRA[3]

System byte address / SDRAM address

VDDRTC

RTC power

Real time clock power, 2.5V

PD[7]/SDQM[1]

I/O

GPIO port D / SDRAM byte lane mask

PD[6]/SDQM[0]

I/O

GPIO port D / SDRAM byte lane mask

PD[3]

I/O

GPIO port D

SSICLK

I/O

MCP/CODEC/SSI2 serial clock

T6 SSIRXFR

MCP/CODEC/SSI2 frame sync

VDDCORE

Core power Core power, 2.5V

DRIVE[0]

I/O

PWM drive output

FB[1]

PWM feedback input

T10

COL[5]

Keyboard scanner column drive

T11

VDDIO

Pad power

Digital I/O power, 3.3V

T12

BUZ

Buzzer drive output

T13

D[28]

I/O

Data I/O

T14

A[26]/DRA[1]

System byte address / SDRAM address

T15

D[25]

I/O

Data I/O

T16

VSSIO

Pad ground

I/O ground

Table V. 256-Ball PBGA Ball Listing (Continued)

Ball Location

Name

Type

Description

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

JTAG Boundary Scan Signal Ordering

Table W. JTAG Boundary Scan Signal Ordering

LQFP

Pin No.

TFBGA

Ball

PBGA

Ball

Signal

Type

Position

nCS[5]

EXPCLK

I/O

WORD

WRITE/nSDRAS

RUN/CLKEN

EXPRDY

TXD2

RXD2

PB[7]

I/O

PB[6]

I/O

PB[5]

I/O

PB[4]

I/O

PB[3]

I/O

PB[2]

I/O

PB[1]/PRDY2

I/O

PB[0]/PRDY1

I/O

PA[7]

I/O

PA[6]

I/O

PA[5]

I/O

PA[4]

I/O

PA[3]

I/O

PA[2]

I/O

PA[1]

I/O

PA[0]

I/O

LEDDRV

TXD1

PHDIN

CTS

RXD1

DCD

DSR

nTEST1

nTEST0

EINT3

nEINT2

nEINT1

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

nEXTFIQ

PE[2]/CLKSEL

I/O

PE[1]/BOOTSEL1

I/O

PE[0]/BOOTSEL0

I/O

PD[7]/SDQM[1]

I/O

PD[6/SDQM[0]]

I/O

PD[5]

I/O

PD[4]

I/O

PD[3]

I/O

101

PD[2]

I/O

104

PD[1]

I/O

107

PD[0]/LEDFLSH

110

SSIRXFR

I/O

122

ADCIN

125

nADCCS

126

DRIVE1

I/O

128

DRIVE0

I/O

131

W10

ADCCLK

134

Y10

ADCOUT

136

V11

SMPCLK

138

W11

FB1

140

Y11

FB0

141

Y12

COL7

142

W12

COL6

144

V12

T10

COL5

146

Y13

COL4

148

W13

R10

COL3

150

V13

N10

COL2

152

Y14

R11

COL1

154

W14

M10

COL0

156

T12

BUZ

158

V14

L10

D[31]

I/O

160

Y15

R12

D[30]

I/O

163

W15

N11

D[29]

I/O

166

V15

T13

D[28]

I/O

169

Y16

R13

A[27]/DRA[0]

Out

172

100

W16

M11

D[27]

I/O

174

101

V16

T14

A[26]/DRA[1]

177

Table W. JTAG Boundary Scan Signal Ordering (Continued)

LQFP

Pin No.

TFBGA

Ball

PBGA

Ball

Signal

Type

Position

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

102

Y17

N12

D[26]

I/O

179

103

W17

R14

A[25]/DRA[2]

182

104

Y18

T15

D[25]

I/O

184

105

V17

N13

HALFWORD

187

106

W18

R16

A[24]/DRA[3]

189

109

Y19

P15

D[24]

I/O

191

110

W20

M13

A[23]/DRA[4]

194

111

U18

N16

D[23]

I/O

196

112

V20

L12

A[22]/DRA[5]

199

113

U19

N15

D[22]

I/O

201

114

U20

L13

A[21]/DRA[6]

204

115

T19

M16

D[21]

I/O

206

117

T20

M15

A[20]/DRA[7]

209

118

R19

K11

D[20]

I/O

211

119

R20

L16

A[19]/DRA[8]

214

120

T18

K12

D[19]

I/O

216

121

P19

L15

A[18]/DRA[9]

219

122

P20

K13

D[18]

I/O

221

126

R18

J10

A[17]/DRA[10]

224

127

N19

J16

D[17]

I/O

226

128

N20

J11

A[16]/DRA[11]

229

129

P18

J15

D[16]

I/O

231

130

M19

J12

A[15]/DRA[12]

234

131

N18

H16

D[15]

I/O

236

132

L20

J13

A[14]/DRA[13]

239

133

L19

H15

D[14]

I/O

241

134

M18

H13

A[13]/DRA[14]

244

135

K20

G16

D[13]

I/O

246

136

K19

H12

A[12]

249

137

K18

G15

D[12]

I/O

251

138

J20

H11

A[11]

254

141

J19

F15

D[11]

I/O

256

142

H20

H10

A[10]

259

143

H19

E16

D[10]

I/O

261

144

J18

G13

A[9]

264

145

E15

D[9]

I/O

266

146

G12

A[8]

269

147

G20

D16

D[8]

I/O

271

Table W. JTAG Boundary Scan Signal Ordering (Continued)

LQFP

Pin No.

TFBGA

Ball

PBGA

Ball

Signal

Type

Position

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

148

H18

G11

A[7]

274

150

F20

D15

D[7]

I/O

276

151

G19

F13

nBATCHG

279

152

E20

C16

nEXTPWR

280

153

F19

F12

BATOK

281

154

G18

C15

nPOR

282

155

D20

E13

nMEDCHG/nBROM

283

156

F18

B16

nURESET

284

161

D19

B14

WAKEUP

285

162

E19

D11

nPWRFL

286

163

C19

A13

A[6]

287

164

C20

F10

D[6]

I/O

289

165

E18

B13

A[5]

292

166

B20

E10

D[5]

I/O

294

169

B16

B12

A[4]

297

170

A16

D10

D[4]

I/O

299

171

C15

A11

A[3]

302

172

B15

D[3]

I/O

304

173

A15

B11

A[2]

307

175

C14

A10

D[2]

I/O

309

176

B14

A[1]

312

177

A14

B10

D[1]

I/O

314

178

C13

A[0]

317

179

B13

D[0]

I/O

319

184

A13

CL2

322

185

C12

CL1

324

186

B12

FRM

326

187

A12

328

188

C11

DD[3]

I/O

330

189

B11

DD[2]

I/O

333

191

B10

DD[1]

I/O

336

192

A10

DD[0]

I/O

339

193

nSDCS[1]

342

194

nSDCS[0]

344

195

SDQM[3]

I/O

346

196

SDQM[2]

I/O

349

199

SDCKE

I/O

352

200

SDCLK

I/O

355

Table W. JTAG Boundary Scan Signal Ordering (Continued)

LQFP

Pin No.

TFBGA

Ball

PBGA

Ball

Signal

Type

Position

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

CONVENTIONS

This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.

Acronyms and Abbreviations

Table X lists abbreviations and acronyms used in this
data sheet.

Units of Measurement

Table X. Acronyms and Abbreviations

Acronym/

Abbreviation

Definition

A/D

analog-to-digital

ADC

analog-to-digital converter

CODEC

coder / decoder

D/A

digital-to-analog

DMA

direct-memory access

EPB

embedded peripheral bus

FCS

frame check sequence

FIFO

first in / first out

FIQ

fast interrupt request

GPIO

general purpose I/O

ICT

in circuit test

infrared

IRQ

standard interrupt request

IrDA

Infrared Data Association

JTAG

Joint Test Action Group

LCD

liquid crystal display

LED

light-emitting diode

LQFP

low profile quad flat pack

LSB

least significant bit

MIPS

millions of instructions per second

MMU

memory management unit

MSB

most significant bit

PBGA

plastic ball grid array

PCB

printed circuit board

PDA

personal digital assistant

PLL

phase locked loop

p/u

pull-up resistor

RISC

reduced instruction set computer

RTC

Real-Time Clock

SIR

slow (9600115.2 kbps) infrared

SRAM

static random access memory

SSI

synchronous serial interface

TAP

test access port

TLB

translation lookaside buffer

UART

universal asynchronous receiver

Table Y. Unit of Measurement

Symbol

Unit of Measure

degree Celsius

sample frequency

hertz (cycle per second)

kbps

kilobits per second

kilobyte (1,024 bytes)

kHz

kilohertz

kilohm

Mbps

megabits (1,048,576 bits) per second

megabyte (1,048,576 bytes)

MBps

megabytes per second

MHz

megahertz (1,000 kilohertz)

microampere

microfarad

microwatt

microsecond (1,000 nanoseconds)

milliampere

milliwatt

millisecond (1,000 microseconds)

nanosecond

volt

watt

Table X. Acronyms and Abbreviations (Continued)

Acronym/

Abbreviation

Definition

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

General Conventions

Hexadecimal numbers are presented with all letters in
uppercase and a lowercase "h" appended or with a 0x at
the beginning. For example, 0x14 and 03CAh are
hexadecimal numbers. Binary numbers are enclosed in
single quotation marks when in text (for example, `11'
designates a binary number). Numbers not indicated by
an "h", 0x or quotation marks are decimal.

Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example,
CODR[7:0]), and are described in the EP7311 User's
Manual. The use of "TBD" indicates values that are "to
be determined," "n/a" designates "not available," and
"n/c" indicates a pin that is a "no connect."

Pin Description Conventions

Abbreviations used for signal directions are listed in
Table Z.

Table Z. Pin Description Conventions

Abbreviation

Direction

Input

Output

I/O

Input or Output

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

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Part Number EP7311

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